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1. 发明授权

US08549384B1 Method and apparatus for determining, based on an error correction code, one or more locations to store data in a flash memory 有权
标题翻译：用于基于纠错码确定将数据存储在闪速存储器中的一个或多个位置的方法和装置
公开(公告)号：US08549384B1
公开(公告)日：2013-10-01
申请号：US12822664
申请日：2010-06-24
申请人： ChengKuo Huang , Sui-Hung Fred Au , Xueshi Yang , Lau Nguyen
发明人： ChengKuo Huang , Sui-Hung Fred Au , Xueshi Yang , Lau Nguyen
IPC分类号： G11C29/00
CPC分类号： G06F11/2053 , G06F11/1012 , G11C29/24 , G11C29/4401 , G11C29/72 , G11C29/82 , G11C2029/0409 , G11C2029/0411
摘要： Apparatus having corresponding methods and computer-readable media comprise an encoder configured to provide encoded data according to an error correction code; a flash memory interface configured to write the encoded data to a location in flash memory, and to read the encoded data from the location in the flash memory; a decoder configured to decode the encoded data read from the location in the flash memory, and to indicate a number of resulting decode errors; and a retirement module configured to retire the location responsive to a number of resulting decode errors reaching an error threshold T.
摘要翻译：具有相应方法和计算机可读介质的装置包括：编码器，被配置为根据纠错码提供编码数据; 闪存接口，被配置为将编码数据写入闪速存储器中的位置，并从闪存中的位置读取编码数据; 解码器，被配置为对从闪速存储器中的位置读取的编码数据进行解码，并指示所得到的解码错误的数量; 以及退避模块，被配置为响应于到达错误阈值T的所得到的解码错误的数量而退出所述位置。

2. 发明授权

US08219775B2 Nonvolatile memory system 有权
标题翻译：非易失性存储器系统
公开(公告)号：US08219775B2
公开(公告)日：2012-07-10
申请号：US13230624
申请日：2011-09-12
申请人： Zining Wu , Lau Nguyen , Pantas Sutardja , Chi-Kong Lee , Tony Yoon
发明人： Zining Wu , Lau Nguyen , Pantas Sutardja , Chi-Kong Lee , Tony Yoon
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F3/0688 , G06F3/0619 , G06F3/0661 , G06F11/1068 , G06F12/0246
摘要： A memory system including a nonvolatile memory, and a memory control module. The nonvolatile memory includes a plurality of memory cells arranged among a plurality of physical memory blocks, wherein each physical memory block is of a predetermined size. The memory control module includes a write path module and a read path module. In response to the memory control module receiving data in a first format such that the data is evenly distributable among the plurality of physical memory blocks, the write path module modifies the first format of the data into a second format prior to writing the data to the plurality of physical memory blocks. The second format of the data is such that the data is no longer evenly distributable among the plurality of physical memory blocks. The read path module is configured to read the data from the nonvolatile memory in accordance with the second format.
摘要翻译：一种包括非易失性存储器和存储器控制模块的存储器系统。非易失性存储器包括布置在多个物理存储器块之间的多个存储器单元，其中每个物理存储块具有预定尺寸。存储器控制模块包括写路径模块和读路径模块。响应于存储器控制模块以第一格式接收数据使得数据在多个物理存储器块之间可均匀地分配，写入路径模块在将数据写入到第二格式之前将数据的第一格式修改为第二格式多个物理存储器块。数据的第二格式使得数据不再能够在多个物理存储器块之间均匀分配。读路径模块被配置为根据第二格式从非易失性存储器读取数据。

3. 发明授权

US08135913B1 Mixed multi-level cell and single level cell storage device 有权
标题翻译：混合多级单元和单级存储单元
公开(公告)号：US08135913B1
公开(公告)日：2012-03-13
申请号：US13113236
申请日：2011-05-23
申请人： Joseph Sheredy , Lau Nguyen
发明人： Joseph Sheredy , Lau Nguyen
IPC分类号： G06F12/00
CPC分类号： G06F3/0616 , G06F3/064 , G06F3/0679 , G06F12/0246 , G06F2212/7211 , G11C11/5628 , G11C11/5635 , G11C16/16 , G11C16/349 , G11C16/3495 , G11C2211/5641
摘要： Some of the embodiments of the present disclosure provide a method for programming a flash memory having a plurality of memory blocks, wherein each memory block of the plurality of memory blocks is either a single-level cell (SLC) memory block or a multi-level cell (MLC) memory block, the method comprising assigning a weighting factor to each memory block of the plurality of memory blocks based on whether the memory block is an SLC memory block or an MLC memory block, tracking a number of write—erase cycles for each memory block, and selecting one or more memory blocks for writing data based at least in part on the weighting factor and the tracked number of write—erase cycles of each memory block of the plurality of memory blocks. Other embodiments are also described and claimed.
摘要翻译：本公开的一些实施例提供了一种用于对具有多个存储器块的闪存进行编程的方法，其中多个存储器块中的每个存储器块是单级单元（SLC）存储器块或多级单元（MLC）存储块，所述方法包括基于所述存储器块是SLC存储器块还是MLC存储块来分配加权因子到所述多个存储器块中的每个存储器块，跟踪多个写擦除周期，并且至少部分地基于所述多个存储器块的每个存储器块的加权因子和所述被跟踪的写擦除周期数来选择用于写入数据的一个或多个存储器块。还描述和要求保护其他实施例。

4. 发明授权

US08650438B2 Controller for reading data from non-volatile memory 有权
标题翻译：用于从非易失性存储器读取数据的控制器
公开(公告)号：US08650438B2
公开(公告)日：2014-02-11
申请号：US12842714
申请日：2010-07-23
申请人： Cheng Kuo Huang , Siu-Hung Fred Au , Lau Nguyen , Perry Neos
发明人： Cheng Kuo Huang , Siu-Hung Fred Au , Lau Nguyen , Perry Neos
IPC分类号： G06F11/00
CPC分类号： G06F11/1068 , G06F3/061 , G06F3/0659 , G06F3/0688 , G06F3/0689
摘要： The present disclosure includes systems and techniques relating to solid state drive controllers. In some implementations, a device includes a buffer that holds a block of data corresponding to a command from a host. The command identifies the block of data and a logical sequence in which the identified block of data is to be transmitted. In response to the command, a data retriever included in the device retrieves the portions of the block of data from non-volatile memory units in a retrieval sequence that is different from the logical sequence. When the device receives multiple commands identifying multiple blocks of data, the device services the commands in parallel by retrieving portions of blocks of data identified by both commands.
摘要翻译：本公开包括与固态驱动控制器有关的系统和技术。在一些实现中，设备包括保存对应于来自主机的命令的数据块的缓冲器。该命令识别数据块以及要发送所识别的数据块的逻辑序列。响应于该命令，包含在该设备中的数据检索器以与逻辑序列不同的检索顺序从非易失性存储器单元检索数据块的部分。当设备接收到识别多个数据块的多个命令时，设备通过检索由两个命令标识的数据块的部分来并行地服务命令。

5. 发明授权

US08572309B2 Apparatus and method to protect metadata against unexpected power down 失效
标题翻译：保护元数据防止意外断电的装置和方法
公开(公告)号：US08572309B2
公开(公告)日：2013-10-29
申请号：US12619938
申请日：2009-11-17
申请人： Luan Ton-That , Lau Nguyen , Gwoyuh Hwu
发明人： Luan Ton-That , Lau Nguyen , Gwoyuh Hwu
IPC分类号： G06F12/00 , G06F12/10 , G06F12/02
CPC分类号： G06F12/0246 , G06F11/1441 , G06F2212/7207
摘要： A system includes first memory configured to store first metadata to associate logical addresses with physical addresses. Second memory is configured to include the physical addresses, to store first data based on the physical addresses, and to store portions of the first metadata when a status of a predetermined group of the physical addresses is changed. A recovery module is configured to update the first metadata based on the portions of the first metadata stored in the second memory.
摘要翻译：系统包括被配置为存储第一元数据以将逻辑地址与物理地址相关联的第一存储器。第二存储器被配置为包括物理地址，以基于物理地址存储第一数据，并且当物理地址的预定组的状态改变时存储第一元数据的部分。恢复模块被配置为基于存储在第二存储器中的第一元数据的部分来更新第一元数据。

6. 发明授权

US08543756B2 Solid-state drive command grouping 失效
标题翻译：固态驱动器命令分组
公开(公告)号：US08543756B2
公开(公告)日：2013-09-24
申请号：US12694501
申请日：2010-01-27
申请人： Lau Nguyen , Perry Neos , Gwoyuh Hwu
发明人： Lau Nguyen , Perry Neos , Gwoyuh Hwu
IPC分类号： G06F12/00
CPC分类号： G06F3/0613 , G06F3/0659 , G06F3/0679
摘要： A method and other embodiments associated with solid-state drive command grouping are described. In one embodiment, a first command and a second command are grouped into a command pack, where the first command and the second command do not share a common channel for execution. A solid-state drive is controlled to execute the command pack on the solid-state drive, where executing the command pack causes the first command and the second command to execute concurrently on separate channels.
摘要翻译：描述了与固态驱动命令分组相关联的方法和其他实施例。在一个实施例中，第一命令和第二命令被分组为命令包，其中第一命令和第二命令不共享用于执行的公共信道。控制固态驱动器以在固态驱动器上执行命令包，其中执行命令包使得第一命令和第二命令在单独的通道上同时执行。

7. 发明授权

US08495320B1 Method and apparatus for storing data in a flash memory including single level memory cells and multi level memory cells 有权
标题翻译：用于将数据存储在包括单级存储器单元和多级存储器单元的闪速存储器中的方法和装置
公开(公告)号：US08495320B1
公开(公告)日：2013-07-23
申请号：US13416678
申请日：2012-03-09
申请人： Joseph Sheredy , Lau Nguyen
发明人： Joseph Sheredy , Lau Nguyen
IPC分类号： G06F12/00
CPC分类号： G06F3/0616 , G06F3/064 , G06F3/0679 , G06F12/0246 , G06F2212/7211 , G11C11/5628 , G11C11/5635 , G11C16/16 , G11C16/349 , G11C16/3495 , G11C2211/5641
摘要： Some of the embodiments of the present disclosure provide a method for programming a flash memory having a plurality of memory blocks, wherein each memory block of the plurality of memory blocks is either a single-level cell (SLC) memory block or a multi-level cell (MLC) memory block, the method comprising assigning a weighting factor to each memory block of the plurality of memory blocks based on whether the memory block is an SLC memory block or an MLC memory block, tracking a number of write-erase cycles for each memory block, and selecting one or more memory blocks for writing data based at least in part on the weighting factor and the tracked number of write-erase cycles of each memory block of the plurality of memory blocks. Other embodiments are also described and claimed.
摘要翻译：本公开的一些实施例提供了一种用于对具有多个存储器块的闪存进行编程的方法，其中多个存储器块中的每个存储器块是单级单元（SLC）存储器块或多级单元（MLC）存储块，所述方法包括基于所述存储器块是SLC存储器块还是MLC存储块来分配加权因子到所述多个存储器块中的每个存储器块，跟踪多个写擦除周期，并且至少部分地基于所述多个存储器块的每个存储器块的加权因子和所述被跟踪的写擦除周期数来选择用于写入数据的一个或多个存储器块。还描述和要求保护其他实施例。

8. 发明申请

US20120303873A1 METHOD FOR STORAGE DEVICES TO ACHIEVE LOW WRITE AMPLIFICATION WITH LOW OVER PROVISION 有权
标题翻译：存储设备的方法，用于实现低写扩频功能
公开(公告)号：US20120303873A1
公开(公告)日：2012-11-29
申请号：US13461899
申请日：2012-05-02
申请人： Lau Nguyen , Perry Neos , Luan Ton-That
发明人： Lau Nguyen , Perry Neos , Luan Ton-That
IPC分类号： G06F12/00
CPC分类号： G06F3/0616 , G06F3/0652 , G06F3/0679 , G06F12/0246 , G06F2212/7209
摘要： A solid state drive (SSD) includes an SSD control module configured to determine frequencies corresponding to how often data stored in respective logical addresses associated with the SSD is updated and form groups of the logical addresses according to the frequencies, and a memory control module configured to rewrite the data to physical addresses in blocks of an SSD storage region based on the groups.
摘要翻译：固态驱动器（SSD）包括SSD控制模块，其被配置为确定对应于根据频率更新存储在与SSD相关联的相应逻辑地址中的数据的频率和形成逻辑地址组的频率，以及配置的存储器控制模块基于组将数据重写到SSD存储区域的块中的物理地址。

9. 发明授权

US08019959B2 Nonvolatile memory system 有权
标题翻译：非易失性存储器系统
公开(公告)号：US08019959B2
公开(公告)日：2011-09-13
申请号：US12025371
申请日：2008-02-04
申请人： Zining Wu , Lau Nguyen , Pantas Sutardja , Chi-Kong Lee , Tony Yoon
发明人： Zining Wu , Lau Nguyen , Pantas Sutardja , Chi-Kong Lee , Tony Yoon
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F3/0688 , G06F3/0619 , G06F3/0661 , G06F11/1068 , G06F12/0246
摘要： A nonvolatile (NV) memory system includes a memory control module that encodes data to provide encoded logical data structures. The system also includes NV memory that includes X arrays that include physical data structures that differ in size from the encoded logical data structures. The memory control module writes/reads from the NV memory according to the encoded logical data structures. X is an integer greater than or equal to 1.
摘要翻译：非易失性（NV）存储器系统包括对数据进行编码以提供编码的逻辑数据结构的存储器控制模块。该系统还包括NV存储器，其包括X阵列，其包括与编码的逻辑数据结构不同的物理数据结构。存储器控制模块根据编码的逻辑数据结构从NV存储器读/写。 X是大于或等于1的整数。

10. 发明授权

US07948798B1 Mixed multi-level cell and single level cell storage device 有权
标题翻译：混合多级单元和单级存储单元
公开(公告)号：US07948798B1
公开(公告)日：2011-05-24
申请号：US12507548
申请日：2009-07-22
申请人： Joseph Sheredy , Lau Nguyen
发明人： Joseph Sheredy , Lau Nguyen
IPC分类号： G11C16/04
CPC分类号： G06F3/0616 , G06F3/064 , G06F3/0679 , G06F12/0246 , G06F2212/7211 , G11C11/5628 , G11C11/5635 , G11C16/16 , G11C16/349 , G11C16/3495 , G11C2211/5641
摘要： Some of the embodiments of the present disclosure provide a method for programming a flash memory having a plurality of memory blocks, wherein each memory block of the plurality of memory blocks is either a single-level cell (SLC) memory block or a multi-level cell (MLC) memory block, the method comprising assigning a weighting factor to each memory block of the plurality of memory blocks based on whether the memory block is an SLC memory block or an MLC memory block, tracking a number of write-erase cycles for each memory block, and selecting one or more memory blocks for writing data based at least in part on the weighting factor and the tracked number of write-erase cycles of each memory block of the plurality of memory blocks. Other embodiments are also described and claimed.
摘要翻译：本公开的一些实施例提供了一种用于对具有多个存储器块的闪存进行编程的方法，其中多个存储器块中的每个存储器块是单级单元（SLC）存储器块或多级单元（MLC）存储块，所述方法包括基于所述存储器块是SLC存储器块还是MLC存储块来分配加权因子到所述多个存储器块中的每个存储器块，跟踪多个写擦除周期，并且至少部分地基于所述多个存储器块的每个存储器块的加权因子和所述被跟踪的写擦除周期数来选择用于写入数据的一个或多个存储器块。还描述和要求保护其他实施例。

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