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1. 发明申请

US20110302366A1 Memory expansion using rank aggregation 有权
标题翻译：使用秩聚合的内存扩展
公开(公告)号：US20110302366A1
公开(公告)日：2011-12-08
申请号：US12802314
申请日：2010-06-04
申请人： Jay Evan Scott Peterson , Philip Manela
发明人： Jay Evan Scott Peterson , Philip Manela
IPC分类号： G06F12/00
CPC分类号： G06F13/1668 , G06F12/0623
摘要： In one embodiment, a method includes receiving from a memory controller, a request to access memory stored at memory modules, the request directed to one of a plurality of logical ranks, mapping at a rank aggregator, the logical rank to one of a plurality of physical ranks at the memory modules, and forwarding the request to one of the memory modules according to the mapping. Two or more of the memory modules are combined to represent the number of logical ranks at the memory controller such that there is a one-to-one mapping between the logical ranks and the physical ranks. An apparatus for rank aggregation is also disclosed.
摘要翻译：在一个实施例中，一种方法包括从存储器控制器接收访问存储在存储器模块中的存储器的请求，指向多个逻辑等级中的一个的请求，在秩聚合器处映射，逻辑等级为多个在内存模块上进行物理排队，并根据映射将请求转发到其中一个内存模块。将两个或更多个存储器模块组合以表示存储器控制器上的逻辑排名的数量，使得在逻辑排队和物理队列之间存在一对一的映射。还公开了一种等级聚合的装置。

2. 发明授权

US07305598B1 Test clock generation for higher-speed testing of a semiconductor device 有权
标题翻译：测试时钟产生用于半导体器件的更高速测试
公开(公告)号：US07305598B1
公开(公告)日：2007-12-04
申请号：US11089994
申请日：2005-03-25
申请人： Amit Sanghani , Philip Manela
发明人： Amit Sanghani , Philip Manela
IPC分类号： G01R31/28
CPC分类号： G01R31/31727
摘要： Embodiments for generating a higher frequency test clock signal for a semiconductor device are disclosed. In an example embodiment, a clock generator may be coupled to a clock input. A test clock generator may receive a clock signal generated by the clock generator, and the test clock generator may output a higher frequency test clock signal derived at least in part from the clock signal generated by the clock generator. The test clock generator may output the higher frequency test clock signal for a configurable number of clock periods.
摘要翻译：公开了用于产生用于半导体器件的较高频率测试时钟信号的实施例。在示例实施例中，时钟发生器可以耦合到时钟输入。测试时钟发生器可以接收由时钟发生器产生的时钟信号，并且测试时钟发生器可以输出至少部分地由时钟发生器产生的时钟信号导出的更高频率的测试时钟信号。测试时钟发生器可以输出更高频率的测试时钟信号，用于可配置的时钟周期数。

3. 发明申请

US20090177849A1 SYSTEM AND METHODS FOR MEMORY EXPANSION 有权
标题翻译：用于存储扩展的系统和方法
公开(公告)号：US20090177849A1
公开(公告)日：2009-07-09
申请号：US11971066
申请日：2008-01-08
申请人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
发明人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
IPC分类号： G06F12/00
CPC分类号： G06F12/1009 , G06F11/1016 , G06F12/0207 , G06F12/0292 , G06F12/0607 , G06F13/1684 , G06F13/4234
摘要： This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving a memory request from a memory controller over a channel. Based on the memory request, the example embodiment includes selecting a location in memory to couple to a sub-channel of the channel and configuring the set of field effect transistors to couple the channel with the sub-channel. In the example embodiment, data may be allowed to flow between the memory controller and the location in the memory over the channel and the sub-channel.
摘要翻译：本文档还讨论了一个用于内存扩展的示例系统和方法。示例实施例包括通过信道从存储器控制器接收存储器请求。基于存储器请求，示例性实施例包括选择存储器中的位置以耦合到信道的子信道并且配置该场效应晶体管集合以将该信道与子信道耦合。在示例实施例中，可以允许数据通过信道和子信道在存储器控制器和存储器中的位置之间流动。

4. 发明授权

US09026714B2 Memory expansion using rank aggregation 有权
标题翻译：使用秩聚合的内存扩展
公开(公告)号：US09026714B2
公开(公告)日：2015-05-05
申请号：US12802314
申请日：2010-06-04
申请人： Jay Evan Scott Peterson , Philip Manela
发明人： Jay Evan Scott Peterson , Philip Manela
IPC分类号： G06F12/00 , G06F13/16 , G06F12/06
CPC分类号： G06F13/1668 , G06F12/0623
摘要： In one embodiment, a method includes receiving from a memory controller, a request to access memory stored at memory modules, the request directed to one of a plurality of logical ranks, mapping at a rank aggregator, the logical rank to one of a plurality of physical ranks at the memory modules, and forwarding the request to one of the memory modules according to the mapping. Two or more of the memory modules are combined to represent the number of logical ranks at the memory controller such that there is a one-to-one mapping between the logical ranks and the physical ranks. An apparatus for rank aggregation is also disclosed.
摘要翻译：在一个实施例中，一种方法包括从存储器控制器接收访问存储在存储器模块中的存储器的请求，指向多个逻辑等级中的一个的请求，在秩聚合器处映射，逻辑等级为多个在内存模块上进行物理排队，并根据映射将请求转发到其中一个内存模块。将两个或更多个存储器模块组合以表示存储器控制器上的逻辑排名的数量，使得在逻辑排队和物理队列之间存在一对一的映射。还公开了一种等级聚合的装置。

5. 发明授权

US08825965B2 System and methods for memory expansion 有权
标题翻译：用于内存扩展的系统和方法
公开(公告)号：US08825965B2
公开(公告)日：2014-09-02
申请号：US11971066
申请日：2008-01-08
申请人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
发明人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
IPC分类号： G06F12/00 , G06F13/42 , G06F13/16 , G06F12/02 , G06F12/06
CPC分类号： G06F12/1009 , G06F11/1016 , G06F12/0207 , G06F12/0292 , G06F12/0607 , G06F13/1684 , G06F13/4234
摘要： This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving a memory request from a memory controller over a channel. Based on the memory request, the example embodiment includes selecting a location in memory to couple to a sub-channel of the channel and configuring the set of field effect transistors to couple the channel with the sub-channel. In the example embodiment, data may be allowed to flow between the memory controller and the location in the memory over the channel and the sub-channel.
摘要翻译：本文档还讨论了一个用于内存扩展的示例系统和方法。示例实施例包括通过信道从存储器控制器接收存储器请求。基于存储器请求，示例性实施例包括选择存储器中的位置以耦合到信道的子信道并且配置该场效应晶体管集合以将该信道与子信道耦合。在示例实施例中，可以允许数据通过信道和子信道在存储器控制器和存储器中的位置之间流动。

6. 发明授权

US08407394B2 System and methods for memory expansion 有权
标题翻译：用于内存扩展的系统和方法
公开(公告)号：US08407394B2
公开(公告)日：2013-03-26
申请号：US11971091
申请日：2008-01-08
申请人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
发明人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
IPC分类号： G06F12/00
CPC分类号： G06F12/0292 , G06F12/06
摘要： This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes detecting a memory command directed to a logical rand and a number of physical ranks mapped to the logical rank. The example embodiment may also include issuing the memory command to the number of physical ranks based on determining that the memory command is to be issued to the number of physical ranks.
摘要翻译：本文档还讨论了一个用于内存扩展的示例系统和方法。示例实施例包括检测针对映射到逻辑秩的逻辑rand和多个物理等级的存储器命令。该示例性实施例还可以包括基于确定存储器命令将被发布到物理等级的数量而将存储器命令发布到物理队列的数量。

7. 发明申请

US20090177853A1 SYSTEM AND METHODS FOR MEMORY EXPANSION 有权
标题翻译：用于存储扩展的系统和方法
公开(公告)号：US20090177853A1
公开(公告)日：2009-07-09
申请号：US11971091
申请日：2008-01-08
申请人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
发明人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
IPC分类号： G06F12/00
CPC分类号： G06F12/0292 , G06F12/06
摘要： This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes detecting a memory command directed to a logical rand and a number of physical ranks mapped to the logical rank. The example embodiment may also include issuing the memory command to the number of physical ranks based on determining that the memory command is to be issued to the number of physical ranks.
摘要翻译：本文档还讨论了一个用于内存扩展的示例系统和方法。示例实施例包括检测针对映射到逻辑秩的逻辑rand和多个物理等级的存储器命令。该示例性实施例还可以包括基于确定存储器命令将被发布到物理等级的数量而将存储器命令发布到物理队列的数量。

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