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1. 发明授权

US08825965B2 System and methods for memory expansion 有权
标题翻译：用于内存扩展的系统和方法
公开(公告)号：US08825965B2
公开(公告)日：2014-09-02
申请号：US11971066
申请日：2008-01-08
申请人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
发明人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
IPC分类号： G06F12/00 , G06F13/42 , G06F13/16 , G06F12/02 , G06F12/06
CPC分类号： G06F12/1009 , G06F11/1016 , G06F12/0207 , G06F12/0292 , G06F12/0607 , G06F13/1684 , G06F13/4234
摘要： This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving a memory request from a memory controller over a channel. Based on the memory request, the example embodiment includes selecting a location in memory to couple to a sub-channel of the channel and configuring the set of field effect transistors to couple the channel with the sub-channel. In the example embodiment, data may be allowed to flow between the memory controller and the location in the memory over the channel and the sub-channel.
摘要翻译：本文档还讨论了一个用于内存扩展的示例系统和方法。示例实施例包括通过信道从存储器控制器接收存储器请求。基于存储器请求，示例性实施例包括选择存储器中的位置以耦合到信道的子信道并且配置该场效应晶体管集合以将该信道与子信道耦合。在示例实施例中，可以允许数据通过信道和子信道在存储器控制器和存储器中的位置之间流动。

2. 发明申请

US20090177849A1 SYSTEM AND METHODS FOR MEMORY EXPANSION 有权
标题翻译：用于存储扩展的系统和方法
公开(公告)号：US20090177849A1
公开(公告)日：2009-07-09
申请号：US11971066
申请日：2008-01-08
申请人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
发明人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
IPC分类号： G06F12/00
CPC分类号： G06F12/1009 , G06F11/1016 , G06F12/0207 , G06F12/0292 , G06F12/0607 , G06F13/1684 , G06F13/4234
摘要： This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving a memory request from a memory controller over a channel. Based on the memory request, the example embodiment includes selecting a location in memory to couple to a sub-channel of the channel and configuring the set of field effect transistors to couple the channel with the sub-channel. In the example embodiment, data may be allowed to flow between the memory controller and the location in the memory over the channel and the sub-channel.
摘要翻译：本文档还讨论了一个用于内存扩展的示例系统和方法。示例实施例包括通过信道从存储器控制器接收存储器请求。基于存储器请求，示例性实施例包括选择存储器中的位置以耦合到信道的子信道并且配置该场效应晶体管集合以将该信道与子信道耦合。在示例实施例中，可以允许数据通过信道和子信道在存储器控制器和存储器中的位置之间流动。

3. 发明授权

US08407394B2 System and methods for memory expansion 有权
标题翻译：用于内存扩展的系统和方法
公开(公告)号：US08407394B2
公开(公告)日：2013-03-26
申请号：US11971091
申请日：2008-01-08
申请人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
发明人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
IPC分类号： G06F12/00
CPC分类号： G06F12/0292 , G06F12/06
摘要： This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes detecting a memory command directed to a logical rand and a number of physical ranks mapped to the logical rank. The example embodiment may also include issuing the memory command to the number of physical ranks based on determining that the memory command is to be issued to the number of physical ranks.
摘要翻译：本文档还讨论了一个用于内存扩展的示例系统和方法。示例实施例包括检测针对映射到逻辑秩的逻辑rand和多个物理等级的存储器命令。该示例性实施例还可以包括基于确定存储器命令将被发布到物理等级的数量而将存储器命令发布到物理队列的数量。

4. 发明申请

US20090177853A1 SYSTEM AND METHODS FOR MEMORY EXPANSION 有权
标题翻译：用于存储扩展的系统和方法
公开(公告)号：US20090177853A1
公开(公告)日：2009-07-09
申请号：US11971091
申请日：2008-01-08
申请人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
发明人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
IPC分类号： G06F12/00
CPC分类号： G06F12/0292 , G06F12/06
摘要： This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes detecting a memory command directed to a logical rand and a number of physical ranks mapped to the logical rank. The example embodiment may also include issuing the memory command to the number of physical ranks based on determining that the memory command is to be issued to the number of physical ranks.
摘要翻译：本文档还讨论了一个用于内存扩展的示例系统和方法。示例实施例包括检测针对映射到逻辑秩的逻辑rand和多个物理等级的存储器命令。该示例性实施例还可以包括基于确定存储器命令将被发布到物理等级的数量而将存储器命令发布到物理队列的数量。

5. 发明授权

US08621132B2 System and methods for memory expansion 有权
标题翻译：用于内存扩展的系统和方法
公开(公告)号：US08621132B2
公开(公告)日：2013-12-31
申请号：US11971080
申请日：2008-01-08
申请人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Dmitry Barsky
发明人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Dmitry Barsky
IPC分类号： G06F12/00
CPC分类号： G06F13/4243 , G11C5/04
摘要： This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving first initialization data from a physical dual inline memory module (DIMM) and converting the first initialization data to second initialization data of a logical DIMM mapped to the physical DIMM. The example embodiment may further include programming a memory controller based on the second initialization data.
摘要翻译：本文档还讨论了一个用于内存扩展的示例系统和方法。示例实施例包括从物理双列直插式存储器模块（DIMM）接收第一初始化数据，并将第一初始化数据转换为映射到物理DIMM的逻辑DIMM的第二初始化数据。该示例性实施例还可以包括基于第二初始化数据来编程存储器控制器。

6. 发明申请

US20090177861A1 SYSTEM AND METHODS FOR MEMORY EXPANSION 有权
标题翻译：用于存储扩展的系统和方法
公开(公告)号：US20090177861A1
公开(公告)日：2009-07-09
申请号：US11971080
申请日：2008-01-08
申请人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Dmitry Barsky
发明人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Dmitry Barsky
IPC分类号： G06F9/34
CPC分类号： G06F13/4243 , G11C5/04
摘要： This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving first initialization data from a physical dual inline memory module (DIMM) and converting the first initialization data to second initialization data of a logical DIMM mapped to the physical DIMM. The example embodiment may further include programming a memory controller based on the second initialization data.
摘要翻译：本文档还讨论了一个用于内存扩展的示例系统和方法。示例实施例包括从物理双列直插式存储器模块（DIMM）接收第一初始化数据，并将第一初始化数据转换为映射到物理DIMM的逻辑DIMM的第二初始化数据。该示例性实施例还可以包括基于第二初始化数据来编程存储器控制器。

7. 发明授权

US08732506B2 Method and apparatus for providing power to a server platforms by using a capacitor to provide power during a second power supply transitioning on 有权
标题翻译：用于通过在第二电源转换期间使用电容器来提供电力来向服务器平台提供电力的方法和装置
公开(公告)号：US08732506B2
公开(公告)日：2014-05-20
申请号：US13116345
申请日：2011-05-26
申请人： Satyanarayana Nishtala , Mark Ramon Imbertson
发明人： Satyanarayana Nishtala , Mark Ramon Imbertson
IPC分类号： G06F1/30 , G06F1/00
CPC分类号： G06F1/28 , G06F1/3206 , G06F1/3287 , Y02D10/171
摘要： In one embodiment, a method includes determining if a power load requirement associated with a server arrangement is below a threshold. The server arrangement includes at least a first power supply and a second power supply, as well as a capacitor arrangement. The method also includes providing power to the server arrangement using the first power supply and not the second power supply when it is determined that the power load requirement is below the threshold, and providing the power to the server arrangement using the first power supply and the second power supply when it is determined that the power load requirement is not below the threshold.
摘要翻译：在一个实施例中，一种方法包括确定与服务器装置相关联的功率负载要求是否低于阈值。服务器装置至少包括第一电源和第二电源以及电容器装置。该方法还包括当确定电力负载要求低于阈值时使用第一电源而不是第二电源向服务器装置提供电力，并且使用第一电源向服务器装置提供电力，并且当确定电力负载要求不低于阈值时，第二电源。

8. 发明授权

US08117369B2 Input-output module for operation in memory module socket and method for extending a memory interface for input-output operations 有权
标题翻译：用于在存储器模块插槽中操作的输入输出模块以及用于扩展用于输入 - 输出操作的存储器接口的方法
公开(公告)号：US08117369B2
公开(公告)日：2012-02-14
申请号：US12986104
申请日：2011-01-06
申请人： Satyanarayana Nishtala , Thomas Lee Lyon , Daniel Edward Lenoski
发明人： Satyanarayana Nishtala , Thomas Lee Lyon , Daniel Edward Lenoski
IPC分类号： G06F13/00 , H05K7/10
CPC分类号： G06F13/385 , G11C5/04
摘要： An I/O module configured to operate in a memory module socket and method for extending a memory interface are generally described herein. The I/O module may include a serial-presence detection (SPD) device to indicate that the I/O module is an I/O device and to indicate one or more functions associated with the I/O module. The I/O module may also include a serial data controller to communicate serial data in accordance with a predetermined communication technique with a configurable switch of a host system over preselected system management (SM) bus address lines and unused system clock signal lines of the memory module socket. The predetermined communication technique may include a peripheral component interconnect express (PCIe), a Serial Advanced Technology Attachment (SATA), a Serial Attached Small Computer System Interface (SAS), a universal-serial bus (USB) or a switched-fabric (InfiniBand) communication technique.
摘要翻译：配置为在存储器模块插座中操作的I / O模块和用于扩展存储器接口的方法一般在此描述。 I / O模块可以包括串行存在检测（SPD）设备，以指示I / O模块是I / O设备并且指示与I / O模块相关联的一个或多个功能。 I / O模块还可以包括串行数据控制器，以根据预定的通信技术，通过主机系统的可配置开关，通过预选的系统管理（SM）总线地址线和存储器的未使用的系统时钟信号线来传送串行数据模块插座。预定的通信技术可以包括外围组件互连快速（PCIe），串行高级技术附件（SATA），串行附属小型计算机系统接口（SAS），通用串行总线（USB）或交换结构（InfiniBand ）通信技术。

9. 发明授权

US07886103B2 Input-output module, processing platform and method for extending a memory interface for input-output operations 有权
标题翻译：输入输出模块，处理平台和扩展用于输入输出操作的存储器接口的方法
公开(公告)号：US07886103B2
公开(公告)日：2011-02-08
申请号：US12206501
申请日：2008-09-08
申请人： Satyanarayana Nishtala , Thomas L. Lyon , Daniel E. Lenoski
发明人： Satyanarayana Nishtala , Thomas L. Lyon , Daniel E. Lenoski
IPC分类号： H05K7/10 , G06F13/00
CPC分类号： G06F13/385 , G11C5/04
摘要： Embodiments of an I/O module, processing platform, and method for extending a memory interface are generally described herein. In some embodiments, the I/O module may be configured to operate in a memory module socket, such as a DIMM socket, to provide increased I/O functionality in a host system. Some system management bus address lines and some unused system clock signal lines may be reconfigured as serial data lines for serial data communications between the I/O module and a PCIe switch of the host system.
摘要翻译：这里一般地描述用于扩展存储器接口的I / O模块，处理平台和方法的实施例。在一些实施例中，I / O模块可以被配置为在诸如DIMM插槽的存储器模块插座中操作，以在主机系统中提供增加的I / O功能。一些系统管理总线地址线和一些未使用的系统时钟信号线可以被重新配置为用于I / O模块和主机系统的PCIe交换机之间的串行数据通信的串行数据线。

10. 发明授权

US5907485A Method and apparatus for flow control in packet-switched computer system 失效
标题翻译：分组交换计算机系统中流控制的方法和装置
公开(公告)号：US5907485A
公开(公告)日：1999-05-25
申请号：US414875
申请日：1995-03-31
申请人： William C. Van Loo , Zahir Ebrahim , Satyanarayana Nishtala , Kevin B. Normoyle , Leslie Kohn , Louis F. Coffin, III
发明人： William C. Van Loo , Zahir Ebrahim , Satyanarayana Nishtala , Kevin B. Normoyle , Leslie Kohn , Louis F. Coffin, III
IPC分类号： G06F9/46 , G06F13/24 , G05B15/00
CPC分类号： G06F9/546 , G06F13/24
摘要： This invention describes a link-by-link flow control method for packet-switched uniprocessor and multiprocessor computer systems that maximizes system resource utilization and throughput, and minimizes system latency. The computer system comprises one or more master interfaces, one or more slave interfaces, and an interconnect system controller which provides dedicated transaction request queues for each master interface and controls the forwarding of transactions to each slave interface. The master interface keeps track of the number of requests in the dedicated queue in the system controller, and the system controller keeps track of the number of requests in each slave interface queue. Both the master interface, and system controller know the maximum capacity of the queue immediately downstream from it, and does not issue more transaction requests than what the downstream queue can accommodate. An acknowledgment from the downstream queue indicates to the sender that there is space in it for another transaction. Thus no system resources are wasted trying to send a request to a queue that is already full.
摘要翻译：本发明描述了一种用于分组交换单处理器和多处理器计算机系统的链路链路流控制方法，其使系统资源利用率和吞吐量最大化，并最小化系统等待时间。计算机系统包括一个或多个主接口，一个或多个从接口和互连系统控制器，其为每个主接口提供专用事务请求队列，并且控制事务到每个从接口的转发。主接口跟踪系统控制器中专用队列中的请求数，系统控制器跟踪每个从接口队列中的请求数。主接口和系统控制器都知道其下游队列的最大容量，并且不会比下游队列可以容纳更多的事务请求。来自下游队列的确认向发送方指示在其中存在另一个事务的空间。因此，尝试将请求发送到已满的队列时，不会浪费任何系统资源。

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