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1. 发明申请

US20100072455A1 Well-Structure Anti-Punch-through Microwire Device 有权
标题翻译：良好结构的抗穿通微线设备
公开(公告)号：US20100072455A1
公开(公告)日：2010-03-25
申请号：US12235359
申请日：2008-09-22
申请人： Mark Albert Crowder
发明人： Mark Albert Crowder
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/125 , B82Y10/00 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/78 , Y10S977/936
摘要： A well-structure anti-punch-through microwire device and associated fabrication method are provided. The method initially forms a microwire with alternating highly and lightly doped cylindrical regions. A channel ring is formed external to the microwire outer shell and surrounding a first dopant well-structure region in the microwire, between source and drain (S/D) regions of the microwire. The S/D regions are doped with a second dopant, opposite to the first dopant. A gate dielectric ring is formed surrounding the channel ring, and a gate electrode ring is formed surrounding the gate dielectric ring. The well-structure, in contrast to conventional micro or nanowire transistors, helps prevent the punch-through phenomena.
摘要翻译：提供了良好结构的抗穿通微线器件和相关的制造方法。该方法最初形成具有交替的高度和轻掺杂的圆柱形区域的微线。通道环形成在微线外壳的外部，并且包围微线中的微线的源极和漏极（S / D）区域之间的第一掺杂剂阱结构区域。 S / D区域掺杂有与第一掺杂剂相反的第二掺杂剂。围绕通道环形成栅介质环，并且围绕栅介质环形成栅电极环。与传统的微纳米线或纳米线晶体管相反，井结构有助于防止穿透现象。

2. 发明授权

US07056629B2 2N mask design for sequential lateral solidification 失效
标题翻译： 2N面罩设计，用于连续横向固化
公开(公告)号：US07056629B2
公开(公告)日：2006-06-06
申请号：US10883230
申请日：2004-07-01
申请人： Mark Albert Crowder
发明人： Mark Albert Crowder
IPC分类号： G01F9/00
CPC分类号： H01L21/0268 , B23K26/066 , H01L21/2026 , Y10S438/942
摘要： A mask design for use in sequential lateral solidification processing is provided comprising a first array of beamlet and a second array of beamlets, which is parallel to the first, for accomplishing a first 2-shot process, and a third array of beamlets and forth array of beamlets, both at at an angle, for example 90 degrees, relative to the first and second array of beamlets for accomplishing a second 2-shot process without the need to rotate the mask. A method of using the mask to accomplish a 2N crystallization process.
摘要翻译：提供了用于顺序横向固化处理的掩模设计，其包括与第一阵列的子束和第二阵列的子束（其平行于第一阵列），用于完成第一个2次工艺，第三阵列的子束和第四阵列的子束，两者以相对于第一和第二子束阵列成一定角度，例如90度，用于完成第二个2次射程，而不需要旋转掩模。使用掩模实现2N结晶过程的方法。

3. 发明授权

US08153482B2 Well-structure anti-punch-through microwire device 有权
标题翻译：良好的抗穿通微线设备
公开(公告)号：US08153482B2
公开(公告)日：2012-04-10
申请号：US12235359
申请日：2008-09-22
申请人： Mark Albert Crowder
发明人： Mark Albert Crowder
IPC分类号： H01L21/335
CPC分类号： H01L29/125 , B82Y10/00 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/78 , Y10S977/936
摘要： A well-structure anti-punch-through microwire device and associated fabrication method are provided. The method initially forms a microwire with alternating highly and lightly doped cylindrical regions. A channel ring is formed external to the microwire outer shell and surrounding a first dopant well-structure region in the microwire, between source and drain (S/D) regions of the microwire. The S/D regions are doped with a second dopant, opposite to the first dopant. A gate dielectric ring is formed surrounding the channel ring, and a gate electrode ring is formed surrounding the gate dielectric ring. The well-structure, in contrast to conventional micro or nanowire transistors, helps prevent the punch-through phenomena.
摘要翻译：提供了良好结构的抗穿通微线器件和相关的制造方法。该方法最初形成具有交替的高度和轻掺杂的圆柱形区域的微线。通道环形成在微线外壳的外部，并且包围微线中的微线的源极和漏极（S / D）区域之间的第一掺杂剂阱结构区域。 S / D区域掺杂有与第一掺杂剂相反的第二掺杂剂。围绕通道环形成栅介质环，并且围绕栅介质环形成栅电极环。与传统的微纳米线或纳米线晶体管相反，井结构有助于防止穿透现象。

4. 发明申请

US20130161643A1 Method for Fabricating Three-Dimensional Gallium Nitride Structures with Planar Surfaces 有权
标题翻译：用平面表面制造三维氮化镓结构的方法
公开(公告)号：US20130161643A1
公开(公告)日：2013-06-27
申请号：US13337843
申请日：2011-12-27
申请人： Mark Albert Crowder , Changqing Zhan , Paul J. Schuele
发明人： Mark Albert Crowder , Changqing Zhan , Paul J. Schuele
IPC分类号： H01L33/34 , H01L33/32
CPC分类号： H01L33/34 , H01L33/007 , H01L33/18 , H01L33/24 , H01L33/32
摘要： A method is provided for fabricating three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. After providing a substrate, the method grows a GaN film overlying a top surface of the substrate and forms cavities in a top surface of the GaN film. The cavities are formed using a laser ablation, ion implantation, sand blasting, or dry etching process. The cavities in the GaN film top surface are then wet etched, forming planar sidewalls extending into the GaN film. More explicitly, the cavities are formed into a c-plane GaN film top surface, and the planar sidewalls are formed perpendicular to a c-plane, in the m-plane or a-plane family.
摘要翻译：提供了一种用于制造具有平面表面的三维氮化镓（GaN）柱结构的方法。在提供衬底之后，该方法生长覆盖在衬底的顶表面上的GaN膜，并在GaN膜的顶表面中形成空腔。使用激光烧蚀，离子注入，喷砂或干蚀刻工艺形成空腔。然后湿式蚀刻GaN膜顶表面中的空腔，形成延伸到GaN膜中的平面侧壁。更明确地说，空腔形成为c面GaN薄膜顶表面，并且平面侧壁在m平面或a平面系列中垂直于c平面形成。

5. 发明授权

US08648328B2 Light emitting diode (LED) using three-dimensional gallium nitride (GaN) pillar structures with planar surfaces 有权
标题翻译：使用具有平面表面的三维氮化镓（GaN）柱结构的发光二极管（LED）
公开(公告)号：US08648328B2
公开(公告)日：2014-02-11
申请号：US13367120
申请日：2012-02-06
申请人： Mark Albert Crowder , Changqing Zhan , Paul J. Schuele
发明人： Mark Albert Crowder , Changqing Zhan , Paul J. Schuele
IPC分类号： H01L33/04
CPC分类号： H01L33/32 , H01L33/0075 , H01L33/04 , H01L33/06 , H01L33/08 , H01L33/18 , H01L33/24 , H01L33/42 , H01L2933/0008 , H01L2933/0016
摘要： A method is provided for fabricating a light emitting diode (LED) using three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. The method forms a plurality of GaN pillar structures, each with an n-doped GaN (n-GaN) pillar and planar sidewalls perpendicular to the c-plane, formed in either an m-plane or a-plane family. A multiple quantum well (MQW) layer is formed overlying the n-GaN pillar sidewalls, and a layer of p-doped GaN (p-GaN) is formed overlying the MQW layer. The plurality of GaN pillar structures are deposited on a first substrate, with the n-doped GaN pillar sidewalls aligned parallel to a top surface of the first substrate. A first end of each GaN pillar structure is connected to a first metal layer. The second end of each GaN pillar structure is etched to expose the n-GaN pillar second end and connected to a second metal layer.
摘要翻译：提供了一种使用具有平面表面的三维氮化镓（GaN）柱结构来制造发光二极管（LED）的方法。该方法形成多个GaN柱结构，每个GaN柱结构均具有n个掺杂的GaN（n-GaN）柱和垂直于c平面的平面侧壁，形成在m面或平面系列中。形成覆盖在n-GaN支柱侧壁上的多量子阱（MQW）层，并且在MQW层上形成一层p掺杂的GaN（p-GaN）层。多个GaN柱结构沉积在第一衬底上，其中n掺杂的GaN柱侧壁平行于第一衬底的顶表面排列。每个GaN柱结构的第一端连接到第一金属层。蚀刻每个GaN柱结构的第二端以暴露n-GaN柱的第二端并连接到第二金属层。

6. 发明授权

US07029961B2 Method for optimized laser annealing smoothing 失效
标题翻译：优化激光退火平滑的方法
公开(公告)号：US07029961B2
公开(公告)日：2006-04-18
申请号：US10913678
申请日：2004-08-05
申请人： Mark Albert Crowder , Yasuhiro Mitani , Apostolos T. Voutsas
发明人： Mark Albert Crowder , Yasuhiro Mitani , Apostolos T. Voutsas
IPC分类号： H01L21/3205
CPC分类号： H01L21/0268 , B23K26/066 , H01L21/2026
摘要： A laser annealing mask is provided with cross-hatched sub-resolution aperture patterns. The mask comprises a first section with aperture patterns for transmitting approximately 100% of incident light, and at least one section with cross-hatched sub-resolution aperture patterns for diffracting incident light. In one aspect, a second mask section with cross-hatched sub-resolution aperture patterns has an area adjacent a vertical edge and a third mask section with cross-hatched sub-resolution aperture patterns adjacent the opposite vertical edge, with the first mask section being located between the second and third mask sections. The section with cross-hatched sub-resolution aperture patterns transmits approximately 40% to 70%, and preferably 50% to 60% of incident light energy density. In some aspects, the section with cross-hatched sub-resolution aperture patterns includes a plurality of different cross-hatched aperture patterns. The cross-hatched sub-resolution aperture patterns can be defined by horizontal gap and slits, as well as vertical gap and slits.
摘要翻译：激光退火掩模具有交叉阴影的子分辨率孔径图案。掩模包括具有用于传输大约100％的入射光的孔径图案的第一部分和具有用于衍射入射光的交叉阴影的子分辨率孔径图案的至少一个部分。在一个方面，具有交叉阴影线的子分辨率孔径图案的第二掩模部分具有与垂直边缘相邻的区域和具有与相对的垂直边缘相邻的交叉阴影的子分辨率孔径图案的第三掩模部分，第一掩模部分是位于第二和第三掩模部分之间。具有交叉阴影的子分辨率孔径图案的部分透射入射光能密度的大约40％至70％，优选地为50％至60％。在一些方面，具有交叉阴影的子分辨率孔径图案的部分包括多个不同的交叉阴影孔径图案。交叉阴影的子分辨率孔径图案可以由水平间隙和狭缝以及垂直间隙和狭缝限定。

7. 发明授权

US06777276B2 System and method for optimized laser annealing smoothing mask 有权
标题翻译：优化激光退火平滑掩模的系统和方法
公开(公告)号：US06777276B2
公开(公告)日：2004-08-17
申请号：US10232089
申请日：2002-08-29
申请人： Mark Albert Crowder , Yasuhiro Mitani , Apostolos T. Voutsas
发明人： Mark Albert Crowder , Yasuhiro Mitani , Apostolos T. Voutsas
IPC分类号： H01L2100
CPC分类号： H01L21/0268 , B23K26/066 , H01L21/2026
摘要： A laser annealing mask is provided with cross-hatched sub-resolution aperture patterns. The mask comprises a first section with aperture patterns for transmitting approximately 100% of incident light, and at least one section with cross-hatched sub-resolution aperture patterns for diffracting incident light. In one aspect, a second mask section with cross-hatched sub-resolution aperture patterns has an area adjacent a vertical edge and a third mask section with cross-hatched sub-resolution aperture patterns adjacent the opposite vertical edge, with the first mask section being located between the second and third mask sections. The section with cross-hatched sub-resolution aperture patterns transmits approximately 40% to 70%, and preferably 50% to 60% of incident light energy density. In some aspects, the section with cross-hatched sub-resolution aperture patterns includes a plurality of different cross-hatched aperture patterns. The cross-hatched sub-resolution aperture patterns can be defined by horizontal gap and slits, as well as vertical gap and slits.
摘要翻译：激光退火掩模具有交叉阴影的子分辨率孔径图案。掩模包括具有用于传输大约100％的入射光的孔径图案的第一部分和具有用于衍射入射光的交叉阴影的子分辨率孔径图案的至少一个部分。在一个方面，具有交叉阴影线的子分辨率孔径图案的第二掩模部分具有与垂直边缘相邻的区域和具有与相对的垂直边缘相邻的交叉阴影的子分辨率孔径图案的第三掩模部分，第一掩模部分是位于第二和第三掩模部分之间。具有交叉阴影的子分辨率孔径图案的部分透射入射光能密度的大约40％至70％，优选地为50％至60％。在一些方面，具有交叉阴影的子分辨率孔径图案的部分包括多个不同的交叉阴影孔径图案。交叉阴影的子分辨率孔径图案可以由水平间隙和狭缝以及垂直间隙和狭缝限定。

8. 发明授权

US08685774B2 Method for fabricating three-dimensional gallium nitride structures with planar surfaces 有权
标题翻译：制备具有平面表面的三维氮化镓结构的方法
公开(公告)号：US08685774B2
公开(公告)日：2014-04-01
申请号：US13337843
申请日：2011-12-27
申请人： Mark Albert Crowder , Changqing Zhan , Paul J. Schuele
发明人： Mark Albert Crowder , Changqing Zhan , Paul J. Schuele
IPC分类号： H01L21/00
CPC分类号： H01L33/34 , H01L33/007 , H01L33/18 , H01L33/24 , H01L33/32
摘要： A method is provided for fabricating three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. After providing a substrate, the method grows a GaN film overlying a top surface of the substrate and forms cavities in a top surface of the GaN film. The cavities are formed using a laser ablation, ion implantation, sand blasting, or dry etching process. The cavities in the GaN film top surface are then wet etched, forming planar sidewalls extending into the GaN film. More explicitly, the cavities are formed into a c-plane GaN film top surface, and the planar sidewalls are formed perpendicular to a c-plane, in the m-plane or a-plane family.
摘要翻译：提供了一种用于制造具有平面表面的三维氮化镓（GaN）柱结构的方法。在提供衬底之后，该方法生长覆盖在衬底的顶表面上的GaN膜，并在GaN膜的顶表面中形成空腔。使用激光烧蚀，离子注入，喷砂或干蚀刻工艺形成空腔。然后湿式蚀刻GaN膜顶表面中的空腔，形成延伸到GaN膜中的平面侧壁。更明确地说，空腔形成为c面GaN薄膜顶表面，并且平面侧壁在m平面或a平面系列中垂直于c平面形成。

9. 发明申请

US20130161584A1 Light Emitting Diode (LED) Using Three-Dimensional Gallium Nitride (GaN) Pillar Structures with Planar Surfaces 有权
标题翻译：发光二极管（LED）使用三维氮化镓（GaN）柱状结构与平面表面
公开(公告)号：US20130161584A1
公开(公告)日：2013-06-27
申请号：US13367120
申请日：2012-02-06
申请人： Mark Albert CROWDER , Changqing ZHAN , Paul J. SCHUELE
发明人： Mark Albert CROWDER , Changqing ZHAN , Paul J. SCHUELE
IPC分类号： H01L33/04
CPC分类号： H01L33/32 , H01L33/0075 , H01L33/04 , H01L33/06 , H01L33/08 , H01L33/18 , H01L33/24 , H01L33/42 , H01L2933/0008 , H01L2933/0016
摘要： A method is provided for fabricating a light emitting diode (LED) using three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. The method forms a plurality of GaN pillar structures, each with an n-doped GaN (n-GaN) pillar and planar sidewalls perpendicular to the c-plane, formed in either an m-plane or a-plane family. A multiple quantum well (MQW) layer is formed overlying the n-GaN pillar sidewalls, and a layer of p-doped GaN (p-GaN) is formed overlying the MQW layer. The plurality of GaN pillar structures are deposited on a first substrate, with the n-doped GaN pillar sidewalls aligned parallel to a top surface of the first substrate. A first end of each GaN pillar structure is connected to a first metal layer. The second end of each GaN pillar structure is etched to expose the n-GaN pillar second end and connected to a second metal layer.
摘要翻译：提供了一种使用具有平面表面的三维氮化镓（GaN）柱结构来制造发光二极管（LED）的方法。该方法形成多个GaN柱结构，每个GaN柱结构均具有n个掺杂的GaN（n-GaN）柱和垂直于c平面的平面侧壁，形成在m面或平面系列中。形成覆盖在n-GaN支柱侧壁上的多量子阱（MQW）层，并且在MQW层上形成一层p掺杂的GaN（p-GaN）层。多个GaN柱结构沉积在第一衬底上，其中n掺杂的GaN柱侧壁平行于第一衬底的顶表面排列。每个GaN柱结构的第一端连接到第一金属层。蚀刻每个GaN柱结构的第二端以暴露n-GaN柱的第二端并连接到第二金属层。

10. 发明申请

US20120168711A1 Narrow-Waist Nanowire Transistor with Wide Aspect Ratio Ends 审中-公开
标题翻译：具有宽纵横比的窄腰纳米线晶体管
公开(公告)号：US20120168711A1
公开(公告)日：2012-07-05
申请号：US12984641
申请日：2011-01-05
申请人： Mark Albert Crowder , Paul J. Schuele
发明人： Mark Albert Crowder , Paul J. Schuele
IPC分类号： H01L29/08 , H01L21/84 , B82Y40/00 , B82Y99/00
CPC分类号： H01L29/78696 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/122 , H01L29/42392
摘要： A method is provided for forming narrow-waist nanowire (NW) transistors with wide aspect ratio ends. The method provides a semiconductor-on-insulator wafer. The top semiconductor layer is etched to form a first pad, a second pad, and a plurality of narrow-waist semiconductor bridges. Each semiconductor bridge has two ends, each with a first width, attached to the first and second pads, and a mid-section less than the first width. A channel is formed in a center portion of each mid-section, a drain interposed between the channel and the first end, a source interposed between the channel and the second end, and a gate dielectric surrounding the channel and adjacent portions of the source and drain. A gate electrode is formed surrounding the gate dielectric. The semiconductor bridge ends are etched from the first and second pads, forming a plurality of narrow-waist semiconductor NW transistors.
摘要翻译：提供一种用于形成具有宽纵横比端的窄腰纳米线（NW）晶体管的方法。该方法提供绝缘体上半导体晶片。蚀刻顶部半导体层以形成第一焊盘，第二焊盘和多个窄腰半导体桥。每个半导体桥具有两个端部，每个端部具有连接到第一和第二焊盘的第一宽度，以及小于第一宽度的中间部分。在每个中间部分的中心部分形成通道，插入在通道和第一端之间的漏极，介于通道和第二端之间的源极以及围绕通道和源极的相邻部分的栅极电介质，以及排水。围绕栅极电介质形成栅电极。从第一和第二焊盘蚀刻半导体桥端，形成多个窄腰半导体NW晶体管。

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