专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08236631B2 Four-transistor Schmitt trigger inverter with hysteresis 有权
标题翻译：具有迟滞的四晶体管施密特触发器
公开(公告)号：US08236631B2
公开(公告)日：2012-08-07
申请号：US12644061
申请日：2009-12-22
申请人： Themistokles Afentakis , Apostolos T. Voutsas , Paul J. Schuele
发明人： Themistokles Afentakis , Apostolos T. Voutsas , Paul J. Schuele
IPC分类号： H01L21/00 , H01L29/76
CPC分类号： H03K3/3565 , H01L29/78624 , H01L29/78642 , H01L29/78648
摘要： A four-transistor Schmitt trigger inverter is provided. The Schmitt trigger inverter is made from an n-channel MOS (NMOS) dual-gate thin-film transistor (DG-TFT) and a p-channel MOS (PMOS) DG-TFT, both DG-TFTs having a top gate, a back gate, and source/drain regions. A (conventional) NMOS TFT has a gate connected to an NMOS DG-TFT first S/D region and a PMOS DG-TFT first S/D region. The NMOS TFT also has a first S/D region connected to the NMOS DG-TFT back gate and the PMOS DG-TFT back gate. A (conventional) PMOS TFT has a gate connected to the NMOS TFT gate, and a first S/D region connected to the NMOS TFT first S/D region.
摘要翻译：提供了一个四晶体管施密特触发器。施密特触发逆变器由n沟道MOS（NMOS）双栅极薄膜晶体管（DG-TFT）和p沟道MOS（PMOS）DG-TFT制成，两个DG-TFT都具有顶栅极，背栅极和源极/漏极区域。（常规）NMOS TFT具有连接到NMOS DG-TFT第一S / D区和PMOS DG-TFT第一S / D区的栅极。 NMOS TFT还具有连接到NMOS DG-TFT背栅和PMOS DG-TFT后栅的第一S / D区。（传统）PMOS TFT具有连接到NMOS TFT栅极的栅极和连接到NMOS TFT第一S / D区域的第一S / D区域。

2. 发明授权

US07872309B2 Self-aligned lightly doped drain recessed-gate thin-film transistor 有权
标题翻译：自对准轻掺杂漏极栅极薄膜晶体管
公开(公告)号：US07872309B2
公开(公告)日：2011-01-18
申请号：US12140017
申请日：2008-06-16
申请人： Paul J. Schuele , Mark A. Crowder , Apostolos T. Voutsas , Hidayat Kisdarjono
发明人： Paul J. Schuele , Mark A. Crowder , Apostolos T. Voutsas , Hidayat Kisdarjono
IPC分类号： H01L27/12 , H01L29/786
CPC分类号： H01L29/78621 , H01L29/66621 , H01L29/66757 , H01L29/78627
摘要： A recessed-gate thin-film transistor (RG-TFT) with a self-aligned lightly doped drain (LDD) is provided, along with a corresponding fabrication method. The method deposits an insulator overlying a substrate and etches a trench in the insulator. The trench has a bottom and sidewalls. An active silicon (Si) layer is formed overlying the insulator and trench, with a gate oxide layer over the active Si layer. A recessed gate electrode is then formed in the trench. The TFT is doped and LDD regions are formed in the active Si layer overlying the trench sidewalls. The LDD regions have a length that extends from a top of the trench sidewall, to the trench bottom, with a doping density that decreases in response to the LDD length. Alternately stated, the LDD length is directly related to the depth of the trench.
摘要翻译：提供了具有自对准轻掺杂漏极（LDD）的凹入栅极薄膜晶体管（RG-TFT）以及相应的制造方法。该方法沉积覆盖衬底的绝缘体并蚀刻绝缘体中的沟槽。沟槽有一个底部和侧壁。在绝缘体和沟槽上形成有源硅（Si）层，在有源Si层上方形成栅极氧化层。然后在沟槽中形成凹陷栅电极。 TFT是掺杂的，并且LDD区域形成在覆盖沟槽侧壁的有源Si层中。 LDD区域具有从沟槽侧壁的顶部延伸到沟槽底部的长度，其掺杂密度响应于LDD长度而减小。替代地，LDD长度与沟槽的深度直接相关。

3. 发明授权

US07378309B2 Method of fabricating local interconnects on a silicon-germanium 3D CMOS 有权
标题翻译：在硅 - 锗3D CMOS上制造局部互连的方法
公开(公告)号：US07378309B2
公开(公告)日：2008-05-27
申请号：US11376542
申请日：2006-03-15
申请人： Jong-Jan Lee , Paul J. Schuele , Sheng Teng Hsu , Jer-Shen Maa
发明人： Jong-Jan Lee , Paul J. Schuele , Sheng Teng Hsu , Jer-Shen Maa
IPC分类号： H01L21/8234
CPC分类号： H01L21/823871 , H01L21/02532 , H01L21/02667 , H01L21/28525 , H01L21/76895 , H01L27/11 , H01L27/1108
摘要： A method of fabricating local interconnect on a silicon-germanium 3D CMOS includes fabricating an active silicon CMOS device on a silicon substrate. An insulator layer is deposited on the silicon substrate and a seed window is opened through the insulator layer to the silicon substrate and to a silicon CMOS device gate. A germanium thin film is deposited on the insulator layer and into windows, forming a contact between the germanium thin film and the silicon device. The germanium thin film is encapsulated in a dielectric material. The wafer is heated at a temperature sufficient to flow the germanium, while maintaining the other layers in a solid condition. The wafer is cooled to solidify the germanium as single crystal germanium and as polycrystalline germanium, which provides local interconnects. Germanium CMOS devices may be fabricated on the single crystal germanium thin film.
摘要翻译：在硅 - 锗3D CMOS上制造局部互连的方法包括在硅衬底上制造有源硅CMOS器件。绝缘体层沉积在硅衬底上，并且晶种窗通过绝缘体层向硅衬底和硅CMOS器件栅极打开。在绝缘体层和窗口上沉积锗薄膜，形成锗薄膜和硅器件之间的接触。锗薄膜被封装在电介质材料中。在足以使锗流动的温度下加热晶片，同时将其它层保持在固体状态。将晶片冷却以将锗固化为单晶锗和作为多晶锗，其提供局部互连。可以在单晶锗薄膜上制造锗CMOS器件。

4. 发明申请

US20080079663A1 Micro-pixelated fluid-assay precursor structure 审中-公开
标题翻译：微像素化流体测定前体结构
公开(公告)号：US20080079663A1
公开(公告)日：2008-04-03
申请号：US11821148
申请日：2007-06-22
申请人： John W. Hartzell , Pooran Chandra Joshi , Paul J. Schuele
发明人： John W. Hartzell , Pooran Chandra Joshi , Paul J. Schuele
IPC分类号： G09G3/20
CPC分类号： G06Q10/08 , G06Q40/04
摘要： A pixel-by-pixel, digitally-addressable, pixelated, precursor, fluid-assay, active-matrix micro-structure including plural pixels formed on a substrate, wherein each pixel includes (a) at least one non-functionalized, digitally-addressable assay sensor, and (b), disposed operatively adjacent this sensor, digitally-addressable and energizable electromagnetic field-creating structure which is selectively energizable to create, in the vicinity of the at least one assay sensor, an ambient electromagnetic field environment which is structured to assist in functionalizing, as a possession on said at least one assay sensor, at least one digitally-addressable assay site which will display an affinity for a selected fluid-assay material.
摘要翻译：逐像素，可数字寻址，像素化，前体，流体测定，包括形成在衬底上的多个像素的有源矩阵微结构，其中每个像素包括（a）至少一个非功能化的，可数字寻址的和（b），其可操作地邻近该传感器设置，可数字寻址和激励的电磁场产生结构，其被选择性地激励以在所述至少一个测定传感器附近产生环境电磁场环境，所述环境电磁场环境被构造在所述至少一个测定传感器上辅助功能化至少一个可显示对所选择的流体测定材料的亲和性的可数字寻址的测定位点。

5. 发明授权

US07238554B2 Simultaneous planar and non-planar thin-film transistor processes 失效
标题翻译：同时平面和非平面薄膜晶体管工艺
公开(公告)号：US07238554B2
公开(公告)日：2007-07-03
申请号：US10985587
申请日：2004-11-09
申请人： Paul J. Schuele , Apostolos T. Voutsas
发明人： Paul J. Schuele , Apostolos T. Voutsas
IPC分类号： H01L21/00
CPC分类号： H01L27/12 , H01L29/78624 , H01L29/78642 , H01L29/78648 , H01L29/78675
摘要： A method is provided for concurrently forming MP-TFTs and P-TFTs. Generally, the method comprises: forming a P-TFT having source/drain (S/D) regions, an intervening channel region, and a gate, all in a first horizontal plane; and simultaneously forming a MP-TFT having a first gate in the first horizontal plane and at least one S/D region in a second horizontal plane, overlying the first horizontal plane. The vertical TFT (V-TFT) is an MP-TFT having vertical first gate sidewalls and a vertical channel region overlying a gate sidewall. The dual-gate TFT (DG-TFT) is an MP-TFT having a bottom gate, first and second S/D regions with top surfaces, an intervening channel region with a top surface, and a second, top gate with a bottom surface, all in a second horizontal plane, overlying the first horizontal plane.
摘要翻译：提供了用于同时形成MP-TFT和P-TFT的方法。通常，该方法包括：在第一水平面中形成具有源极/漏极（S / D）区域，中间沟道区域和栅极的P-TFT; 同时在第一水平面上形成具有第一栅极的MP-TFT和位于第一水平面上的第二水平面中的至少一个S / D区域。垂直TFT（V-TFT）是具有垂直的第一栅极侧壁和覆盖栅极侧壁的垂直沟道区的MP-TFT。双栅极TFT（DG-TFT）是具有底栅，具有顶表面的第一和第二S / D区，具有顶表面的中间沟道区和具有底表面的第二顶栅的MP-TFT 都在第二个水平面上，覆盖着第一个水平面。

6. 发明授权

US06313031B1 Method of fabricating a contract structure having a composite barrier layer between a platinum layer and a polysilicon plug 失效
标题翻译：制造在铂层和多晶硅插塞之间具有复合阻挡层的合同结构的方法
公开(公告)号：US06313031B1
公开(公告)日：2001-11-06
申请号：US09535050
申请日：2000-03-24
申请人： Paul J. Schuele , Pierre C. Fazan
发明人： Paul J. Schuele , Pierre C. Fazan
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： This invention is a process for forming an effective titanium nitride barrier layer between the upper surface of a polysilicon plug formed in a thick dielectric layer and a platinum lower capacitor plate in a dynamic random access memory which is being fabricated on a silicon wafer.
摘要翻译：本发明是一种在制造在硅晶片上的动态随机存取存储器中，在形成于厚电介质层的多晶硅插塞的上表面和铂下电容器板之间形成有效的氮化钛阻挡层的工艺。

7. 发明授权

US6049101A Processing methods of forming a capacitor, and capacitor construction 失效
公开(公告)号：US6049101A
公开(公告)日：2000-04-11
申请号：US36702
申请日：1998-03-06
申请人： Thomas M. Graettinger , Paul J. Schuele , Pierre C. Fazan , Li Li , Zhiqiang Wu , Kunal R. Parekh , Thomas Arthur Figura
发明人： Thomas M. Graettinger , Paul J. Schuele , Pierre C. Fazan , Li Li , Zhiqiang Wu , Kunal R. Parekh , Thomas Arthur Figura
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L28/84
摘要： Capacitors and methods of forming capacitors are described. According to one implementation, a capacitor opening is formed over a substrate node location. Electrically conductive material is subsequently formed within the capacitor opening and makes an electrical connection with the node location. A protuberant insulative structure is formed within the capacitor opening and includes a lateral outer surface at least a portion of which is supported by and extends elevationally below adjacent conductive material. First and second capacitor plates and a dielectric layer therebetween are formed within the capacitor opening and supported by the protuberant structure. In one aspect, the conductive material is formed to occupy less than all of the capacitor opening and to leave a void therewithin, with the protuberant structure substantially, if not completely filling in the void. In another aspect, the conductive material is formed to occupy less than all of the capacitor opening and to leave a void therewithin, with the protuberant structure only partially filling in the void to provide a tubular structure.

8. 发明授权

US5760474A Capacitor, integrated circuitry, diffusion barriers, and method for forming an electrically conductive diffusion barrier 失效
公开(公告)号：US5760474A
公开(公告)日：1998-06-02
申请号：US675997
申请日：1996-07-09
申请人： Paul J. Schuele
发明人： Paul J. Schuele
IPC分类号： H01L21/02 , H01L21/8242 , H01L29/92 , H01L23/48 , H01L27/108
CPC分类号： H01L28/40 , H01L27/1085
摘要： A capacitor having a pair of conductive electrodes separated by a dielectric layer and wherein at least one of the electrodes comprise Ti.sub.x Al.sub.1-x N, and wherein the variable "x" lies in a range of about 0.4 to about 0.8. The invention also contemplates a method for forming an electrically conductive diffusion barrier on a silicon substrate and which comprises providing a chemical vapor deposition reactor having a chamber; positioning the silicon substrate in the chemical vapor deposition reactor chamber; providing a source of gaseous titanium aluminum and nitrogen to the chemical vapor deposition reactor chamber; and providing temperature and pressure conditions in the chemical vapor deposition reactor chamber effective to deposit an electrically conductive diffusion barrier layer on the silicon substrate comprising Ti.sub.x Al.sub.1-x N, and wherein the variable "x" is in a range of about 0.4 to about 0.8.

9. 发明授权

US08896907B2 Plasmonic reflective display fabricated using anodized aluminum oxide 有权
标题翻译：使用阳极氧化铝制造的等离子体反射显示器
公开(公告)号：US08896907B2
公开(公告)日：2014-11-25
申请号：US13449370
申请日：2012-04-18
申请人： Douglas J. Tweet , Akinori Hashimura , Paul J. Schuele , Apostolos T. Voutsas
发明人： Douglas J. Tweet , Akinori Hashimura , Paul J. Schuele , Apostolos T. Voutsas
IPC分类号： G02B26/00 , G02F1/1335
CPC分类号： G02F1/133553 , G02F1/19 , G02F2201/124 , G02F2203/10
摘要： A method is provided for forming a reflective plasmonic display. The method provides a substrate and deposits a bottom dielectric layer. A conductive film is deposited overlying the bottom dielectric layer. A hard mask is formed with nano-size openings overlying the conductive film. The conductive film is plasma etched via nano-size openings in the hard mask, stopping at the dielectric layer. After removing the hard mask, a conductive film is left with nano-size openings to the dielectric layer. Metal is deposited in the nano-size openings, creating a pattern of metallic nanoparticles overlying the dielectric layer. Then, the conductive film is removed. The hard mask may be formed by conformally depositing an Al film overlying the conductive film and anodizing the Al film, creating a hard mask of porous anodized Al oxide (AAO) film. The porous AAO film may form a short-range hexagonal, and long-range random order hole patterns.
摘要翻译：提供了形成反射等离子体显示器的方法。该方法提供衬底并沉积底部电介质层。沉积覆盖在底部介电层上的导电膜。形成具有覆盖导电膜的纳米尺寸开口的硬掩模。导电膜通过硬掩模中的纳米尺寸开口进行等离子体蚀刻，停留在电介质层。在去除硬掩模之后，导电膜留下具有到介电层的纳米尺寸的开口。金属沉积在纳米尺寸的开口中，形成覆盖在介电层上的金属纳米颗粒图案。然后，去除导电膜。硬掩模可以通过共形沉积覆盖在导电膜上的Al膜并阳极氧化Al膜，形成多孔阳极氧化Al氧化物（AAO）膜的硬掩模来形成。多孔AAO膜可以形成短程六边形和长程随机顺序孔图案。

10. 发明授权

US08236571B2 Method of making micro-pixelated fluid-assay precursor structure 有权
标题翻译：制备微像素化流体测定前体结构的方法
公开(公告)号：US08236571B2
公开(公告)日：2012-08-07
申请号：US11827175
申请日：2007-07-10
申请人： John W. Hartzell , Pooran Chandra Joshi , Paul J. Schuele
发明人： John W. Hartzell , Pooran Chandra Joshi , Paul J. Schuele
IPC分类号： G01N21/00
CPC分类号： B81C1/00246 , B81B2201/0214 , B81C2203/075 , Y10S436/805
摘要： A method of producing a precursor, active-matrix, fluid-assay micro-structure including the steps of (1) utilizing low-temperature TFT and Si technology, establishing preferably on a glass or plastic substrate a matrix array of non-functionalized pixels, and (2) preparing at least one of these pixels for individual, digitally-addressed (a) functionalization, and (b) reading out, ultimately, of completed assay results.
摘要翻译：一种制备前体，活性基质，流体测定微结构的方法，包括以下步骤：（1）利用低温TFT和Si技术，优选在玻璃或塑料基材上建立非官能化像素的矩阵阵列，和（2）准备用于个体，数字寻址（a）功能化的这些像素中的至少一个，以及（b）最终读出完成的测定结果。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式