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1. 发明授权

US07210109B2 Equivalence checking of scan path flush operations 失效
标题翻译：扫描路径冲洗操作的等效性检查
公开(公告)号：US07210109B2
公开(公告)日：2007-04-24
申请号：US10875476
申请日：2004-06-24
申请人： Kenneth Michael Caron , Robert Lowell Kanzelman , Scott Henry Mack , Lance Gordon Thompson , Mark Allen Williams
发明人： Kenneth Michael Caron , Robert Lowell Kanzelman , Scott Henry Mack , Lance Gordon Thompson , Mark Allen Williams
IPC分类号： G07F17/50
CPC分类号： G06F17/504
摘要： A method, apparatus, system, and signal-bearing medium that in an embodiment apply a latch behavior to a first and second netlist, where the latch behavior exhibits transparent behavior. Flush enabling conditions are applied to the first netlist and a second netlist. For each latch in a first scan chain in the first netlist, a corresponding latch in the second netlist is found. Cones of logic are then extracted from the latches under the constraints enabling the flush operation, and the cones of logic are compared for functional equivalence. If all the cones are functionally equivalent, then the flush reset states of the netlists are functionally equivalent. If at least one of the cones is not functionally equivalent, then the flush reset states of the two netlists are not equivalent.
摘要翻译：一种方法，装置，系统和信号承载介质，其在一个实施例中将锁存行为应用于第一和第二网表，其中锁存行为呈现透明行为。刷新启用条件应用于第一个网表和第二个网表。对于第一网表中的第一扫描链中的每个锁存器，找到第二网表中的相应锁存器。然后，在启用冲洗操作的约束下，从锁存器中提取逻辑锥，并且将功能对等的逻辑锥进行比较。如果所有锥体在功能上相当，则网表的刷新复位状态在功能上相当。如果至少一个锥体在功能上不相等，则两个网表的刷新复位状态不相等。

2. 发明申请

US20120192133A1 LOGIC DESIGN VERIFICATION TECHNIQUES FOR LIVENESS CHECKING WITH RETIMING 有权
标题翻译：用于生活垃圾检查的LOGIC设计验证技术
公开(公告)号：US20120192133A1
公开(公告)日：2012-07-26
申请号：US13436196
申请日：2012-03-30
申请人： Jason R. Baumgartner , Gabor Bobok , Paul Joseph Roessler , Mark Allen Williams
发明人： Jason R. Baumgartner , Gabor Bobok , Paul Joseph Roessler , Mark Allen Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/504 , G06F2217/84
摘要： A technique for verification of a retimed logic design using liveness checking includes assigning a liveness gate to a liveness property for an original netlist and assigning a fairness gate to a fairness constraint for the original netlist. In this case, the fairness gate is associated with the liveness gate and is asserted for at least one time-step during any valid behavioral loop associated with the liveness gate. The original netlist is retimed, using a retiming engine, to provide a retimed netlist. The liveness and fairness gates of the retimed netlist are retimed such that a lag of the fairness gate is no greater than a lag of the liveness gate. Verification analysis is then performed on the retimed netlist. Finally, when the verification analysis yields a valid counter-example trace for the retimed netlist, a liveness violation for the original netlist is returned.
摘要翻译：用于使用活动检查验证重新定时逻辑设计的技术包括将活跃门分配给原始网表的活动属性，并将公平门分配给原始网表的公平约束。在这种情况下，公平门与活跃门相关联，并且在与活跃门相关联的任何有效行为循环期间被断言至少一个时间步长。使用重新定时引擎重新计算原始网表，以提供重新定时的网表。重新定义的网表的活跃和公平的门被重新定位，使得公平门的滞后不大于活跃门的滞后。然后在重新定时的网表上进行验证分析。最后，当验证分析为重新定时的网表产生有效的对照示例时，返回原始网表的活动违反。

3. 发明授权

US06993734B2 Use of time step information in a design verification system 失效
标题翻译：在设计验证系统中使用时间步信息
公开(公告)号：US06993734B2
公开(公告)日：2006-01-31
申请号：US10371002
申请日：2003-02-20
申请人： Jason Raymond Baumgartner , Hari Mony , Viresh Paruthi , Mark Allen Williams
发明人： Jason Raymond Baumgartner , Hari Mony , Viresh Paruthi , Mark Allen Williams
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5022
摘要： The disclosed design verification system includes a verification engine to model the operation of an integrated circuit and to assess the model's adherence to a property during N time steps of its operation. The value of N is recorded and propagated. The propagated value of N is used to reduce resources expended during subsequent analysis of the integrated circuit by ignoring the model's adherence to the property during the early stages of subsequent analysis (during time steps less than N). The system may include a diameter estimator that identifies a value of N beyond which subsequent modeling of the integrated circuit produces no new states. Property checking is ignored during states having a time step value greater than the estimated diameter.
摘要翻译：所公开的设计验证系统包括验证引擎，用于对集成电路的操作进行建模，并且在其操作的N个时间步骤期间评估模型对属性的遵守性。 N的值被记录和传播。 N的传播值用于通过忽略模型在后续分析的早期阶段（在小于N的时间步长期间）对属性的依赖性来减少在后续分析集成电路期间消耗的资源。系统可以包括识别N的值的直径估计器，超过该值，集成电路的后续建模不产生新的状态。在具有大于估计直径的时间步长值的状态下，属性检查被忽略。

4. 发明授权

US08407641B2 Logic design verification techniques for liveness checking with retiming 有权
标题翻译：重新定义活动检查的逻辑设计验证技术
公开(公告)号：US08407641B2
公开(公告)日：2013-03-26
申请号：US13436196
申请日：2012-03-30
申请人： Jason R. Baumgartner , Gabor Bobok , Paul Joseph Roessler , Mark Allen Williams
发明人： Jason R. Baumgartner , Gabor Bobok , Paul Joseph Roessler , Mark Allen Williams
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031 , G06F17/504 , G06F2217/84
摘要： A technique for verification of a retimed logic design using liveness checking includes assigning a liveness gate to a liveness property for an original netlist and assigning a fairness gate to a fairness constraint for the original netlist. In this case, the fairness gate is associated with the liveness gate and is asserted for at least one time-step during any valid behavioral loop associated with the liveness gate. The original netlist is retimed, using a retiming engine, to provide a retimed netlist. The liveness and fairness gates of the retimed netlist are retimed such that a lag of the fairness gate is no greater than a lag of the liveness gate. Verification analysis is then performed on the retimed netlist. Finally, when the verification analysis yields a valid counter-example trace for the retimed netlist, a liveness violation for the original netlist is returned.
摘要翻译：用于使用活动检查验证重新定时逻辑设计的技术包括将活跃门分配给原始网表的活动属性，并将公平门分配给原始网表的公平约束。在这种情况下，公平门与活跃门相关联，并且在与活跃门相关联的任何有效行为循环期间被断言至少一个时间步长。使用重新定时引擎重新计算原始网表，以提供重新定时的网表。重新定义的网表的活跃和公平的门被重新定位，使得公平门的滞后不大于活跃门的滞后。然后在重新定时的网表上进行验证分析。最后，当验证分析为重新定时的网表产生有效的对照示例时，返回原始网表的活动违反。

5. 发明授权

US08255848B2 Logic design verification techniques for liveness checking with retiming 有权
标题翻译：重新定义活动检查的逻辑设计验证技术
公开(公告)号：US08255848B2
公开(公告)日：2012-08-28
申请号：US12394560
申请日：2009-02-27
申请人： Jason R. Baumgartner , Gabor Bobok , Paul Joseph Roessler , Mark Allen Williams
发明人： Jason R. Baumgartner , Gabor Bobok , Paul Joseph Roessler , Mark Allen Williams
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031 , G06F17/504 , G06F2217/84
摘要： A technique for verification of a retimed logic design using liveness checking includes assigning a liveness gate to a liveness property for an original netlist and assigning a fairness gate to a fairness constraint for the original netlist. In this case, the fairness gate is associated with the liveness gate and is asserted for at least one time-step during any valid behavioral loop associated with the liveness gate. The original netlist is retimed, using a retiming engine, to provide a retimed netlist. The liveness and fairness gates of the retimed netlist are retimed such that a lag of the fairness gate is no greater than a lag of the liveness gate. Verification analysis is then performed on the retimed netlist. Finally, when the verification analysis yields a valid counter-example trace for the retimed netlist, a liveness violation for the original netlist is returned.
摘要翻译：用于使用活动检查验证重新定时逻辑设计的技术包括将活跃门分配给原始网表的活动属性，并将公平门分配给原始网表的公平约束。在这种情况下，公平门与活跃门相关联，并且在与活跃门相关联的任何有效行为循环期间被断言至少一个时间步长。使用重新定时引擎重新计算原始网表，以提供重新定时的网表。重新定义的网表的活跃和公平的门被重新定位，使得公平门的滞后不大于活跃门的滞后。然后在重新定时的网表上进行验证分析。最后，当验证分析为重新定时的网表产生有效的对照示例时，返回原始网表的活动违反。

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