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1. 发明申请

US20120192133A1 LOGIC DESIGN VERIFICATION TECHNIQUES FOR LIVENESS CHECKING WITH RETIMING 有权
标题翻译：用于生活垃圾检查的LOGIC设计验证技术
公开(公告)号：US20120192133A1
公开(公告)日：2012-07-26
申请号：US13436196
申请日：2012-03-30
申请人： Jason R. Baumgartner , Gabor Bobok , Paul Joseph Roessler , Mark Allen Williams
发明人： Jason R. Baumgartner , Gabor Bobok , Paul Joseph Roessler , Mark Allen Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/504 , G06F2217/84
摘要： A technique for verification of a retimed logic design using liveness checking includes assigning a liveness gate to a liveness property for an original netlist and assigning a fairness gate to a fairness constraint for the original netlist. In this case, the fairness gate is associated with the liveness gate and is asserted for at least one time-step during any valid behavioral loop associated with the liveness gate. The original netlist is retimed, using a retiming engine, to provide a retimed netlist. The liveness and fairness gates of the retimed netlist are retimed such that a lag of the fairness gate is no greater than a lag of the liveness gate. Verification analysis is then performed on the retimed netlist. Finally, when the verification analysis yields a valid counter-example trace for the retimed netlist, a liveness violation for the original netlist is returned.
摘要翻译：用于使用活动检查验证重新定时逻辑设计的技术包括将活跃门分配给原始网表的活动属性，并将公平门分配给原始网表的公平约束。在这种情况下，公平门与活跃门相关联，并且在与活跃门相关联的任何有效行为循环期间被断言至少一个时间步长。使用重新定时引擎重新计算原始网表，以提供重新定时的网表。重新定义的网表的活跃和公平的门被重新定位，使得公平门的滞后不大于活跃门的滞后。然后在重新定时的网表上进行验证分析。最后，当验证分析为重新定时的网表产生有效的对照示例时，返回原始网表的活动违反。

2. 发明申请

US20110022373A1 MODEL CHECKING OF LIVENESS PROPERTY IN A PHASE ABSTRACTED MODEL 有权
标题翻译：在相位抽象模型中检验生活物质的模型
公开(公告)号：US20110022373A1
公开(公告)日：2011-01-27
申请号：US12507099
申请日：2009-07-22
申请人： Jason Raymond Baumgartner , Shaked Flur , Ziv Nevo , Paul Joseph Roessler
发明人： Jason Raymond Baumgartner , Shaked Flur , Ziv Nevo , Paul Joseph Roessler
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： Phase abstraction may be utilized to increase efficiency of model checking techniques. A liveness property may be checked in respect to a phase abstracted model by modifying the liveness property in accordance with the phase abstracted model. A fairness property may be modified to ensure that the fairness property is held by the model checker. A counter-example produced by a model checker is modified to be in accordance to an original model. The counter-example comprises a repetitive behavior. The counter-example may be modified to shorten the repetitive behavior or to apply the repetitive behavior in an earlier cycle of the counter-example.
摘要翻译：可以利用相位抽象来提高模型检查技术的效率。可以通过根据相位抽象模型修改活性属性来检查相位抽象模型的活跃性。可以修改公平财产，以确保公平性由模型检查员持有。由模型检查器产生的对照例被修改为与原始模型一致。反例包括重复行为。可以修改对照例以缩短重复行为或者在反例的早期循环中应用重复行为。

3. 发明授权

US08352894B2 Verification techniques for liveness checking of logic designs 有权
标题翻译：逻辑设计的活性检查验证技术
公开(公告)号：US08352894B2
公开(公告)日：2013-01-08
申请号：US13403799
申请日：2012-02-23
申请人： Jason R. Baumgartner , Paul Joseph Roessler , Ohad Shacham , Jiazhao Xu
发明人： Jason R. Baumgartner , Paul Joseph Roessler , Ohad Shacham , Jiazhao Xu
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A technique for verification of a logic design using a liveness-to-safety conversion includes assigning liveness gates for liveness properties of a netlist and assigning a single loop gate to provide a loop signal for the liveness gates. Assertion of the single loop gate is prevented when none of the liveness gates are asserted. A first state of the netlist is sampled and the sampled first state provides an initial state for a first behavioral loop for at least one of the liveness gates following the assertion of the single loop gate. The sampled first state of the first behavioral loop is compared with a later state of the first behavioral loop to determine if the sampled first state is repeated. A liveness violation is returned when the sampled first state is repeated and an associated one of the liveness gates remains asserted for a duration of the first behavioral loop.
摘要翻译：用于验证使用安全性转换的逻辑设计的技术包括为网表的活动属性分配活动门，并分配单个循环门以为活跃门提供循环信号。当没有活动门被断言时，防止单回路门的断言。对网表的第一状态进行采样，并且采样的第一状态为在单循环门的断言之后的活动门中的至少一个为第一行为环提供初始状态。将第一行为循环的采样的第一状态与第一行为循环的稍后状态进行比较，以确定是否重复采样的第一状态。当重复采样的第一状态并且在第一行为循环的持续时间内相关联的一个活动门保持断言时，返回活动违反。

4. 发明授权

US08627273B2 Model checking of liveness property in a phase abstracted model 有权
标题翻译：相位抽象模型中活性属性的模型检验
公开(公告)号：US08627273B2
公开(公告)日：2014-01-07
申请号：US12507099
申请日：2009-07-22
申请人： Jason Raymond Baumgartner , Shaked Flur , Ziv Nevo , Paul Joseph Roessler
发明人： Jason Raymond Baumgartner , Shaked Flur , Ziv Nevo , Paul Joseph Roessler
IPC分类号： G06F9/44
CPC分类号： G06F17/504
摘要： Phase abstraction may be utilized to increase efficiency of model checking techniques. A liveness property may be checked in respect to a phase abstracted model by modifying the liveness property in accordance with the phase abstracted model. A fairness property may be modified to ensure that the fairness property is held by the model checker. A counter-example produced by a model checker is modified to be in accordance to an original model. The counter-example comprises a repetitive behavior. The counter-example may be modified to shorten the repetitive behavior or to apply the repetitive behavior in an earlier cycle of the counter-example.
摘要翻译：可以利用相位抽象来提高模型检查技术的效率。可以通过根据相位抽象模型修改活性属性来检查相位抽象模型的活跃性。可以修改公平财产，以确保公平性由模型检查员持有。由模型检查器产生的对照例被修改为与原始模型一致。反例包括重复行为。可以修改对照例以缩短重复行为或者在反例的早期循环中应用重复行为。

5. 发明申请

US20100223584A1 Logic Design Verification Techniques for Liveness Checking With Retiming 有权
标题翻译：逻辑设计验证技术，用于重新定义活动检查
公开(公告)号：US20100223584A1
公开(公告)日：2010-09-02
申请号：US12394560
申请日：2009-02-27
申请人： Jason R. Baumgartner , Gabor Bobok , Paul Joseph Roessler , Mark Williams
发明人： Jason R. Baumgartner , Gabor Bobok , Paul Joseph Roessler , Mark Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/504 , G06F2217/84
摘要： A technique for verification of a retimed logic design using liveness checking includes assigning a liveness gate to a liveness property for an original netlist and assigning a fairness gate to a fairness constraint for the original netlist. In this case, the fairness gate is associated with the liveness gate and is asserted for at least one time-step during any valid behavioral loop associated with the liveness gate. The original netlist is retimed, using a retiming engine, to provide a retimed netlist. The liveness and fairness gates of the retimed netlist are retimed such that a lag of the fairness gate is no greater than a lag of the liveness gate. Verification analysis is then performed on the retimed netlist. Finally, when the verification analysis yields a valid counter-example trace for the retimed netlist, a liveness violation for the original netlist is returned.
摘要翻译：用于使用活动检查验证重新定时逻辑设计的技术包括将活跃门分配给原始网表的活动属性，并将公平门分配给原始网表的公平约束。在这种情况下，公平门与活跃门相关联，并且在与活跃门相关联的任何有效行为循环期间被断言至少一个时间步长。使用重新定时引擎重新计算原始网表，以提供重新定时的网表。重新定义的网表的活跃和公平的门被重新定位，使得公平门的滞后不大于活跃门的滞后。然后在重新定时的网表上进行验证分析。最后，当验证分析为重新定时的网表产生有效的对照示例时，返回原始网表的活动违反。

6. 发明授权

US08407641B2 Logic design verification techniques for liveness checking with retiming 有权
标题翻译：重新定义活动检查的逻辑设计验证技术
公开(公告)号：US08407641B2
公开(公告)日：2013-03-26
申请号：US13436196
申请日：2012-03-30
申请人： Jason R. Baumgartner , Gabor Bobok , Paul Joseph Roessler , Mark Allen Williams
发明人： Jason R. Baumgartner , Gabor Bobok , Paul Joseph Roessler , Mark Allen Williams
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031 , G06F17/504 , G06F2217/84
摘要： A technique for verification of a retimed logic design using liveness checking includes assigning a liveness gate to a liveness property for an original netlist and assigning a fairness gate to a fairness constraint for the original netlist. In this case, the fairness gate is associated with the liveness gate and is asserted for at least one time-step during any valid behavioral loop associated with the liveness gate. The original netlist is retimed, using a retiming engine, to provide a retimed netlist. The liveness and fairness gates of the retimed netlist are retimed such that a lag of the fairness gate is no greater than a lag of the liveness gate. Verification analysis is then performed on the retimed netlist. Finally, when the verification analysis yields a valid counter-example trace for the retimed netlist, a liveness violation for the original netlist is returned.
摘要翻译：用于使用活动检查验证重新定时逻辑设计的技术包括将活跃门分配给原始网表的活动属性，并将公平门分配给原始网表的公平约束。在这种情况下，公平门与活跃门相关联，并且在与活跃门相关联的任何有效行为循环期间被断言至少一个时间步长。使用重新定时引擎重新计算原始网表，以提供重新定时的网表。重新定义的网表的活跃和公平的门被重新定位，使得公平门的滞后不大于活跃门的滞后。然后在重新定时的网表上进行验证分析。最后，当验证分析为重新定时的网表产生有效的对照示例时，返回原始网表的活动违反。

7. 发明授权

US08255848B2 Logic design verification techniques for liveness checking with retiming 有权
标题翻译：重新定义活动检查的逻辑设计验证技术
公开(公告)号：US08255848B2
公开(公告)日：2012-08-28
申请号：US12394560
申请日：2009-02-27
申请人： Jason R. Baumgartner , Gabor Bobok , Paul Joseph Roessler , Mark Allen Williams
发明人： Jason R. Baumgartner , Gabor Bobok , Paul Joseph Roessler , Mark Allen Williams
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031 , G06F17/504 , G06F2217/84
摘要： A technique for verification of a retimed logic design using liveness checking includes assigning a liveness gate to a liveness property for an original netlist and assigning a fairness gate to a fairness constraint for the original netlist. In this case, the fairness gate is associated with the liveness gate and is asserted for at least one time-step during any valid behavioral loop associated with the liveness gate. The original netlist is retimed, using a retiming engine, to provide a retimed netlist. The liveness and fairness gates of the retimed netlist are retimed such that a lag of the fairness gate is no greater than a lag of the liveness gate. Verification analysis is then performed on the retimed netlist. Finally, when the verification analysis yields a valid counter-example trace for the retimed netlist, a liveness violation for the original netlist is returned.
摘要翻译：用于使用活动检查验证重新定时逻辑设计的技术包括将活跃门分配给原始网表的活动属性，并将公平门分配给原始网表的公平约束。在这种情况下，公平门与活跃门相关联，并且在与活跃门相关联的任何有效行为循环期间被断言至少一个时间步长。使用重新定时引擎重新计算原始网表，以提供重新定时的网表。重新定义的网表的活跃和公平的门被重新定位，使得公平门的滞后不大于活跃门的滞后。然后在重新定时的网表上进行验证分析。最后，当验证分析为重新定时的网表产生有效的对照示例时，返回原始网表的活动违反。

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