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1. 发明申请

US20120192133A1 LOGIC DESIGN VERIFICATION TECHNIQUES FOR LIVENESS CHECKING WITH RETIMING 有权
标题翻译：用于生活垃圾检查的LOGIC设计验证技术
公开(公告)号：US20120192133A1
公开(公告)日：2012-07-26
申请号：US13436196
申请日：2012-03-30
申请人： Jason R. Baumgartner , Gabor Bobok , Paul Joseph Roessler , Mark Allen Williams
发明人： Jason R. Baumgartner , Gabor Bobok , Paul Joseph Roessler , Mark Allen Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/504 , G06F2217/84
摘要： A technique for verification of a retimed logic design using liveness checking includes assigning a liveness gate to a liveness property for an original netlist and assigning a fairness gate to a fairness constraint for the original netlist. In this case, the fairness gate is associated with the liveness gate and is asserted for at least one time-step during any valid behavioral loop associated with the liveness gate. The original netlist is retimed, using a retiming engine, to provide a retimed netlist. The liveness and fairness gates of the retimed netlist are retimed such that a lag of the fairness gate is no greater than a lag of the liveness gate. Verification analysis is then performed on the retimed netlist. Finally, when the verification analysis yields a valid counter-example trace for the retimed netlist, a liveness violation for the original netlist is returned.
摘要翻译：用于使用活动检查验证重新定时逻辑设计的技术包括将活跃门分配给原始网表的活动属性，并将公平门分配给原始网表的公平约束。在这种情况下，公平门与活跃门相关联，并且在与活跃门相关联的任何有效行为循环期间被断言至少一个时间步长。使用重新定时引擎重新计算原始网表，以提供重新定时的网表。重新定义的网表的活跃和公平的门被重新定位，使得公平门的滞后不大于活跃门的滞后。然后在重新定时的网表上进行验证分析。最后，当验证分析为重新定时的网表产生有效的对照示例时，返回原始网表的活动违反。

2. 发明授权

US08407641B2 Logic design verification techniques for liveness checking with retiming 有权
标题翻译：重新定义活动检查的逻辑设计验证技术
公开(公告)号：US08407641B2
公开(公告)日：2013-03-26
申请号：US13436196
申请日：2012-03-30
申请人： Jason R. Baumgartner , Gabor Bobok , Paul Joseph Roessler , Mark Allen Williams
发明人： Jason R. Baumgartner , Gabor Bobok , Paul Joseph Roessler , Mark Allen Williams
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031 , G06F17/504 , G06F2217/84
摘要： A technique for verification of a retimed logic design using liveness checking includes assigning a liveness gate to a liveness property for an original netlist and assigning a fairness gate to a fairness constraint for the original netlist. In this case, the fairness gate is associated with the liveness gate and is asserted for at least one time-step during any valid behavioral loop associated with the liveness gate. The original netlist is retimed, using a retiming engine, to provide a retimed netlist. The liveness and fairness gates of the retimed netlist are retimed such that a lag of the fairness gate is no greater than a lag of the liveness gate. Verification analysis is then performed on the retimed netlist. Finally, when the verification analysis yields a valid counter-example trace for the retimed netlist, a liveness violation for the original netlist is returned.
摘要翻译：用于使用活动检查验证重新定时逻辑设计的技术包括将活跃门分配给原始网表的活动属性，并将公平门分配给原始网表的公平约束。在这种情况下，公平门与活跃门相关联，并且在与活跃门相关联的任何有效行为循环期间被断言至少一个时间步长。使用重新定时引擎重新计算原始网表，以提供重新定时的网表。重新定义的网表的活跃和公平的门被重新定位，使得公平门的滞后不大于活跃门的滞后。然后在重新定时的网表上进行验证分析。最后，当验证分析为重新定时的网表产生有效的对照示例时，返回原始网表的活动违反。

3. 发明授权

US08255848B2 Logic design verification techniques for liveness checking with retiming 有权
标题翻译：重新定义活动检查的逻辑设计验证技术
公开(公告)号：US08255848B2
公开(公告)日：2012-08-28
申请号：US12394560
申请日：2009-02-27
申请人： Jason R. Baumgartner , Gabor Bobok , Paul Joseph Roessler , Mark Allen Williams
发明人： Jason R. Baumgartner , Gabor Bobok , Paul Joseph Roessler , Mark Allen Williams
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031 , G06F17/504 , G06F2217/84
摘要： A technique for verification of a retimed logic design using liveness checking includes assigning a liveness gate to a liveness property for an original netlist and assigning a fairness gate to a fairness constraint for the original netlist. In this case, the fairness gate is associated with the liveness gate and is asserted for at least one time-step during any valid behavioral loop associated with the liveness gate. The original netlist is retimed, using a retiming engine, to provide a retimed netlist. The liveness and fairness gates of the retimed netlist are retimed such that a lag of the fairness gate is no greater than a lag of the liveness gate. Verification analysis is then performed on the retimed netlist. Finally, when the verification analysis yields a valid counter-example trace for the retimed netlist, a liveness violation for the original netlist is returned.
摘要翻译：用于使用活动检查验证重新定时逻辑设计的技术包括将活跃门分配给原始网表的活动属性，并将公平门分配给原始网表的公平约束。在这种情况下，公平门与活跃门相关联，并且在与活跃门相关联的任何有效行为循环期间被断言至少一个时间步长。使用重新定时引擎重新计算原始网表，以提供重新定时的网表。重新定义的网表的活跃和公平的门被重新定位，使得公平门的滞后不大于活跃门的滞后。然后在重新定时的网表上进行验证分析。最后，当验证分析为重新定时的网表产生有效的对照示例时，返回原始网表的活动违反。

4. 发明申请

US20100223584A1 Logic Design Verification Techniques for Liveness Checking With Retiming 有权
标题翻译：逻辑设计验证技术，用于重新定义活动检查
公开(公告)号：US20100223584A1
公开(公告)日：2010-09-02
申请号：US12394560
申请日：2009-02-27
申请人： Jason R. Baumgartner , Gabor Bobok , Paul Joseph Roessler , Mark Williams
发明人： Jason R. Baumgartner , Gabor Bobok , Paul Joseph Roessler , Mark Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/504 , G06F2217/84
摘要： A technique for verification of a retimed logic design using liveness checking includes assigning a liveness gate to a liveness property for an original netlist and assigning a fairness gate to a fairness constraint for the original netlist. In this case, the fairness gate is associated with the liveness gate and is asserted for at least one time-step during any valid behavioral loop associated with the liveness gate. The original netlist is retimed, using a retiming engine, to provide a retimed netlist. The liveness and fairness gates of the retimed netlist are retimed such that a lag of the fairness gate is no greater than a lag of the liveness gate. Verification analysis is then performed on the retimed netlist. Finally, when the verification analysis yields a valid counter-example trace for the retimed netlist, a liveness violation for the original netlist is returned.
摘要翻译：用于使用活动检查验证重新定时逻辑设计的技术包括将活跃门分配给原始网表的活动属性，并将公平门分配给原始网表的公平约束。在这种情况下，公平门与活跃门相关联，并且在与活跃门相关联的任何有效行为循环期间被断言至少一个时间步长。使用重新定时引擎重新计算原始网表，以提供重新定时的网表。重新定义的网表的活跃和公平的门被重新定位，使得公平门的滞后不大于活跃门的滞后。然后在重新定时的网表上进行验证分析。最后，当验证分析为重新定时的网表产生有效的对照示例时，返回原始网表的活动违反。

5. 发明授权

US08352894B2 Verification techniques for liveness checking of logic designs 有权
标题翻译：逻辑设计的活性检查验证技术
公开(公告)号：US08352894B2
公开(公告)日：2013-01-08
申请号：US13403799
申请日：2012-02-23
申请人： Jason R. Baumgartner , Paul Joseph Roessler , Ohad Shacham , Jiazhao Xu
发明人： Jason R. Baumgartner , Paul Joseph Roessler , Ohad Shacham , Jiazhao Xu
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A technique for verification of a logic design using a liveness-to-safety conversion includes assigning liveness gates for liveness properties of a netlist and assigning a single loop gate to provide a loop signal for the liveness gates. Assertion of the single loop gate is prevented when none of the liveness gates are asserted. A first state of the netlist is sampled and the sampled first state provides an initial state for a first behavioral loop for at least one of the liveness gates following the assertion of the single loop gate. The sampled first state of the first behavioral loop is compared with a later state of the first behavioral loop to determine if the sampled first state is repeated. A liveness violation is returned when the sampled first state is repeated and an associated one of the liveness gates remains asserted for a duration of the first behavioral loop.
摘要翻译：用于验证使用安全性转换的逻辑设计的技术包括为网表的活动属性分配活动门，并分配单个循环门以为活跃门提供循环信号。当没有活动门被断言时，防止单回路门的断言。对网表的第一状态进行采样，并且采样的第一状态为在单循环门的断言之后的活动门中的至少一个为第一行为环提供初始状态。将第一行为循环的采样的第一状态与第一行为循环的稍后状态进行比较，以确定是否重复采样的第一状态。当重复采样的第一状态并且在第一行为循环的持续时间内相关联的一个活动门保持断言时，返回活动违反。

6. 发明授权

US08589327B2 Efficiently determining boolean satisfiability with lazy constraints 失效
标题翻译：有效地确定具有延迟约束的布尔可满足性
公开(公告)号：US08589327B2
公开(公告)日：2013-11-19
申请号：US13092262
申请日：2011-04-22
申请人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
发明人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
IPC分类号： G06F17/00 , G06N5/02
CPC分类号： G06F17/504 , G06F17/11 , G06F2217/06
摘要： A mechanism is provided for efficiently determining Boolean satisfiability (SAT) using lazy constraints. A determination is made as to whether a SAT problem is satisfied without constraints in a list of constraints. Responsive to the SAT problem being satisfied without constraints, a set of variable assignments that are determined in satisfying the SAT problem without constraints are fixed. For each constraint in the list of constraints, a determination is made as to whether the SAT problem with the constraint results in the set of variable assignments remaining constant. Responsive to the SAT problem with the constraint resulting in the set of variable assignments remaining constant, the constraint is added to a list of non-affecting constraints and a satisfied result is returned.
摘要翻译：提供了一种使用延迟约束有效地确定布尔可满足性（SAT）的机制。确定SAT问题是否满足约束列表中的约束。响应于没有约束的满足SAT问题的SAT问题，在不受约束的情况下满足SAT问题确定的一组可变分配是固定的。对于约束列表中的每个约束，确定具有约束的SAT问题是否导致可变分配集合保持不变。响应于导致变量赋值集合保持不变的约束的SAT问题，约束被添加到不受影响的约束的列表，并且返回满意的结果。

7. 发明授权

US08473882B2 Method and system for scalable reduction in registers with SAT-based resubstitution 失效
标题翻译：用于基于SAT重新配置的寄存器的可缩减方法和系统
公开(公告)号：US08473882B2
公开(公告)日：2013-06-25
申请号：US13415924
申请日：2012-03-09
申请人： Jason R. Baumgartner , Michael L. Case , Hari Mony , Viresh Paruthi
发明人： Jason R. Baumgartner , Michael L. Case , Hari Mony , Viresh Paruthi
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/505
摘要： A method, system, and computer program product for reducing the size of a logic network design, prior to verification of the logic network design. The method includes eliminating registers to reduce the size of the logic network design; thereby, increasing the speed and functionality of the verification process, and decreasing the size of the logic network design. The system identifies one or more compatible resubstitutions of a selected register, wherein the compatible resubstitution expresses the selected register as one or more pre-existing registers of fixed initial state. The resubstitutions are refined utilizing design invariants. When one more resubstitutions are preformed, the system eliminates the selected registers to reduce the size of the logic network design. As a result of the resubstitution process, a logic network design of reduced size is generated.
摘要翻译：在验证逻辑网络设计之前，用于减小逻辑网络设计大小的方法，系统和计算机程序产品。该方法包括消除寄存器以减小逻辑网络设计的大小; 从而增加验证过程的速度和功能，并减小逻辑网络设计的大小。系统识别所选择的寄存器的一个或多个兼容的重新配置，其中兼容重新配置将所选择的寄存器表示为一个或多个预先存在的固定初始状态的寄存器。利用设计不变量来改进重组。当再进行一次重新配置时，系统将删除所选择的寄存器以减小逻辑网络设计的大小。作为重新配置处理的结果，生成尺寸减小的逻辑网络设计。

8. 发明授权

US08418106B2 Techniques for employing retiming and transient simplification on netlists that include memory arrays 失效
标题翻译：对包含存储器阵列的网表进行重新定时和瞬态简化的技术
公开(公告)号：US08418106B2
公开(公告)日：2013-04-09
申请号：US12872490
申请日：2010-08-31
申请人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
发明人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A technique for performing an analysis of a logic design (that includes a native memory array embodied in a netlist) includes detecting an initial transient behavior in the logic design as embodied in the netlist. The technique also includes determining a duration of the initial transient behavior and gathering reduction information on the logic design based on the initial transient behavior. The netlist is then modified based on the reduction information.
摘要翻译：用于执行对逻辑设计（包括在网表中包含的本地存储器阵列）的分析的技术包括检测在网表中体现的逻辑设计中的初始瞬态行为。该技术还包括基于初始瞬态行为来确定初始瞬态行为的持续时间并收集关于逻辑设计的减少信息。然后基于减少信息来修改网表。

9. 发明申请

US20120290992A1 LOGICAL CIRCUIT NETLIST REDUCTION AND MODEL SIMPLIFICATION USING SIMULATION RESULTS CONTAINING SYMBOLIC VALUES 失效
标题翻译：使用包含符号值的模拟结果的逻辑电路网络列表减少和模型简化
公开(公告)号：US20120290992A1
公开(公告)日：2012-11-15
申请号：US13104573
申请日：2011-05-10
申请人： Michael L. Case , Jason R. Baumgartner , Robert L. Kanzelman , Hari Mony
发明人： Michael L. Case , Jason R. Baumgartner , Robert L. Kanzelman , Hari Mony
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A logic synthesis program, method and system for simplifying and/or reducing a logic design receives output from a logic simulator that uses symbolic values for stimulus and contains symbolic values in the logic simulator output. Relationships between the nodes dependent on symbolic values can be used to merge nodes or otherwise simplify the logic design. Behaviors such as oscillators, transient values, identical signals, dependent logical states and chicken-switch determined states that depend on the symbolic values can be detected in the simulation results and the netlist simplified using the results of the detection. The netlist can be simplified by inserting registers to represent nodes that assume a symbolic value or combination based on symbolic values either statically or after an initial transient. Oscillating nodes can be replaced with equivalent oscillator circuits, and nodes having values dependent on chicken-switch operation can be detected and replaced with registers initialized from the chicken-switch input states.
摘要翻译：用于简化和/或减少逻辑设计的逻辑综合程序，方法和系统从逻辑模拟器接收输出，该逻辑模拟器使用符号值作为刺激，并在逻辑模拟器输出中包含符号值。依赖于符号值的节点之间的关系可用于合并节点或简化逻辑设计。可以在仿真结果和使用检测结果简化的网表中检测到依赖于符号值的振荡器，瞬态值，相同信号，依赖逻辑状态和鸡开关确定状态等行为。可以通过插入寄存器来简化网表，以代表以静态方式或初始瞬态之后基于符号值假设符号值或组合的节点。振荡节点可以用等效的振荡器电路代替，并且可以检测具有取决于鸡开关操作的值的节点，并用从鸡开关输入状态初始化的寄存器替换振荡节点。

10. 发明授权

US08146034B2 Efficient Redundancy Identification, Redundancy Removal, and Sequential Equivalence Checking within Designs Including Memory Arrays. 有权
标题翻译：有效的冗余识别，冗余删除和在包括内存数组的设计中的顺序等价检查。
公开(公告)号：US08146034B2
公开(公告)日：2012-03-27
申请号：US12771677
申请日：2010-04-30
申请人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
发明人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/504
摘要： A mechanism is provided for efficient redundancy identification, redundancy removal, and sequential equivalence checking with designs including memory arrays. The mechanism includes an array merging component to optimally merge an array output such that if the address is out-of-bounds or the port is not asserted, the array output is converted to a random output. The mechanism also includes a component for determining the equivalence of enabled array outputs rather than the array outputs directly and creating an enabled array output. The mechanism also includes a component that precludes potentially-redundant array cells from participating in the sequential redundancy removal determination. This component first checks for compatibility of the corresponding arrays, then the corresponding read port enables and addresses, then the corresponding initial values, and finally checking that writes to the corresponding columns yield a compatible set of values.
摘要翻译：提供了一种机制，用于有效的冗余识别，冗余删除和与包括存储器阵列的设计的顺序等同性检查。该机制包括阵列合并组件，以最佳地合并阵列输出，以便如果地址超出边界或端口未被断言，阵列输出将转换为随机输出。该机制还包括用于确定启用的阵列输出的等效性的组件，而不是直接对阵列输出进行创建并创建启用的阵列输出。该机制还包括排除潜在冗余阵列单元参与顺序冗余移除确定的组件。该组件首先检查相应阵列的兼容性，然后对应的读端口启用和地址，然后对应的初始值，最后检查对相应列的写入是否产生兼容的值集合。

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