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1. 发明授权

US06658610B1 Compilable address magnitude comparator for memory array self-testing 有权
标题翻译：可编程地址幅度比较器用于存储器阵列自检
公开(公告)号：US06658610B1
公开(公告)日：2003-12-02
申请号：US09669117
申请日：2000-09-25
申请人： Chiaming Chai , Jeffrey H. Fischer , Michael R. Ouellette , Michael H. Wood
发明人： Chiaming Chai , Jeffrey H. Fischer , Michael R. Ouellette , Michael H. Wood
IPC分类号： G11C2900
CPC分类号： G01R31/3187 , G01R31/3193 , G11C29/26 , G11C2029/1802
摘要： The present invention provides a method and apparatus that improves Built-In-Self-Test (BIST) flexibility without requiring the complexity of a compilable BIST circuit. Additionally, the present invention provides the ability to use a single BIST to test multiple memory arrays of different sizes. The preferred embodiment of the present invention provides a compilable address magnitude comparator to facilitate BIST testing of different size memory arrays without requiring customization of the BIST controller. The preferred embodiment compilable address magnitude comparator is compiled within the compilable memory arrays of the ASIC to allow a single BIST controller to test multiple sizes of memory arrays without requiring that the BIST controller itself be compilable. In the preferred embodiment, the compilable magnitude address comparator overrides the self-test signal from the BIST when the BIST attempts to test addresses that do not exist in the memory. As such, the BIST is prevented from writing to addresses that do not exist, and does not receive error signals from those addresses. Thus, the BIST controller is able to test memory arrays without regard for their particular size. Furthermore, a single BIST controller can then be used to test multiple memory arrays of different sizes in the ASIC, again reducing device complexity.
摘要翻译：本发明提供了一种改进内置自测（BIST）灵活性的方法和装置，而不需要可编译BIST电路的复杂性。此外，本发明提供了使用单个BIST来测试不同大小的多个存储器阵列的能力。本发明的优选实施例提供可编译的地址幅度比较器，以便于不需要定制BIST控制器的不同大小的存储器阵列的BIST测试。优选实施例可编译地址幅度比较器被编译在ASIC的可编译存储器阵列内，以允许单个BIST控制器测试存储器阵列的多个大小，而不需要BIST控制器本身可编译。在优选实施例中，当BIST尝试测试存储器中不存在的地址时，可编译幅度地址比较器覆盖来自BIST的自检信号。因此，BIST被阻止写入不存在的地址，并且不从这些地址接收到错误信号。因此，BIST控制器能够测试存储器阵列，而不考虑其特定大小。此外，可以使用单个BIST控制器来测试ASIC中不同大小的多个存储器阵列，从而降低器件的复杂性。

2. 发明申请

US20140040844A1 Method for Achieving An Efficient Statistical Optimization of Integrated Circuits 有权
标题翻译：实现集成电路高效统计优化的方法
公开(公告)号：US20140040844A1
公开(公告)日：2014-02-06
申请号：US13564751
申请日：2012-08-02
申请人： Chandramouli Visweswariah , Eric Fluhr , Stephen G. Shuma , Debjit Sinha , Michael H. Wood
发明人： Chandramouli Visweswariah , Eric Fluhr , Stephen G. Shuma , Debjit Sinha , Michael H. Wood
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： Method for performing timing closure of integrated circuits in the presence of manufacturing and environmental variations. The starting design is analyzed using statistical static timing analysis to determine timing violations. Each timing violation in its statistical canonical form is examined. In a first aspect of the invention, the canonical failing slack is inspected to determine what type of move is most likely to fix the timing violation taking into account all relevant manufacturing and environmental variations. In a second aspect of the invention, pre-characterized moves such as insertion of delay pad cells are evaluated for their ability to fix the timing violation without triggering timing, and the best move or set of moves is selected.
摘要翻译：在存在制造和环境变化的情况下执行集成电路的定时关闭的方法。使用统计静态时序分析来分析起始设计，以确定时序违规。检查其统计规范形式的每个时间违规。在本发明的第一方面，检查规范的故障松弛以确定哪种类型的移动最有可能在考虑到所有相关的制造和环境变化的情况下修复定时违规。在本发明的第二方面中，评估了诸如插入延迟垫单元之类的预先表征的移动能够固定定时违反而不触发定时，并且选择最佳移动或移动集合。

3. 发明授权

US06959930B2 Combination oil scrapper ring/gas seal assembly 有权
标题翻译：组合刮油环/气密封组件
公开(公告)号：US06959930B2
公开(公告)日：2005-11-01
申请号：US10438474
申请日：2003-05-15
申请人： Michael H. Wood , Ernest B. McCurdy
发明人： Michael H. Wood , Ernest B. McCurdy
IPC分类号： F16J15/26 , F16J9/12
CPC分类号： F16J15/26
摘要： A ring assembly, including a first oil scraper ring, a center oil scraper ring and a gas seal ring, adapted for disposition in a single groove of a packing cup which can be stationarily mounted over and around a reciprocally movable piston rod of a gas compressor. The function of the assembly is to both scrape lubricating oil from the piston rod for return to one side of the cup and to provide a seal against gas leakage from an opposite side of the cup, both along the piston rod under the seal ring and between the seal ring and opposing sides of the center ring and groove to prevent mixing of gas with the oil and escape of gas from the compressor. The center ring features a tapered outer peripheral surface portion. An annular side loading element, which can be a garter spring, is mounted in compression around the center ring so as to bear against the tapered surface portion and against an adjacent side of the first ring. The element thus side loads the first ring, by urging it against one side of the groove and oppositely side loads the center ring and seal ring to force one against the other and to urge the seal ring tightly against an opposite side wall of the groove to effect a satisfactory gas seal. The first ring and center ring, together, provide three separate and axially spaced apart oil scraper edges.
摘要翻译：一种环组件，包括第一刮油环，中心刮油环和气密封环，其适于配置在填料杯的单个槽中，其可以固定地安装在气体压缩机的往复运动的活塞杆上。该组件的功能是既要从活塞杆上刮去润滑油，以便返回到杯的一侧，并且提供密封件，以防止来自杯的相对侧的气体泄漏，两者沿密封圈下方的活塞杆和第二密封环和中心环和槽的相对侧，以防止气体与油的混合和气体从压缩机逸出。中心环具有锥形外周面部分。环形侧装载元件可以是一个拉杆弹簧，围绕中心环压缩安装，以抵靠锥形表面部分并抵靠第一环的相邻侧。因此，元件通过将其推向槽的一侧来加载第一环，并且相反侧装载中心环和密封环以迫使一个抵靠另一个并且将密封环紧紧地推靠在槽的相对侧壁上实现令人满意的气密封。第一环和中心环一起提供三个独立且轴向隔开的刮油边。

4. 发明授权

US5563517A Dual channel d.c. low noise measurement system and test methodology 失效
标题翻译：双通道直流低噪声测量系统和测试方法
公开(公告)号：US5563517A
公开(公告)日：1996-10-08
申请号：US442556
申请日：1995-05-16
申请人： Glenn A. Biery , Daniel M. Boyne , Kenneth P. Rodbell , Richard G. Smith , Michael H. Wood
发明人： Glenn A. Biery , Daniel M. Boyne , Kenneth P. Rodbell , Richard G. Smith , Michael H. Wood
IPC分类号： G01R31/26 , G01R29/26 , H01L21/66
CPC分类号： G01R29/26
摘要： A test system having an improved physical layout and electrical design allows the 1/f noise of metal interconnects to be measured at levels close to that of Johnson or thermal noise. A detailed description of examples of operation of the test system provides evidence of the effectiveness of the test system in minimizing system noise to a level significantly lower than Johnson noise. This permits quantitative measurment of the noise contribution attributable to variations in cross-sectional area of connections for various applications and for qualitative prediction of electromigration lifetimes of metal films, particularly aluminum, having different microstructures. The test system includes an enclosure which includes several nested groups of housings including a sample oven within a device under test box which is, in turn, contained within the system enclosure. Wire wound resistors powered by a DC power supply are used to provide heating without interfering with measurement of 1/f noise of a device under test (D.U.T.). A biasing circuit and a bank of batteries are also provided with separate enclosures within the system enclosure.
摘要翻译：具有改进的物理布局和电气设计的测试系统允许以接近Johnson或热噪声的水平测量金属互连的1 / f噪声。测试系统操作示例的详细描述提供了测试系统在将系统噪声降至明显低于约翰逊噪声水平的有效性的证据。这允许由于各种应用的连接的横截面积的变化以及用于定性预测具有不同微结构的金属膜，特别是铝的电迁移寿命的噪声贡献的定量测量。该测试系统包括一个外壳，该外壳包括若干嵌套的外壳组，其中包括在被测箱的设备内的样品烘箱，该烘箱也被包含在系统外壳内。由直流电源供电的绕线电阻器用于提供加热，而不会干扰被测器件（D.U.T.）的1 / f噪声的测量。偏置电路和电池组还在系统外壳内设置有单独的外壳。

5. 发明授权

US08732642B2 Method for achieving an efficient statistical optimization of integrated circuits 有权
标题翻译：实现集成电路有效统计优化的方法
公开(公告)号：US08732642B2
公开(公告)日：2014-05-20
申请号：US13564751
申请日：2012-08-02
申请人： Chandramouli Visweswariah , Eric Fluhr , Stephen G. Shuma , Debjit Sinha , Michael H. Wood
发明人： Chandramouli Visweswariah , Eric Fluhr , Stephen G. Shuma , Debjit Sinha , Michael H. Wood
IPC分类号： G06F9/455
CPC分类号： G06F17/5031
摘要： Method for performing timing closure of integrated circuits in the presence of manufacturing and environmental variations. The starting design is analyzed using statistical static timing analysis to determine timing violations. Each timing violation in its statistical canonical form is examined. In a first aspect of the invention, the canonical failing slack is inspected to determine what type of move is most likely to fix the timing violation taking into account all relevant manufacturing and environmental variations. In a second aspect of the invention, pre-characterized moves such as insertion of delay pad cells are evaluated for their ability to fix the timing violation without triggering timing, and the best move or set of moves is selected.
摘要翻译：在存在制造和环境变化的情况下执行集成电路的定时关闭的方法。使用统计静态时序分析来分析起始设计，以确定时序违规。检查其统计规范形式的每个时间违规。在本发明的第一方面，检查规范的故障松弛以确定哪种类型的移动最有可能在考虑到所有相关的制造和环境变化的情况下修复定时违规。在本发明的第二方面中，评估了诸如插入延迟垫单元之类的预先表征的移动能够固定定时违反而不触发定时，并且选择最佳移动或移动集合。

6. 发明授权

US08468306B2 Microprocessor and method for deferred store data forwarding for store background data in a system with no memory model restrictions 有权
标题翻译：用于在没有内存模式限制的系统中存储后台数据的延迟存储数据转发的微处理器和方法
公开(公告)号：US08468306B2
公开(公告)日：2013-06-18
申请号：US12031858
申请日：2008-02-15
申请人： Aaron Tsai , Barry W. Krumm , James R. Mitchell , Bradley Nelson , Brian D. Barrick , Chung-Lung Kevin Shum , Michael H. Wood
发明人： Aaron Tsai , Barry W. Krumm , James R. Mitchell , Bradley Nelson , Brian D. Barrick , Chung-Lung Kevin Shum , Michael H. Wood
IPC分类号： G06F9/38
CPC分类号： G06F12/0804 , G06F9/30043
摘要： A pipelined processor includes circuitry adapted for store forwarding, including: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one block of data; merging store data from the store request with the block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated block of data into a store data queue; for each additional store request, where the additional store request requires at least one updated block of data: determining if store forwarding is appropriate for the additional store request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the additional store request.
摘要翻译：流水线处理器包括适于商店转发的电路，包括：对于每个存储请求，以及在对高速缓存和存储器中的一个进行写入待处理的情况下; 获取至少一个数据块的最新值; 将来自存储请求的存储数据与数据块合并，从而更新数据块并形成新的最新值和更新的完整数据块; 以及将更新的数据块缓冲到存储数据队列中; 对于每个额外的存储请求，其中附加存储请求需要至少一个更新的数据块：确定存储转发是否适合逐块的附加存储请求; 如果存储转发是适当的，则在逐块的基础上从存储数据队列中选择适当的数据块; 以及将所选择的数据块转发到附加存储请求。

7. 发明申请

US20110066996A1 SCHEMATIC WIRE ANNOTATION TOOL 失效
标题翻译：立体电报工具
公开(公告)号：US20110066996A1
公开(公告)日：2011-03-17
申请号：US12557855
申请日：2009-09-11
申请人： Kutalmis Koyuncu , David Webber , Michael H. Wood
发明人： Kutalmis Koyuncu , David Webber , Michael H. Wood
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method of automating circuit design is provided and includes storing one or more circuit design schematics in a memory, providing, by way of an interface, a plurality of search parameters for searching for nets of the schematics in the memory, searching for nets of the schematics in the memory in accordance with search parameters input into the interface and presenting, by way of the interface, information associated with a net matching the received search parameters.
摘要翻译：提供一种自动化电路设计的方法，包括将一个或多个电路设计原理图存储在存储器中，通过接口提供用于搜索存储器中的原理图网络的多个搜索参数，搜索存储器的网络存储器中的原理图根据搜索参数输入到接口中并通过接口呈现与网络相关联的信息匹配接收到的搜索参数。

8. 发明申请

US20090210679A1 PROCESSOR AND METHOD FOR STORE DATA FORWARDING IN A SYSTEM WITH NO MEMORY MODEL RESTRICTIONS 有权
标题翻译：在没有记忆模型限制的系统中存储数据转发的处理器和方法
公开(公告)号：US20090210679A1
公开(公告)日：2009-08-20
申请号：US12031898
申请日：2008-02-15
申请人： Aaron Tsai , Barry W. Krumm , James R. Mitchell , Bradley Nelson , Brian D. Barrick , Chung-Lung Kevin Shum , Michael H. Wood
发明人： Aaron Tsai , Barry W. Krumm , James R. Mitchell , Bradley Nelson , Brian D. Barrick , Chung-Lung Kevin Shum , Michael H. Wood
IPC分类号： G06F9/38
CPC分类号： G06F12/0855 , G06F9/3826 , G06F9/3834
摘要： A pipelined microprocessor includes circuitry for store forwarding by performing: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one complete block of data; merging store data from the store request with the complete block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated complete block of data into a store data queue; for each load request, where the load request may require at least one updated completed block of data: determining if store forwarding is appropriate for the load request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the load request.
摘要翻译：流水线微处理器包括用于存储转发的电路，通过执行以下操作：对于每个存储请求以及对高速缓存和存储器之一的写入待处理; 获取至少一个完整数据块的最新值; 将存储请求的存储数据与完整的数据块合并，从而更新数据块并形成新的最新值和更新的完整数据块; 以及将更新的完整数据块缓冲到存储数据队列中; 对于每个加载请求，其中所述加载请求可能需要至少一个更新的完成的数据块：确定在逐块的基础上存储转发是否适合于所述加载请求; 如果存储转发是适当的，则在逐块的基础上从存储数据队列中选择适当的数据块; 并将所选择的数据块转发到加载请求。

9. 发明申请

US20090064081A1 Process for Managing Complex Pre-Wired Net Segments in a VLSI Design 有权
标题翻译：在VLSI设计中管理复杂的预先有线网段的过程
公开(公告)号：US20090064081A1
公开(公告)日：2009-03-05
申请号：US11846577
申请日：2007-08-29
申请人： Christopher J. Berry , Michael A. Bowen , Michael R. Scheuermann , Michael H. Wood
发明人： Christopher J. Berry , Michael A. Bowen , Michael R. Scheuermann , Michael H. Wood
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method for pre-wiring through multiple levels of metal using flues includes steps of: receiving information comprising flue geometries and flue properties; producing multiple routing patterns of a design for the flues; identifying macro instance terminals to be pre-wired in the design; selecting at least one of the routing patterns for the macro instance terminals in the design to avoid blockage; and instantiating the design such that the flues can be manipulated as vias.
摘要翻译：使用烟道预先接线多层金属的方法包括以下步骤：接收包括烟道几何形状和烟道特性的信息; 生成针对流感的设计的多个路由模式; 识别要在设计中预先布线的宏实例终端; 在设计中选择用于宏实例终端的路由模式中的至少一个以避免阻塞; 并实例化设计，使得烟道可以被操纵为过孔。

10. 发明授权

US07073112B2 Compilable address magnitude comparator for memory array self-testing 失效
标题翻译：可编程地址幅度比较器用于存储器阵列自检
公开(公告)号：US07073112B2
公开(公告)日：2006-07-04
申请号：US10681856
申请日：2003-10-08
申请人： Chiaming Chai , Jeffrey H. Fischer , Michael R. Ouellette , Michael H. Wood
发明人： Chiaming Chai , Jeffrey H. Fischer , Michael R. Ouellette , Michael H. Wood
IPC分类号： G01R31/28
CPC分类号： G01R31/3187 , G01R31/3193 , G11C29/26 , G11C2029/1802
摘要： An apparatus that improves Built-In-Self-Test (BIST) flexibility. A compilable address magnitude comparator facilitates BIST testing of different size memory arrays without requiring customization of the BIST controller. The compilable address magnitude comparator is compiled within the compilable memory arrays of the ASIC to allow a single BIST controller to test multiple sizes of memory arrays without requiring that the BIST controller be compilable. The compilable magnitude address comparator overrides the self-test signal from the BIST when the BIST attempts to test addresses not existing in the memory. The BIST is prevented from writing to addresses that do not exist, and does not receive error signals from those addresses. The BIST controller is able to test memory arrays without regard for their particular size. A single BIST controller can be used to test multiple memory arrays of different sizes in the ASIC, reducing device complexity.
摘要翻译：一种改进内置自检（BIST）灵活性的设备。可编译的地址幅度比较器便于对不同大小的存储器阵列进行BIST测试，而无需定制BIST控制器。可编译地址幅度比较器在ASIC的可编译存储器阵列中编译，以允许单个BIST控制器测试多个大小的存储器阵列，而不需要BIST控制器可编译。当BIST尝试测试存储器中不存在的地址时，可编译幅度地址比较器会覆盖BIST的自检信号。 BIST被阻止写入不存在的地址，并且不会从这些地址接收到错误信号。 BIST控制器能够测试存储器阵列，而不考虑其特定大小。单个BIST控制器可用于在ASIC中测试不同大小的多个存储器阵列，从而降低器件的复杂性。

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