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1. 发明授权

US09443583B2 Resistive memory and method 有权
标题翻译：电阻记忆和方法
公开(公告)号：US09443583B2
公开(公告)日：2016-09-13
申请号：US13270592
申请日：2011-10-11
申请人： Christian Pacha , Tim Schönauer , Michael Kund
发明人： Christian Pacha , Tim Schönauer , Michael Kund
IPC分类号： G11C19/08 , G11C13/00 , H01L27/24 , H01L45/00 , H01L29/78
CPC分类号： G11C13/0011 , G11C13/0004 , G11C13/0007 , G11C2213/32 , H01L27/2436 , H01L29/785 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1273 , H01L45/145
摘要： A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area.
摘要翻译：存储器件包括具有接触区域的翅片的多栅极场效应晶体管（MuGFET）。可编程存储元件邻接鳍片接触区域。

2. 发明授权

US07561460B2 Resistive memory arrangement 有权
标题翻译：电阻记忆布置
公开(公告)号：US07561460B2
公开(公告)日：2009-07-14
申请号：US11688556
申请日：2007-03-20
申请人： Corvin Liaw , Thomas Roehr , Michael Kund
发明人： Corvin Liaw , Thomas Roehr , Michael Kund
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0011 , G11C2213/78 , G11C2213/79
摘要： Provided is a resistive memory arrangement having a cell array structured in rows and columns and having resistive memory cells connected to a drive element for driving. Each drive element is jointly connected to n cell resistors forming a memory cell, the cell resistors being CBRAM resistance elements, in particular, and also to a writing, reading and erasing method for a resistive memory arrangement realized with CBRAM resistance elements.
摘要翻译：提供了具有以行和列构成的单元阵列并且具有连接到用于驱动的驱动元件的电阻性存储单元的电阻式存储器装置。每个驱动元件共同连接到形成存储单元的n个单元电阻器，单元电阻器是CBRAM电阻元件，特别是与CBRAM电阻元件实现的用于电阻存储器布置的写入，读取和擦除方法。

3. 发明授权

US07457145B2 Write/delete process for resistive switching memory components 有权
标题翻译：电阻式开关存储器组件的写/删除过程
公开(公告)号：US07457145B2
公开(公告)日：2008-11-25
申请号：US11092969
申请日：2005-03-30
申请人： Michael Kund , Thomas Happ
发明人： Michael Kund , Thomas Happ
IPC分类号： G11C11/00
CPC分类号： G11C13/0011 , G11C13/0004 , G11C13/0064 , G11C13/0069
摘要： The invention relates to a system, a memory component and a process for operating a memory cell, which includes an active material, which can be changed into a more or less conductive state by an appropriate switching process, whereby the process including (a) bringing the memory cell into the more or less conductive state and evaluating the state of the memory cell after it has been changed into the more or less conductive state.
摘要翻译：本发明涉及一种用于操作存储器单元的系统，存储器组件和用于操作存储单元的过程，其包括活性材料，其可以通过适当的切换过程改变为或多或少的导电状态，由此该过程包括（a）带来存储器单元进入或多或少的导电状态，并且在将存储单元改变为或多或少的导电状态之后评估存储单元的状态。

4. 发明申请

US20080259676A1 Integrated Circuit, Memory Module, Method of Operating an Integrated Circuit, Method of Manufacturing an Integrated Circuit, and Computer Program Product 审中-公开
标题翻译：集成电路，存储器模块，集成电路的操作方法，制造集成电路的方法和计算机程序产品
公开(公告)号：US20080259676A1
公开(公告)日：2008-10-23
申请号：US11736439
申请日：2007-04-17
申请人： Bernhard Ruf , Michael Kund , Heinz Hoenigschmid
发明人： Bernhard Ruf , Michael Kund , Heinz Hoenigschmid
IPC分类号： G11C11/34 , G11C11/56 , H01L29/66
CPC分类号： G11C13/0011 , B82Y10/00 , G11C11/5614 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C29/50 , G11C2013/0083 , G11C2213/32 , G11C2213/71 , G11C2213/79
摘要： According to one embodiment of the present invention, an integrated circuit is provided which includes a plurality of resistivity changing cells. At least two resistance ranges are assigned to each resistivity changing cell, each resistance range defining a possible state of the resistivity changing cell. The integrated circuit is operable in a cell initializing mode in which initializing signals are applied to the resistivity changing cells. The strengths and durations of the initializing signals are chosen such that the resistance of each resistivity changing cell is shifted into one of the resistance ranges assigned to the resistivity changing cell.
摘要翻译：根据本发明的一个实施例，提供一种集成电路，其包括多个电阻率变化单元。至少两个电阻范围被分配给每个电阻率变化单元，每个电阻范围限定电阻率变化单元的可能状态。集成电路可以在将初始化信号施加到电阻率变化单元的单元初始化模式中操作。选择初始化信号的强度和持续时间，使得每个电阻率变化单元的电阻被转移到分配给电阻率变化单元的电阻范围之一。

5. 发明授权

US07436694B2 Nonvolatile memory cell 失效
标题翻译：非易失性存储单元
公开(公告)号：US07436694B2
公开(公告)日：2008-10-14
申请号：US11444295
申请日：2006-05-31
申请人： Joerg Berthold , Dieter Draxelmayr , Winfried Kamp , Michael Kund , Tim Schoenauer
发明人： Joerg Berthold , Dieter Draxelmayr , Winfried Kamp , Michael Kund , Tim Schoenauer
IPC分类号： G11C11/00
CPC分类号： G11C13/0011 , G11C13/0004 , G11C14/009
摘要： Nonvolatile memory cell, having a first resistor that is electrically programmable in a nonvolatile fashion, a second resistor that is electrically programmable in a nonvolatile fashion, a first leakage current reducing element connected between the first resistor and an operating potential, and a second leakage current reducing element connected between the second resistor and the operating potential.
摘要翻译：具有以非易失性方式电可编程的第一电阻器的非易失性存储器单元，以非易失性方式电可编程的第二电阻器，连接在第一电阻器和工作电位之间的第一漏电流减少元件和第二漏电流连接在第二电阻和工作电位之间的减少元件。

6. 发明申请

US20070053224A1 Method and device for programming CBRAM memory cells 失效
标题翻译：用于编程CBRAM存储单元的方法和设备
公开(公告)号：US20070053224A1
公开(公告)日：2007-03-08
申请号：US11515421
申请日：2006-09-05
申请人： Thomas Happ , Michael Kund
发明人： Thomas Happ , Michael Kund
IPC分类号： G11C16/04
CPC分类号： G11C13/0011 , G11C13/0069 , G11C16/3495
摘要： Methods and devices for programming conductive bridging RAM (CBRAM) memory cells improve the cycle stability by ensuring that the memory cells are erased before being written to anew. Optionally, in the event of overwriting the memory cells, memory cells may be written to only when the writing operation would alter the cell content (i.e., the state of bit stored in the memory cell is being changed from a logical 0 to a logical 1 or vice versa).
摘要翻译：用于编程导电桥接RAM（CBRAM）存储单元的方法和设备通过确保在重新写入之前擦除存储单元来提高周期稳定性。可选地，在重写存储器单元的情况下，仅当写入操作将改变单元内容时（即，存储在存储单元中的位的状态正在从逻辑0改变为逻辑1 或相反亦然）。

7. 发明申请

US20070008863A1 Memory comprising a memory device and a write unit configured as a probe 审中-公开
标题翻译：存储器，包括配置为探针的存储器件和写入单元
公开(公告)号：US20070008863A1
公开(公告)日：2007-01-11
申请号：US11176740
申请日：2005-07-07
申请人： Corvin Liaw , Michael Kund , Gerhard Mueller
发明人： Corvin Liaw , Michael Kund , Gerhard Mueller
IPC分类号： G11B9/00
CPC分类号： G11B9/04 , B82Y10/00 , G11B9/1427 , G11B9/149
摘要： Embodiments of the present invention provide a method and memory device for storing and reading data. In one embodiment, the probe is positioned proximate to an area of a solid electrolyte layer in which the data is to be stored. A voltage difference is created across the solid electrolyte layer by applying a first voltage to a first side of the solid electrolyte layer via a tip of the probe and applying a second voltage to a second side of the solid electrolyte layer via an electrode layer coupled to the solid electrolyte layer. The voltage difference applied across the solid electrolyte layer causes ions from the electrode layer to be introduced into the solid electrolyte layer, creating a lowered resistance in the solid electrolyte layer. The lowered resistance corresponds to a first logical value stored in the solid electrolyte layer.
摘要翻译：本发明的实施例提供一种用于存储和读取数据的方法和存储装置。在一个实施例中，探针位于其中要存储数据的固体电解质层的区域附近。通过经由探针的尖端向固体电解质层的第一侧施加第一电压，并通过耦合到固体电解质层的电极层向固体电解质层的第二侧施加第二电压，在固体电解质层上形成电压差固体电解质层。施加在固体电解质层两端的电压差使得来自电极层的离子被引入到固体电解质层中，导致固体电解质层中的电阻降低。降低的电阻对应于存储在固体电解质层中的第一逻辑值。

8. 发明申请

US20060050547A1 Resistive memory arrangement 有权
公开(公告)号：US20060050547A1
公开(公告)日：2006-03-09
申请号：US11215443
申请日：2005-08-30
申请人： Corvin Liaw , Thomas Roehr , Michael Kund
发明人： Corvin Liaw , Thomas Roehr , Michael Kund
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0011 , G11C2213/78 , G11C2213/79
摘要： Provided is a resistive memory arrangement having a cell array structured in rows and columns and having resistive memory cells connected to a drive element for driving. Each drive element is jointly connected to n cell resistors forming a memory cell, the cell resistors being CBRAM resistance elements, in particular, and also to a writing, reading and erasing method for a resistive memory arrangement realized with CBRAM resistance elements.

9. 发明授权

US06661694B2 Configuration and method for increasing the retention time and the storage security in a ferroelectric or ferromagnetic semiconductor memory 有权
公开(公告)号：US06661694B2
公开(公告)日：2003-12-09
申请号：US10000691
申请日：2001-11-15
申请人： Michael Kund , Reinhard Salchner
发明人： Michael Kund , Reinhard Salchner
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A configuration and a method for increasing the retention time and the storage security in a ferroelectric or ferromagnetic semiconductor memory utilize the imprint effect for increasing the remanent polarization or remanent magnetization of a material having a hysteresis property. The remanent polarization or magnetization is increased by writing a memory content a number of times to the same memory cells.

10. 发明授权

US07751163B2 Electric device protection circuit and method for protecting an electric device 失效
标题翻译：电气设备保护电路及其保护方法
公开(公告)号：US07751163B2
公开(公告)日：2010-07-06
申请号：US11541402
申请日：2006-09-29
申请人： Alexander Duch , Ulrich Klostermann , Michael Kund
发明人： Alexander Duch , Ulrich Klostermann , Michael Kund
IPC分类号： H02H9/00
CPC分类号： H02H9/046 , G11C13/0011 , G11C13/0038 , G11C13/0059 , H02H9/02
摘要： An electric device protection circuit comprises at least one conductive bridging unit which electrically connects a terminal of the electric device to a protection node set to a protection potential, the protection potential being chosen such that the conductive bridging unit switches from a resistive state to a conductive state in case that the voltage or current at the terminal exceeds a predetermined threshold value.
摘要翻译：电气设备保护电路包括至少一个导电桥接单元，其将电气设备的端子与设置为保护电位的保护节点电连接，所述保护电位被选择为使得导电桥接单元从电阻状态切换到导电在端子处的电压或电流超过预定阈值的情况下状态。

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