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1. 发明授权

US08595449B2 Memory scheduler for managing maintenance operations in a resistive memory in response to a trigger condition 有权
标题翻译：用于响应于触发条件来管理电阻性存储器中的维护操作的存储器调度器
公开(公告)号：US08595449B2
公开(公告)日：2013-11-26
申请号：US12202581
申请日：2008-09-02
申请人： Michael Kund , Thomas Happ , GillYong Lee , Heinz Hoenigschmid , Rolf Weis , Christoph Ludwig
发明人： Michael Kund , Thomas Happ , GillYong Lee , Heinz Hoenigschmid , Rolf Weis , Christoph Ludwig
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G11C13/00 , G11C11/00 , G11C11/34 , G11C16/06 , G11C16/04 , G11C7/04
CPC分类号： G11C7/04 , G11C13/0002 , G11C13/0033 , G11C16/3431
摘要： An integrated circuit includes: a resistive memory having an array of resistive memory cells; a memory controller that controls operation of the resistive memory in accordance with external commands from an external device; and a memory scheduler coupled to the resistive memory and to the memory controller. The memory scheduler schedules internal maintenance operations within the resistive memory in response to trigger conditions indicated by at least one sensor signal or external command. The operation of the memory scheduler and performance of the internal maintenance operations are transparent to the external device and, optionally, transparent to the memory controller.
摘要翻译：集成电路包括：具有电阻存储器单元阵列的电阻性存储器; 存储器控制器，其根据来自外部设备的外部命令来控制所述电阻性存储器的操作; 以及耦合到电阻存储器和存储器控制器的存储器调度器。存储器调度器响应于由至少一个传感器信号或外部命令指示的触发条件来调度电阻性存储器内的内部维护操作。内存调度器的操作和内部维护操作的性能对于外部设备是透明的，并且可选地对存储器控制器是透明的。

2. 发明申请

US20070171698A1 Memory circuit including a resistive memory element and method for operating such a memory circuit 有权
标题翻译：包括电阻式存储器元件的存储器电路和用于操作这种存储器电路的方法
公开(公告)号：US20070171698A1
公开(公告)日：2007-07-26
申请号：US11318345
申请日：2005-12-23
申请人： Heinz Hoenigschmid , Milena Dimitrova , Corvin Liaw , Michael Angerbauer
发明人： Heinz Hoenigschmid , Milena Dimitrova , Corvin Liaw , Michael Angerbauer
IPC分类号： G11C11/00
CPC分类号： G11C13/0011 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/0078 , G11C2013/009 , G11C2213/79
摘要： The present invention relates to a memory circuit and method of operating the same. In at least one embodiment, the memory circuit includes a resistive memory element coupled to a plate potential by a first terminal; a bit line which is connectable to a second terminal of the resistive memory element; a programming circuit operable to change the resistance of the resistive memory element; a bleeder circuit operable to provide a bleeding current to or from the bit line due to a change of the resistance of the resistive memory element caused by the programming circuit.
摘要翻译：本发明涉及一种存储电路及其操作方法。在至少一个实施例中，存储器电路包括由第一端子耦合到板电位的电阻性存储器元件; 可连接到电阻式存储器元件的第二端子的位线; 编程电路，其可操作以改变所述电阻式存储元件的电阻; 泄放电路可操作以由于由编程电路引起的电阻性存储元件的电阻的变化而向位线或从位线提供出流电流。

3. 发明授权

US06426907B1 Reference for MRAM cell 有权
标题翻译： MRAM细胞参考
公开(公告)号：US06426907B1
公开(公告)日：2002-07-30
申请号：US09836817
申请日：2001-04-17
申请人： Heinz Hoenigschmid
发明人： Heinz Hoenigschmid
IPC分类号： G11C700
CPC分类号： G11C11/15
摘要： A reference circuit (132) for an MRAM array, including logic “1” reference MRAM cells (MR1a) and (MR1b) coupled in parallel with logic “0” reference MRAM cells (MR0a) and (MR0b) The reference current (Iref)is coupled to a measurement resistor (Rm4) of a sense amplifier (130) which is adapted to determine the logic state of an unknown memory cell MCu.
摘要翻译：用于MRAM阵列的参考电路（132）包括与逻辑“0”参考MRAM单元（MR0a）和（MR0b）并联耦合的逻辑“1”参考MRAM单元（MR1a）和（MR1b）。参考电流（Iref）耦合到读出放大器（130）的测量电阻器（Rm4），其适于确定未知存储器单元MCu的逻辑状态。

4. 发明授权

US5821592A Dynamic random access memory arrays and methods therefor 失效
标题翻译：动态随机存取存储器阵列及其方法
公开(公告)号：US5821592A
公开(公告)日：1998-10-13
申请号：US884853
申请日：1997-06-30
申请人： Heinz Hoenigschmid , John DeBrosse
发明人： Heinz Hoenigschmid , John DeBrosse
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/68
CPC分类号： H01L27/10805 , H01L27/10882 , Y10S257/905 , Y10S257/907
摘要： A dynamic random access memory array having an array of memory cells. Individual cells of the array are addressable by a plurality of word lines and a plurality of bit lines. The memory cells are disposed in active areas of the array. The array of memory cells includes a first strip of memory cells. The dynamic random access memory array includes a lower metal layer and an upper metal layer disposed above the lower metal layer. The dynamic random access memory array further includes a dielectric layer disposed between the lower metal layer and the upper metal layer. There is further included a first bit line of the plurality of bit lines which includes a lower metal first bit line portion implemented in the lower metal layer. The lower metal first bit line portion is coupled to a first plurality of memory cells of the first strip of memory cells. The first bit line also includes an upper metal first bit line portion implemented in the upper metal layer. The upper metal first bit line portion is coupled to the lower first metal bit line portion by a first contact through the dielectric layer. The first contact is disposed above one of the active areas.
摘要翻译：一种具有存储器单元阵列的动态随机存取存储器阵列。该阵列的单个单元可由多个字线和多个位线寻址。存储单元被布置在阵列的有效区域中。存储单元的阵列包括第一条存储单元。动态随机存取存储器阵列包括下金属层和设置在下金属层上方的上金属层。动态随机存取存储器阵列还包括设置在下金属层和上金属层之间的电介质层。还包括多个位线的第一位线，其包括实现在下金属层中的下金属第一位线部分。下金属第一位线部分耦合到第一条存储器单元的第一多个存储单元。第一位线还包括实现在上金属层中的上金属第一位线部分。上金属第一位线部分通过介电层的第一接触耦合到下部第一金属位线部分。第一触点设置在有效区域之上。

5. 发明授权

US07869253B2 Method of determining a memory state of a resistive memory cell and device measuring the memory state of a resistive memory cell 有权
标题翻译：确定电阻性存储单元的存储状态的方法和测量电阻存储单元的存储状态的装置
公开(公告)号：US07869253B2
公开(公告)日：2011-01-11
申请号：US11507362
申请日：2006-08-21
申请人： Corvin Liaw , Michael Angerbauer , Heinz Hoenigschmid
发明人： Corvin Liaw , Michael Angerbauer , Heinz Hoenigschmid
IPC分类号： G11C11/00 , G11C11/14
CPC分类号： G11C11/16 , B82Y10/00 , G11C11/5614 , G11C11/5664 , G11C11/5678 , G11C13/0004 , G11C13/0011 , G11C13/0014 , G11C13/004 , G11C13/0061 , G11C2013/0054
摘要： A method of determining the memory state of a resistive memory cell including a first electrode, a second electrode and an active material being arranged between the first electrode and the second electrode, comprises generating a read capacity by applying a voltage between the first electrode and the second electrode, discharging the read capacity over the active material of the memory cell, and determining the memory state of the memory cell in dependence on a change of the voltage during the discharge of the read capacity.
摘要翻译：确定包括布置在第一电极和第二电极之间的第一电极，第二电极和活性材料的电阻式存储单元的存储状态的方法包括通过在第一电极和第二电极之间施加电压来产生读取容量第二电极，通过存储单元的活性材料放电读取容量，以及根据读出容量放电期间电压的变化来确定存储单元的存储状态。

6. 发明授权

US07848134B2 FB DRAM memory with state memory 有权
标题翻译： FB DRAM内存带状态存储器
公开(公告)号：US07848134B2
公开(公告)日：2010-12-07
申请号：US12178407
申请日：2008-07-23
申请人： Milena Ivanov , Heinz Hoenigschmid , Stefan Dietrich , Michael Markert
发明人： Milena Ivanov , Heinz Hoenigschmid , Stefan Dietrich , Michael Markert
IPC分类号： G11C11/24
CPC分类号： G11C11/4091 , G11C11/404 , G11C2211/4016
摘要： A memory chip with a plurality of FB DRAM cells, having a word line coupled to a first FB DRAM cell and a second FB DRAM cell is disclosed. The memory chip further has a first bit line coupled to the first FB DRAM cell, and a first state memory circuit coupled to the first bit line. The memory chip further includes a second bit line coupled to the second FB DRAM cell, and a second state memory circuit coupled to the second bit line. The memory chip further includes a sense amplifier, which can be coupled to the first FB DRAM cell, the second FB DRAM cell, the first state memory circuit or the second state memory circuit.
摘要翻译：公开了具有耦合到第一FB DRAM单元和第二FB DRAM单元的字线的具有多个FB DRAM单元的存储器芯片。存储器芯片还具有耦合到第一FB DRAM单元的第一位线和耦合到第一位线的第一状态存储器电路。存储器芯片还包括耦合到第二FB DRAM单元的第二位线和耦合到第二位线的第二状态存储器电路。存储器芯片还包括读出放大器，其可耦合到第一FB DRAM单元，第二FB DRAM单元，第一状态存储器电路或第二状态存储器电路。

7. 发明授权

US07599209B2 Memory circuit including a resistive memory element and method for operating such a memory circuit 有权
标题翻译：包括电阻式存储器元件的存储器电路和用于操作这种存储器电路的方法
公开(公告)号：US07599209B2
公开(公告)日：2009-10-06
申请号：US11318345
申请日：2005-12-23
申请人： Heinz Hoenigschmid , Milena Dimitrova , Corvin Liaw , Michael Angerbauer
发明人： Heinz Hoenigschmid , Milena Dimitrova , Corvin Liaw , Michael Angerbauer
IPC分类号： G11C11/00
CPC分类号： G11C13/0011 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/0078 , G11C2013/009 , G11C2213/79
摘要： The present invention relates to a memory circuit and method of operating the same. In at least one embodiment, the memory circuit includes a resistive memory element coupled to a plate potential by a first terminal; a bit line which is connectable to a second terminal of the resistive memory element; a programming circuit operable to change the resistance of the resistive memory element; a bleeder circuit operable to provide a bleeding current to or from the bit line due to a change of the resistance of the resistive memory element caused by the programming circuit.
摘要翻译：本发明涉及一种存储电路及其操作方法。在至少一个实施例中，存储器电路包括由第一端子耦合到板电位的电阻性存储器元件; 可连接到电阻式存储器元件的第二端子的位线; 编程电路，其可操作以改变所述电阻式存储元件的电阻; 泄放电路可操作以由于由编程电路引起的电阻性存储元件的电阻的变化而向位线或从位线提供出流电流。

8. 发明申请

US20080192529A1 INTEGRATED CIRCUIT HAVING A RESISTIVE MEMORY 审中-公开
标题翻译：具有电阻记忆体的集成电路
公开(公告)号：US20080192529A1
公开(公告)日：2008-08-14
申请号：US11673111
申请日：2007-02-09
申请人： Heinz HOENIGSCHMID , Stefan DIETRICH , Milena DIMITROVA , Michael MARKERT
发明人： Heinz HOENIGSCHMID , Stefan DIETRICH , Milena DIMITROVA , Michael MARKERT
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0011 , G11C13/003 , G11C13/0069 , G11C2013/009 , G11C2213/79
摘要： An integrated circuit having a resistive memory including a resistive memory element, a selection device, a conductive line, and a reference electrode is disclosed. In one embodiment, the conductive line is set to a first voltage for establishing a first resistive state of the resistive memory element and to a second voltage, being lower than the first voltage, for establishing a second resistive state of the resistive memory element. The reference electrode is coupled to the resistive memory element and is set to a voltage level being provided between the first voltage and the second voltage.
摘要翻译：公开了一种具有电阻性存储器的集成电路，该电阻存储器包括电阻性存储元件，选择器件，导线和参考电极。在一个实施例中，为了建立电阻式存储器元件的第二电阻状态，将导线设置为第一电压以建立电阻性存储元件的第一电阻状态和低于第一电压的第二电压。参考电极耦合到电阻性存储元件，并被设置为在第一电压和第二电压之间提供的电压电平。

9. 发明授权

US06624461B1 Memory device 有权
标题翻译：内存设备
公开(公告)号：US06624461B1
公开(公告)日：2003-09-23
申请号：US10089910
申请日：2002-06-27
申请人： Heinz Hoenigschmid , Georg Braun
发明人： Heinz Hoenigschmid , Georg Braun
IPC分类号： H01L27108
CPC分类号： H01L27/10885 , G11C5/10 , H01L27/10811 , H01L27/10814
摘要： The invention relates to a memory device comprising numerous memory cells, each cell comprising at least one selection transistor and one stacked capacitor and driven via word and bit lines. This memory device comprises two metallized sheets through which the bit line is led and between which the memory cell stacked capacitor is arranged.
摘要翻译：本发明涉及包括多个存储器单元的存储器件，每个单元包括至少一个选择晶体管和一个堆叠电容器，并通过字和位线驱动。该存储器件包括两个金属化片，位线被引导通过该金属化片，布置有存储单元堆叠电容器之间。

10. 发明授权

US06567300B1 Narrow contact design for magnetic random access memory (MRAM) arrays 失效
标题翻译：磁性随机存取存储器（MRAM）阵列的窄接点设计
公开(公告)号：US06567300B1
公开(公告)日：2003-05-20
申请号：US10080415
申请日：2002-02-22
申请人： Wolfgang Raberg , Heinz Hoenigschmid
发明人： Wolfgang Raberg , Heinz Hoenigschmid
IPC分类号： G11C1115
CPC分类号： G11C11/16 , H01L27/222 , Y10S977/943
摘要： An MRAM device (200) and method of manufacturing thereof having second conductive lines (228) with a narrow width. The second conductive lines (228) partially contact the resistive memory elements (214), reducing leakage currents in neighboring cells (214).
摘要翻译： MRAM器件（200）及其制造方法具有窄宽度的第二导线（228）。第二导线（228）部分地接触电阻性存储器元件（214），减少相邻单元（214）中的漏电流。

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