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1. 发明申请

US20130212427A1 RECLAIMING DISCARDED SOLID STATE DEVICES 有权
标题翻译：重新抛弃固定状态装置
公开(公告)号：US20130212427A1
公开(公告)日：2013-08-15
申请号：US13396020
申请日：2012-02-14
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G06F11/16
CPC分类号： G11C29/56008 , G06F11/2289 , G06F11/3409 , G11C16/349
摘要： Discarded memory devices unfit for an original purpose can be reclaimed for reuse for another purpose. The discarded memory devices are tested and evaluated to determine the level of performance degradation therein. A set of an alternate usage and an information encoding scheme to facilitate a reuse of the tested memory device is identified based on the evaluation of the discarded memory device. A memory chip controller may be configured to facilitate usage of reclaimed memory devices by enabling a plurality of encoding schemes therein. Further, a memory device can be configured to facilitate diagnosis of the functionality, and to facilitate usage as a discarded memory unit. Waste due to discarded memory devices can be thereby reduced.
摘要翻译：废弃的不适合原始目的的存储设备可以回收再利用用于另一目的。对废弃的存储器件进行测试和评估，以确定其中性能下降的程度。基于对废弃的存储器件的评估来识别一组替代使用和信息编码方案，以便于重新使用被测试的存储器件。存储器芯片控制器可以被配置为通过使能其中的多个编码方案来促进再生存储器件的使用。此外，存储器装置可以被配置为便于诊断功能，并且便于作为丢弃的存储器单元的使用。因此可以减少由于废弃的存储器件造成的浪费。

2. 发明申请

US20130166821A1 LOW LATENCY AND PERSISTENT DATA STORAGE 有权
标题翻译：低期和持续数据存储
公开(公告)号：US20130166821A1
公开(公告)日：2013-06-27
申请号：US13336287
申请日：2011-12-23
申请人： Blake G. Fitch , Michele M. Franceschini , Ashish Jagmohan , Todd E. Takken
发明人： Blake G. Fitch , Michele M. Franceschini , Ashish Jagmohan , Todd E. Takken
IPC分类号： G06F12/02
CPC分类号： G06F3/0611 , G06F3/0659 , G06F3/0688 , G06F11/1658 , G06F11/1666 , G06F12/02
摘要： Persistent data storage with low latency is provided by a method that includes receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed.
摘要翻译：具有低延迟的持久数据存储通过包括接收包括写入数据的低延迟存储命令的方法来提供。写入数据被写入由以第一访问速度为特征的非易失性固态存储器技术实现的第一存储器件。确认写入数据已成功写入第一个存储器件。写入数据被写入由易失性存储器技术实现的第二存储器件。当在第一存储装置中累积了预定量的数据时，第一存储装置中的数据的至少一部分被写入第三存储装置。第三存储器件通过非易失性固态存储器技术来实现，其特征在于比第一存取速度慢的第二存取速度。

3. 发明授权

US08464137B2 Probabilistic multi-tier error correction in not-and (NAND) flash memory 有权
标题翻译：不和（NAND）闪存中的概率多层纠错
公开(公告)号：US08464137B2
公开(公告)日：2013-06-11
申请号：US12960004
申请日：2010-12-03
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G06F11/00
CPC分类号： G06F11/1012 , H03M13/2906 , H03M13/3715 , H03M13/3738
摘要： Error correction in not-and (NAND) flash memory including a system for retrieving data from memory. The system includes a decoder in communication with a memory. The decoder is for performing a method that includes receiving a codeword stored on a page in the memory, the codeword including data and first-tier check symbols that are generated in response to the data. The method further includes determining that the codeword includes errors that cannot be corrected using the first-tier check symbols, and in response second-tier check symbols are received. The second-tier check symbols are generated in response to receiving the data and to the contents of other pages in the memory that were written prior to the page containing the codeword. The codeword is corrected in response to the second-tier check symbols. The corrected codeword is output.
摘要翻译：在非NAND（NAND）闪存中包括用于从存储器检索数据的系统的纠错。该系统包括与存储器通信的解码器。解码器用于执行包括接收存储在存储器中的页面上的码字的方法，所述码字包括响应于该数据生成的数据和第一层校验符号。该方法还包括确定码字包括不能使用第一层校验符号校正的错误，并且响应于接收到第二层校验符号。响应于接收到包含码字的页面之前写入的数据和存储器中其他页面的内容，生成第二层校验符号。响应于第二层校验符号校正码字。校正的码字被输出。

4. 发明授权

US08341612B2 Method and apparatus for run-time statistics dependent program execution using source-coding 有权
标题翻译：使用源代码的运行时统计依赖程序执行的方法和装置
公开(公告)号：US08341612B2
公开(公告)日：2012-12-25
申请号：US11749295
申请日：2007-05-16
申请人： Dake He , Ashish Jagmohan , Jian Lou , Ligang Lu
发明人： Dake He , Ashish Jagmohan , Jian Lou , Ligang Lu
IPC分类号： G06F9/455 , G06F17/50 , G06F9/45
CPC分类号： G06F9/30 , G06F8/4441 , G06F9/45525
摘要： Disclosed are a method and system for optimized, dynamic data-dependent program execution. The disclosed system comprises a statistics computer which computes statistics of the incoming data at the current time instant, where the said statistics include the probability distribution of the incoming data, the probability distribution over program modules induced by the incoming data, the probability distribution induced over program outputs by the incoming data, and the time-complexity of each program module for the incoming data, wherein the said statistics are computed on as a function of current and past data, and previously computed statistics; a plurality of alternative execution path orders designed prior to run-time by the use of an appropriate source code; a source code selector which selects one of the execution path orders as a function of the statistics computed by the statistics computer; a complexity measurement which measures the time-complexity of the currently selected execution path-order.
摘要翻译：公开了一种用于优化的动态数据相关程序执行的方法和系统。所公开的系统包括统计计算机，其计算当前时刻的输入数据的统计量，其中所述统计包括输入数据的概率分布，由输入数据引起的程序模块上的概率分布，所引入的概率分布输入数据的程序输出和输入数据的每个程序模块的时间 - 复杂度，其中根据当前和过去数据以及先前计算的统计量来计算所述统计; 通过使用适当的源代码在运行时间之前设计的多个替代执行路径命令; 源代码选择器，其根据由统计计算机计算出的统计量的函数选择执行路径顺序之一; 测量当前选择的执行路径顺序的时间 - 复杂度的复杂度测量。

5. 发明授权

US08341501B2 Adaptive endurance coding of non-volatile memories 有权
标题翻译：非易失性存储器的适应性耐力编码
公开(公告)号：US08341501B2
公开(公告)日：2012-12-25
申请号：US12433669
申请日：2009-04-30
申请人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano
发明人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G06F12/0246 , G06F11/1012 , G06F2212/1036 , G06F2212/401 , G06F2212/403 , G06F2212/7207 , G11C16/349
摘要： Adaptive endurance coding including a method for storing data that includes receiving write data and a write address. A compression algorithm is applied to the write data to generate compressed data. An endurance code is applied to the compressed data to generate a codeword. The endurance code is selected and applied in response to the amount of space saved by applying the compression to the write data. The codeword is written to the write address.
摘要翻译：自适应耐力编码包括用于存储包括接收写入数据和写入地址的数据的方法。将压缩算法应用于写入数据以生成压缩数据。将耐力码应用于压缩数据以产生码字。响应于通过将压缩应用于写数据而节省的空间量来选择和应用耐久代码。代码字被写入写入地址。

6. 发明授权

US08331168B2 Increased capacity heterogeneous storage elements 有权
标题翻译：增加容量的异构存储元件
公开(公告)号：US08331168B2
公开(公告)日：2012-12-11
申请号：US12433157
申请日：2009-04-30
申请人： Ibrahim M. Elfadel , Michele Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Ibrahim M. Elfadel , Michele Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G11C7/00
CPC分类号： G11C29/08 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0076 , G11C2211/5641
摘要： Providing increased capacity in heterogeneous storage elements including a method for storing data including a write process writing to a memory and a read process reading from the memory. Physical characteristics of memory cells in the memory support different sets of data levels. The write process takes into account the different sets of data levels when writing to the memory. The read process first obtains data in the memory and subsequently determines how to interpret the data.
摘要翻译：提供异构存储元件的增加的容量，包括用于存储数据的方法，包括对存储器的写入过程写入和从存储器读取读取过程。存储器单元的物理特性在存储器中支持不同的数据级别。写入过程在写入存储器时考虑到不同的数据级别集。读取过程首先获得存储器中的数据，然后确定如何解释数据。

7. 发明申请

US20120311262A1 MEMORY CELL PRESETTING FOR IMPROVED MEMORY PERFORMANCE 审中-公开
标题翻译：用于改善记忆性能的存储单元预置
公开(公告)号：US20120311262A1
公开(公告)日：2012-12-06
申请号：US13151043
申请日：2011-06-01
申请人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
发明人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/00 , G06F12/08 , G06F12/0802 , G06F12/0891
摘要： Memory cell presetting for improved performance including a system that includes a memory, a cache, and a memory controller. The memory includes memory lines made up of memory cells. The cache includes cache lines that correspond to a subset of the memory lines. The memory controller is in communication with the memory and the cache. The memory controller is configured to perform a method that includes scheduling a request to set memory cells of a memory line to a common specified state in response to a cache line attaining a dirty state.
摘要翻译：用于改进性能的存储单元预置，包括包括存储器，高速缓存和存储器控制器的系统。存储器包括由存储单元组成的存储器线。缓存包括对应于存储器线的子集的高速缓存行。存储器控制器与存储器和缓存器通信。存储器控制器被配置为执行一种方法，该方法包括根据达到肮脏状态的高速缓存线来调度将存储器线的存储单元设置为公共指定状态的请求。

8. 发明授权

US08176234B2 Multi-write coding of non-volatile memories 有权
标题翻译：非易失性存储器的多写编码
公开(公告)号：US08176234B2
公开(公告)日：2012-05-08
申请号：US12631470
申请日：2009-12-04
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/401 , G11C11/5621 , G11C16/3418 , G11C16/349
摘要： Multi-write coding of non-volatile memories including a method that receives write data, and a write address of a memory page. The memory page is in either an erased state or a previously written state. If the memory page is in the erased state: selecting a first codeword from a code such that the first codeword encodes the write data and is consistent with a target set of distributions of electrical charge levels in the memory page; and writing the first codeword to the memory page. If the memory page is in the previously written state: selecting a coset from a linear code such that the coset encodes the write data and includes one or more words that are consistent with previously written content of the memory page; selecting a subsequent codeword from the one or more words in the coset; and writing the subsequent codeword to the memory page.
摘要翻译：包括接收写入数据的方法的非易失性存储器的多写入编码以及存储器页面的写入地址。存储器页面处于擦除状态或先前写入的状态。如果存储器页面处于擦除状态：从代码中选择第一码字，使得第一码字对写入数据进行编码，并与存储器页面中的电荷电平分布的目标集合一致; 以及将所述第一码字写入所述存储器页。如果存储器页面处于先前写入的状态：从线性代码选择陪集，使得陪集对编写数据进行编码并且包括与存储器页面的先前写入的内容一致的一个或多个单词; 从陪集中的一个或多个单词中选择随后的码字; 以及将所述后续码字写入所述存储器页面。

9. 发明授权

US08160130B2 System and method for the dynamic resolution change for video encoding 有权
标题翻译：用于视频编码的动态分辨率变化的系统和方法
公开(公告)号：US08160130B2
公开(公告)日：2012-04-17
申请号：US11931512
申请日：2007-10-31
申请人： Krishna C. Ratakonda , Ashish Jagmohan
发明人： Krishna C. Ratakonda , Ashish Jagmohan
IPC分类号： H04N7/12 , H04N11/02 , H04N11/04
CPC分类号： H04N19/59 , H04N19/107 , H04N19/117 , H04N19/137 , H04N19/14 , H04N19/142 , H04N19/146 , H04N19/152 , H04N19/164
摘要： The present invention relates to a method, system and computer program product for the predictive encoding of digital video sequences. The objectives of the invention are accomplished by dynamically determining the resolution of a current frame being encoded and outputting the determination. The determination process is based on statistical and coding information of a plurality of frames, including at least one previous frame and the current frame. Further, general encoding parameters and the encoding parameters of a current frame at a chosen resolution are determined, wherein the encoding parameter selection step takes into account the determination of the dynamic resolution determination step in determining the encoding parameters.
摘要翻译：本发明涉及用于数字视频序列的预测编码的方法，系统和计算机程序产品。本发明的目的通过动态地确定正被编码的当前帧的分辨率并输出该确定来实现。确定处理基于包括至少一个先前帧和当前帧的多个帧的统计和编码信息。此外，确定所选分辨率下的当前帧的一般编码参数和编码参数，其中编码参数选择步骤在确定编码参数时考虑动态分辨率确定步骤的确定。

10. 发明申请

US20110246703A1 CONSTRAINED CODING TO REDUCE FLOATING GATE COUPLING IN NON-VOLATILE MEMORIES 失效
标题翻译：约束编码以减少非易失性存储器中的浮动栅极耦合
公开(公告)号：US20110246703A1
公开(公告)日：2011-10-06
申请号：US12751197
申请日：2010-03-31
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G11C16/0483 , G06F12/0246 , G06F2212/7202 , G11C7/1006 , G11C16/10
摘要： Constrained coding to reduce floating gate coupling in non-volatile memories including a method for storing data. The method includes receiving write data to be written to a flash memory device, selecting a codeword in response to the write data, and writing the codeword to the flash memory device. The codeword is selected to reduce floating gate coupling in the flash memory device by preventing specified symbol patterns from occurring in the codeword.
摘要翻译：约束编码以减少非易失性存储器中的浮动栅极耦合，包括用于存储数据的方法。该方法包括接收要写入闪速存储器件的写入数据，响应写入数据选择一个代码字，以及将该代码字写入闪存器件。选择码字以通过防止在码字中发生指定的符号模式来减少闪存器件中的浮动栅极耦合。

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