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1. 发明申请

US20130212427A1 RECLAIMING DISCARDED SOLID STATE DEVICES 有权
标题翻译：重新抛弃固定状态装置
公开(公告)号：US20130212427A1
公开(公告)日：2013-08-15
申请号：US13396020
申请日：2012-02-14
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G06F11/16
CPC分类号： G11C29/56008 , G06F11/2289 , G06F11/3409 , G11C16/349
摘要： Discarded memory devices unfit for an original purpose can be reclaimed for reuse for another purpose. The discarded memory devices are tested and evaluated to determine the level of performance degradation therein. A set of an alternate usage and an information encoding scheme to facilitate a reuse of the tested memory device is identified based on the evaluation of the discarded memory device. A memory chip controller may be configured to facilitate usage of reclaimed memory devices by enabling a plurality of encoding schemes therein. Further, a memory device can be configured to facilitate diagnosis of the functionality, and to facilitate usage as a discarded memory unit. Waste due to discarded memory devices can be thereby reduced.
摘要翻译：废弃的不适合原始目的的存储设备可以回收再利用用于另一目的。对废弃的存储器件进行测试和评估，以确定其中性能下降的程度。基于对废弃的存储器件的评估来识别一组替代使用和信息编码方案，以便于重新使用被测试的存储器件。存储器芯片控制器可以被配置为通过使能其中的多个编码方案来促进再生存储器件的使用。此外，存储器装置可以被配置为便于诊断功能，并且便于作为丢弃的存储器单元的使用。因此可以减少由于废弃的存储器件造成的浪费。

2. 发明授权

US08472224B2 Adjustable write bins for multi-level analog memories 失效
标题翻译：适用于多级模拟存储器的可调式写入箱
公开(公告)号：US08472224B2
公开(公告)日：2013-06-25
申请号：US13355833
申请日：2012-01-23
申请人： Ibrahim M. Elfadel , Michele M. Franceschini , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Ibrahim M. Elfadel , Michele M. Franceschini , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C27/00
CPC分类号： G11C8/10 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C27/005 , G11C2013/0083
摘要： Selecting bins in a memory by receiving a target cost for performing writes at an analog memory that is capable of storing a range of values. Possible bins that may be created in the range of values and a cost associated with each possible bin are determined. Each possible bin includes one or more of the values. A group of bins are identified, the group of bins are among the possible bins with associated costs that are within a threshold of the target cost. A maximum number of bins are selected from the group of bins that have non-overlapping values. The selected bins are stored along with the values of the selected bins utilized to encode and decode contents of the analog memory.
摘要翻译：通过接收在能够存储一定范围的值的模拟存储器上执行写入的目标成本来选择存储器中的存储器。确定可能在值范围内创建的可能的仓和与每个可能仓相关联的成本。每个可能的仓包括一个或多个值。识别出一组垃圾箱，这些垃圾箱是可能的垃圾箱，其相关成本在目标成本的阈值之内。从具有非重叠值的分组组中选择最大数量的分区。所选择的存储槽与用于对模拟存储器的内容进行编码和解码的所选择的存储器的值一起存储。

3. 发明授权

US08464137B2 Probabilistic multi-tier error correction in not-and (NAND) flash memory 有权
标题翻译：不和（NAND）闪存中的概率多层纠错
公开(公告)号：US08464137B2
公开(公告)日：2013-06-11
申请号：US12960004
申请日：2010-12-03
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G06F11/00
CPC分类号： G06F11/1012 , H03M13/2906 , H03M13/3715 , H03M13/3738
摘要： Error correction in not-and (NAND) flash memory including a system for retrieving data from memory. The system includes a decoder in communication with a memory. The decoder is for performing a method that includes receiving a codeword stored on a page in the memory, the codeword including data and first-tier check symbols that are generated in response to the data. The method further includes determining that the codeword includes errors that cannot be corrected using the first-tier check symbols, and in response second-tier check symbols are received. The second-tier check symbols are generated in response to receiving the data and to the contents of other pages in the memory that were written prior to the page containing the codeword. The codeword is corrected in response to the second-tier check symbols. The corrected codeword is output.
摘要翻译：在非NAND（NAND）闪存中包括用于从存储器检索数据的系统的纠错。该系统包括与存储器通信的解码器。解码器用于执行包括接收存储在存储器中的页面上的码字的方法，所述码字包括响应于该数据生成的数据和第一层校验符号。该方法还包括确定码字包括不能使用第一层校验符号校正的错误，并且响应于接收到第二层校验符号。响应于接收到包含码字的页面之前写入的数据和存储器中其他页面的内容，生成第二层校验符号。响应于第二层校验符号校正码字。校正的码字被输出。

4. 发明授权

US08331168B2 Increased capacity heterogeneous storage elements 有权
标题翻译：增加容量的异构存储元件
公开(公告)号：US08331168B2
公开(公告)日：2012-12-11
申请号：US12433157
申请日：2009-04-30
申请人： Ibrahim M. Elfadel , Michele Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Ibrahim M. Elfadel , Michele Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G11C7/00
CPC分类号： G11C29/08 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0076 , G11C2211/5641
摘要： Providing increased capacity in heterogeneous storage elements including a method for storing data including a write process writing to a memory and a read process reading from the memory. Physical characteristics of memory cells in the memory support different sets of data levels. The write process takes into account the different sets of data levels when writing to the memory. The read process first obtains data in the memory and subsequently determines how to interpret the data.
摘要翻译：提供异构存储元件的增加的容量，包括用于存储数据的方法，包括对存储器的写入过程写入和从存储器读取读取过程。存储器单元的物理特性在存储器中支持不同的数据级别。写入过程在写入存储器时考虑到不同的数据级别集。读取过程首先获得存储器中的数据，然后确定如何解释数据。

5. 发明授权

US08230276B2 Writing to memory using adaptive write techniques 有权
标题翻译：使用自适应写入技术写入内存
公开(公告)号：US08230276B2
公开(公告)日：2012-07-24
申请号：US12568035
申请日：2009-09-28
申请人： Stefanie Chiras , Michele Franceschini , John P. Karidis , Luis A. Lastras , Mayank Sharma
发明人： Stefanie Chiras , Michele Franceschini , John P. Karidis , Luis A. Lastras , Mayank Sharma
IPC分类号： G11C29/00
CPC分类号： G11C13/0004 , G11C13/0069 , G11C16/10 , G11C16/3459 , G11C2013/0076
摘要： Techniques for writing to memory using adaptive write techniques. An adaptive write technique includes receiving at a computer a message including a plurality of symbols. The message is written to a memory. The writing to memory includes performing for each symbol in the message: writing a data value to a memory location in the memory and reading contents of the memory location after the data value has been written. The data value is determined at the computer in response to the symbol and to the contents of any memory locations previously read as part of writing the message to the memory. It is determined at the computer if the contents of the memory locations reflect the message. The writing is restarted at the computer in response to determining that the contents of the memory locations do not reflect the message.
摘要翻译：使用自适应写入技术写入存储器的技术。一种自适应写入技术包括在计算机处接收包括多个符号的消息。消息被写入存储器。对存储器的写入包括对消息中的每个符号执行：将数据值写入存储器中的存储器位置，并且在写入数据值之后读取存储器位置的内容。数据值在计算机响应于符号以及先前读取的任何存储器位置的内容来确定，作为将消息写入存储器的一部分。在计算机中确定存储器位置的内容是否反映消息。响应于确定存储器位置的内容不反映消息，在计算机上重新开始写入。

6. 发明申请

US20110246703A1 CONSTRAINED CODING TO REDUCE FLOATING GATE COUPLING IN NON-VOLATILE MEMORIES 失效
标题翻译：约束编码以减少非易失性存储器中的浮动栅极耦合
公开(公告)号：US20110246703A1
公开(公告)日：2011-10-06
申请号：US12751197
申请日：2010-03-31
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G11C16/0483 , G06F12/0246 , G06F2212/7202 , G11C7/1006 , G11C16/10
摘要： Constrained coding to reduce floating gate coupling in non-volatile memories including a method for storing data. The method includes receiving write data to be written to a flash memory device, selecting a codeword in response to the write data, and writing the codeword to the flash memory device. The codeword is selected to reduce floating gate coupling in the flash memory device by preventing specified symbol patterns from occurring in the codeword.
摘要翻译：约束编码以减少非易失性存储器中的浮动栅极耦合，包括用于存储数据的方法。该方法包括接收要写入闪速存储器件的写入数据，响应写入数据选择一个代码字，以及将该代码字写入闪存器件。选择码字以通过防止在码字中发生指定的符号模式来减少闪存器件中的浮动栅极耦合。

7. 发明申请

US20110078392A1 WRITING TO MEMORY USING ADAPTIVE WRITE TECHNIQUES 有权
标题翻译：使用自适应写入技术写入记忆
公开(公告)号：US20110078392A1
公开(公告)日：2011-03-31
申请号：US12568035
申请日：2009-09-28
申请人： Stefanie Chiras , Michele Franceschini , John P. Karidis , Luis A. Lastras , Mayank Sharma
发明人： Stefanie Chiras , Michele Franceschini , John P. Karidis , Luis A. Lastras , Mayank Sharma
IPC分类号： G06F12/00
CPC分类号： G11C13/0004 , G11C13/0069 , G11C16/10 , G11C16/3459 , G11C2013/0076
摘要： Techniques for writing to memory using adaptive write techniques. An adaptive write technique includes receiving at a computer a message including a plurality of symbols. The message is written to a memory. The writing to memory includes performing for each symbol in the message: writing a data value to a memory location in the memory and reading contents of the memory location after the data value has been written. The data value is determined at the computer in response to the symbol and to the contents of any memory locations previously read as part of writing the message to the memory. It is determined at the computer if the contents of the memory locations reflect the message. The writing is restarted at the computer in response to determining that the contents of the memory locations do not reflect the message.
摘要翻译：使用自适应写入技术写入存储器的技术。自适应写入技术包括在计算机处接收包括多个符号的消息。消息被写入存储器。对存储器的写入包括对消息中的每个符号执行：将数据值写入存储器中的存储器位置，并且在写入数据值之后读取存储器位置的内容。数据值在计算机响应于符号以及先前读取的任何存储器位置的内容来确定，作为将消息写入存储器的一部分。在计算机中确定存储器位置的内容是否反映消息。响应于确定存储器位置的内容不反映消息，在计算机上重新开始写入。

8. 发明申请

US20230025256A1 PROTEIN BLOCKING ASSEMBLY AND METHODS OF MAKING AND USING 有权
公开(公告)号：US20230025256A1
公开(公告)日：2023-01-26
申请号：US17782717
申请日：2020-12-03
申请人： SIMON FRIEDMAN , SWETHA CHINTALA , MAYANK SHARMA
发明人： SIMON FRIEDMAN , SWETHA CHINTALA , MAYANK SHARMA
IPC分类号： C07K14/605 , C07K14/62 , C07K14/705
摘要： Certain aspects of the present invention are directed to a method for making a protein blocking assembly reversibly linking a therapeutic protein to a blocking group via a linker moiety. Additional aspects of the invention are directed to the protein blocking assembly, and to methods of administering the protein blocking assembly to a subject, where the protein is cleaved from the protein blocking assembly.

9. 发明申请

US20120290778A1 INCREASED CAPACITY HETEROGENEOUS STORAGE ELEMENTS 有权
标题翻译：增加容量异质存储元素
公开(公告)号：US20120290778A1
公开(公告)日：2012-11-15
申请号：US13557294
申请日：2012-07-25
申请人： Ibrahim M. Elfadel , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Ibrahim M. Elfadel , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G11C29/08 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0076 , G11C2211/5641
摘要： Providing increased capacity in heterogeneous storage elements including a method for storing data in a heterogeneous memory that includes receiving a write message and a write address corresponding to a block of memory cells where at least two of the memory cells support different data levels, determining physical characteristics of the memory cells, and identifying virtual memories associated with the block of memory cells in response to the physical characteristics. The following is performed for each of the virtual memories: generating a constraint vector that describes the virtual cells in the virtual memory; and calculating a virtual write vector in response to the constraint vector and the write data, the calculating including writing the write data, bit by bit, in order, into the virtual memory, skipping locations known to be stuck to a particular value as indicated by the constraint vector. The virtual write vectors are combined into a write word and the write word is output to the block of memory cells.
摘要翻译：提供异构存储元件中的增加的容量，包括用于在异构存储器中存储数据的方法，该方法包括接收对应于其中至少两个存储器单元支持不同数据电平的存储器单元块的写入消息和写入地址，确定物理特性并且响应于物理特性识别与存储器单元块相关联的虚拟存储器。对每个虚拟存储器执行以下操作：生成描述虚拟存储器中的虚拟单元的约束向量; 以及响应于所述约束向量和所述写入数据计算虚拟写入向量，所述计算包括按顺序将所述写入数据逐位写入到所述虚拟存储器中，跳过已知被粘附到特定值的位置，如约束向量。虚拟写入向量被组合成写入字，并将写入字输出到存储器单元块。

10. 发明申请

US20120144272A1 PROBABILISTIC MULTI-TIER ERROR CORRECTION IN NOT-AND (NAND) FLASH MEMORY 有权
标题翻译：非 - 和（NAND）闪存中的概念多层错误校正
公开(公告)号：US20120144272A1
公开(公告)日：2012-06-07
申请号：US12960004
申请日：2010-12-03
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1012 , H03M13/2906 , H03M13/3715 , H03M13/3738
摘要： Error correction in not-and (NAND) flash memory including a system for retrieving data from memory. The system includes a decoder in communication with a memory. The decoder is for performing a method that includes receiving a codeword stored on a page in the memory, the codeword including data and first-tier check symbols that are generated in response to the data. The method further includes determining that the codeword includes errors that cannot be corrected using the first-tier check symbols, and in response second-tier check symbols are received. The second-tier check symbols are generated in response to receiving the data and to the contents of other pages in the memory that were written prior to the page containing the codeword. The codeword is corrected in response to the second-tier check symbols. The corrected codeword is output.
摘要翻译：在非NAND（NAND）闪存中包括用于从存储器检索数据的系统的纠错。该系统包括与存储器通信的解码器。解码器用于执行包括接收存储在存储器中的页面上的码字的方法，所述码字包括响应于该数据生成的数据和第一层校验符号。该方法还包括确定码字包括不能使用第一层校验符号校正的错误，并且响应于接收到第二层校验符号。响应于接收到包含码字的页面之前写入的数据和存储器中的其他页面的内容，生成第二层校验符号。响应于第二层校验符号校正码字。校正的码字被输出。

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