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1. 发明申请

US20220114103A1 GRAPH MEMORY ENGINE 有权
公开(公告)号：US20220114103A1
公开(公告)日：2022-04-14
申请号：US17378647
申请日：2021-07-16
申请人： MoSys, Inc.
发明人： Michael J. Miller
IPC分类号： G06F12/0875
摘要： A system, method, and apparatus for graph memory. In one embodiment, the method includes: traversing program instructions disposed in an associative memory for operating a computer, the method comprising: receiving input data to be processed; identifying a next instruction to be fetched in the memory for processing the input data via: receiving a current node ID of a current state; performing a computational test on the input data resulting in a computed value; generating a search key by combining at least a portion of the computed edge value with the current node ID; and accessing the next instruction in associative memory via the search key.

2. 发明授权

US10114558B2 Integrated main memory and coprocessor with low latency 有权
公开(公告)号：US10114558B2
公开(公告)日：2018-10-30
申请号：US15898659
申请日：2018-02-18
申请人： MoSys, Inc.
发明人： Michael J. Miller , Jay B Patel , Michael J Morrison
IPC分类号： G06F3/06 , G06F9/38 , G06F12/00 , H04L29/12 , H04L29/08 , G06F12/0875 , G06F12/0895
摘要： System, method, and apparatus for integrated main memory (MM) and configurable coprocessor (CP) chip for processing subset of network functions. Chip supports external accesses to MM without additional latency from on-chip CP. On-chip memory scheduler resolves all bank conflicts and configurably load balances MM accesses. Instruction set and data on which the CP executes instructions are all disposed on-chip with no on-chip cache memory, thereby avoiding latency and coherency issues. Multiple independent and orthogonal threading domains used: a FIFO-based scheduling domain (SD) for the I/O; a multi-threaded processing domain for the CP. The CP is an array of independent, autonomous, unsequenced processing engines processing on-chip data tracked by SD of external CMD and reordered per FIFO CMD sequence before transmission. Paired I/O ports tied to unique global on-chip SD allow multiple external processors to slave chip and its resources independently and autonomously without scheduling between the external processors.

3. 发明申请

US20130329553A1 TRAFFIC METERING AND SHAPING FOR NETWORK PACKETS 审中-公开
标题翻译：网络包的交通计费和形状
公开(公告)号：US20130329553A1
公开(公告)日：2013-12-12
申请号：US13838971
申请日：2013-03-15
申请人： MoSys, Inc.
发明人： Mankit Tang , Jay Patel , Michael J. Miller
IPC分类号： H04L12/815
CPC分类号： H04L47/10 , G06F9/3005 , G06F13/128 , H04L47/22
摘要： An integrated circuit device comprising, an interface configured to receive signals external to said integrated circuit device; a memory; a logic unit; and a lookup table coupled with the logic unit, wherein the lookup table is configured to govern traffic of a network.
摘要翻译：一种集成电路装置，包括：被配置为在所述集成电路装置外部接收信号的接口; 记忆一个逻辑单元; 以及与所述逻辑单元耦合的查找表，其中所述查找表被配置为管理网络的业务。

4. 发明申请

US20130332681A1 MEMORY SYSTEM INCLUDING VARIABLE WRITE BURST AND BROADCAST COMMAND SCHEDULING 有权
标题翻译：存储系统，包括可变写波峰和广播命令调度
公开(公告)号：US20130332681A1
公开(公告)日：2013-12-12
申请号：US13911218
申请日：2013-06-06
申请人： MoSys, Inc.
发明人： Michael J. Miller , Michael J. Morrison , Jay B. Patel
IPC分类号： G06F3/06
CPC分类号： G06F3/0659 , G06F3/0644 , G06F9/3004 , G06F13/1626 , G06F13/1642 , G06F13/28
摘要： A system includes a host device that may be configured to initiate memory requests to a system memory. The system also includes a memory controller that may be configured receive the memory requests and to format the memory requests into memory transactions that are conveyed to the memory device via a memory interface. The memory transactions include a memory write burst command having a first frame that includes a corresponding opcode positioned in one of a first command slot or a second command slot. The memory write burst command may also include a number of subsequent frames for conveying a data payload, as specified for example, by the opcode. The control unit may be configured to generate a number of concurrent sequential memory write operations to the memory in response to receiving the memory write burst command.
摘要翻译：系统包括主机设备，其可以被配置为向系统存储器发起存储器请求。该系统还包括可被配置为接收存储器请求并且将存储器请求格式化成通过存储器接口传送到存储器设备的存储器事务的存储器控制器。存储器事务包括具有第一帧的存储器写突发命令，该第一帧包括位于第一命令槽或第二命令槽之一中的对应操作码。存储器写突发命令还可以包括用于传送例如由操作码指定的数据有效载荷的多个后续帧。控制单元可以被配置为响应于接收到存储器写入突发命令而向存储器生成多个并行顺序存储器写入操作。

5. 发明授权

US09971567B2 Method and apparatus for randomizer 有权
公开(公告)号：US09971567B2
公开(公告)日：2018-05-15
申请号：US15390715
申请日：2016-12-26
申请人： MoSys, Inc.
发明人： Michael J. Miller , Michael J. Morrison , Jay B Patel
IPC分类号： G06F7/58
CPC分类号： G06F7/582
摘要： The randomizer includes connection circuitry with a random connection layout to parallely couple each of a quantity of bits for each of a plurality of inputs of bit width n to multiple output bits of a respectively coupled output. Combinational circuitry combines at least a portion of each of the plurality of outputs associated with each of the plurality of inputs to create a single resultant output of random data having a bit width of the quantity n.

6. 发明申请

US20170109135A1 Method and Apparatus for Randomizer 有权
公开(公告)号：US20170109135A1
公开(公告)日：2017-04-20
申请号：US15390715
申请日：2016-12-26
申请人： MoSys, Inc.
发明人： Michael J. Miller , Michael J. Morrison , Jay B. Patel
IPC分类号： G06F7/58
CPC分类号： G06F7/582
摘要： A Method and Apparatus for Randomizer has been disclosed. In one implementation a sequence of randomized connections then exclusive-OR operations and then an adder produce a randomized output.

7. 发明授权

US09496009B2 Memory with bank-conflict-resolution (BCR) module including cache 有权
标题翻译：具有银行冲突解决（BCR）模块的内存包括缓存
公开(公告)号：US09496009B2
公开(公告)日：2016-11-15
申请号：US13841025
申请日：2013-03-15
申请人： MoSys, Inc.
发明人： Dipak Sikdar , Michael J. Miller , Jay Patel
IPC分类号： G11C7/10 , G06F12/08 , G11C8/12 , G11C8/18 , G11C11/417
CPC分类号： G11C7/1072 , G06F12/0802 , G06F2212/304 , G11C7/1039 , G11C8/12 , G11C8/18 , G11C11/417 , G11C2207/2209 , G11C2207/2245
摘要： A memory device includes a block of memory cells and a cache. The block of memory cells is a random access memory with multiple ports. The block of memory cells is partitioned into subunits that have only a single port. The cache is coupled to the block of memory cells adapted to handle a plurality of accesses to a same subunit of memory cells without a conflict such that the memory appears to be a random access memory to said plurality of accesses. A method of operating the memory, and a memory with bank-conflict-resolution (BCR) module including cache are also provided.
摘要翻译：存储器件包括存储器单元块和高速缓存。存储器单元块是具有多个端口的随机存取存储器。存储器单元块被分割成仅具有单个端口的子单元。高速缓存耦合到适于处理对存储器单元的相同子单元的多个访问的存储器单元块而不产生冲突，使得存储器看起来是对所述多个访问的随机存取存储器。还提供了一种操作存储器的方法，以及具有包含缓存的存储体冲突解决（BCR）模块的存储器。

8. 发明申请

US20160188222A1 Integrated Main Memory And Coprocessor With Low Latency 审中-公开
标题翻译：集成主存储器和低延迟的协处理器
公开(公告)号：US20160188222A1
公开(公告)日：2016-06-30
申请号：US14872002
申请日：2015-09-30
申请人： MoSys, Inc.
发明人： Michael J. Miller , Jay B. Patel , Michael J. Morrison
IPC分类号： G06F3/06 , G06F12/08
CPC分类号： G06F3/0611 , G06F3/0659 , G06F3/067 , G06F9/3877 , G06F12/00 , G06F12/0875 , G06F12/0895 , G06F2212/1024 , G06F2212/452 , G06F2212/604 , H04L29/12 , H04L67/1017 , H04L67/2842
摘要： System, method, and apparatus for integrated main memory (MM) and configurable coprocessor (CP) chip for processing subset of network functions. Chip supports external accesses to MM without additional latency from on-chip CP. On-chip memory scheduler resolves all bank conflicts and configurably load balances MM accesses. Instruction set and data on which the CP executes instructions are all disposed on-chip with no on-chip cache memory, thereby avoiding latency and coherency issues. Multiple independent and orthogonal threading domains used: a FIFO-based scheduling domain (SD) for the I/O; a multi-threaded processing domain for the CP. The CP is an array of independent, autonomous, unsequenced processing engines processing on-chip data tracked by SD of external CMD and reordered per FIFO CMD sequence before transmission. Paired I/O ports tied to unique global on-chip SD allow multiple external processors to slave chip and its resources independently and autonomously without scheduling between the external processors.
摘要翻译：用于集成主存储器（MM）和可配置协处理器（CP）芯片的系统，方法和装置，用于处理网络功能的子集。芯片支持对MM的外部访问，而无需片上CP的额外延迟。片上存储器调度器可以解决所有存储体冲突和可配置的MM访问负载平衡。 CP执行指令的指令集和数据都片上放置，没有片上高速缓存，从而避免延迟和一致性问题。使用多个独立和正交的线程域：用于I / O的基于FIFO的调度域（SD）; CP的多线程处理域。 CP是独立的，自主的，未排序的处理引擎的阵列，处理由外部CMD的SD跟踪的片上数据，并且在传输之前对每个FIFO CMD序列重新排序。绑定到独特的全局片上SD的配对I / O端口允许多个外部处理器独立和自主地从属芯片及其资源，而无需在外部处理器之间进行调度。

9. 发明申请

US20190332274A1 PROCESSING ENGINES COUPLED WITH READ WRITE MODIFY MEMORY 审中-公开
公开(公告)号：US20190332274A1
公开(公告)日：2019-10-31
申请号：US16174268
申请日：2018-10-29
申请人： MoSys, Inc.
发明人： Michael J. Miller , Jay B. Patel , Michael J. Morrison
IPC分类号： G06F3/06 , H04L29/08 , G06F12/0895 , G06F12/00 , H04L29/12 , G06F9/38 , G06F12/0875
摘要： System, method, and apparatus for integrated main memory (MM) and configurable coprocessor (CP) chip for processing subset of network functions. Chip supports external accesses to MM without additional latency from on-chip CP. On-chip memory scheduler resolves all bank conflicts and configurably load balances MM accesses. Instruction set and data on which the CP executes instructions are all disposed on-chip with no on-chip cache memory, thereby avoiding latency and coherency issues. Multiple independent and orthogonal threading domains used: a FIFO-based scheduling domain (SD) for the I/O; a multi-threaded processing domain for the CP. The CP is an array of independent, autonomous, unsequenced processing engines processing on-chip data tracked by SD of external CMD and reordered per FIFO CMD sequence before transmission. Paired I/O ports tied to unique global on-chip SD allow multiple external processors to slave chip and its resources independently and autonomously without scheduling between the external processors.

10. 发明申请

US20180173433A1 Integrated Main Memory And Coprocessor With Low Latency 审中-公开
公开(公告)号：US20180173433A1
公开(公告)日：2018-06-21
申请号：US15898659
申请日：2018-02-18
申请人： MoSys, Inc.
发明人： Michael J. Miller , Jay B. Patel , Michael J. Morrison
IPC分类号： G06F3/06 , G06F12/0895 , G06F9/38 , G06F12/00 , G06F12/0875 , H04L29/12 , H04L29/08
CPC分类号： G06F3/0611 , G06F3/0659 , G06F3/067 , G06F9/3877 , G06F12/00 , G06F12/0875 , G06F12/0895 , G06F2212/1024 , G06F2212/452 , G06F2212/604 , H04L29/12 , H04L67/1017 , H04L67/2842
摘要： System, method, and apparatus for integrated main memory (MM) and configurable coprocessor (CP) chip for processing subset of network functions. Chip supports external accesses to MM without additional latency from on-chip CP. On-chip memory scheduler resolves all bank conflicts and configurably load balances MM accesses. Instruction set and data on which the CP executes instructions are all disposed on-chip with no on-chip cache memory, thereby avoiding latency and coherency issues. Multiple independent and orthogonal threading domains used: a FIFO-based scheduling domain (SD) for the I/O; a multi-threaded processing domain for the CP. The CP is an array of independent, autonomous, unsequenced processing engines processing on-chip data tracked by SD of external CMD and reordered per FIFO CMD sequence before transmission. Paired I/O ports tied to unique global on-chip SD allow multiple external processors to slave chip and its resources independently and autonomously without scheduling between the external processors.

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