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1. 发明授权

US08377267B2 Foil plating for semiconductor packaging 有权
标题翻译：半导体封装镀膜
公开(公告)号：US08377267B2
公开(公告)日：2013-02-19
申请号：US12571223
申请日：2009-09-30
申请人： Jaime A. Bayan , Nghia Thuc Tu , Will K. Wong
发明人： Jaime A. Bayan , Nghia Thuc Tu , Will K. Wong
IPC分类号： C25D17/00 , B65G49/02
CPC分类号： C25D5/028 , C25D7/0635 , H01L23/49582 , H01L24/45 , H01L2224/45144 , H01L2224/48639 , H01L2224/85439 , H01L2924/00014 , H01L2924/14 , H01L2224/48 , H01L2924/00
摘要： Arrangements for plating a single surface of a thin foil are described. In one aspect, a metal foil is wrapped tightly at least partially around a plating solution drum. The drum is partially immersed in a plating solution such that the waterline of the metal plating solution is below a break point where the metallic foil strip begins to unwind from the plating solution drum. With this arrangement, one side of the metallic foil strip is exposed to the metal plating solution, while the opposing back side of the metallic foil strip does not come in substantial contact with the metal plating solution. In this manner, the exposed side of the foil is plated while the back surface of the foil is not plated. The drum may be rotated to convey the foil through the plating solution.
摘要翻译：描述了用于镀覆薄箔的单个表面的布置。在一个方面，金属箔至少部分地围绕电镀液桶包裹。将滚筒部分地浸入电镀溶液中，使得金属电镀溶液的水线低于金属箔带开始从电镀液滚筒放卷的断点。通过这种布置，金属箔条的一侧暴露于金属镀液，而金属箔条的相对背面不与金属电镀液基本接触。以这种方式，箔的暴露面被镀覆，而箔的背面不被镀覆。滚筒可以旋转以将箔传送通过电镀溶液。

2. 发明授权

US07846775B1 Universal lead frame for micro-array packages 有权
标题翻译：通用引线框架用于微阵列封装
公开(公告)号：US07846775B1
公开(公告)日：2010-12-07
申请号：US11135836
申请日：2005-05-23
申请人： Shaw Wei Lee , Nghia Thuc Tu , Sadanand R. Patil
发明人： Shaw Wei Lee , Nghia Thuc Tu , Sadanand R. Patil
IPC分类号： H01L21/00
CPC分类号： H01L21/4821 , H01L21/4828 , H01L21/4842 , H01L21/568 , H01L21/6835 , H01L23/3107 , H01L23/4951 , H01L23/49541 , H01L23/49582 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/83 , H01L24/85 , H01L24/97 , H01L2224/29007 , H01L2224/32014 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48599 , H01L2224/49171 , H01L2224/73265 , H01L2224/83101 , H01L2224/85001 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/15747 , H01L2924/181 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599
摘要： Techniques for forming micro-array style packages are disclosed. A matrix of isolated contact posts are placed on an adhesive carrier. Dice are then mounted (directly or indirectly) on the carrier and each die is electrically connected to a plurality of associated contacts. The dice and portions of the contacts are then encapsulated in a manner that leaves at least bottom portions of the contacts exposed to facilitate electrical connection to external devices. The encapsulant serves to hold the contacts in place after the carrier has been removed.
摘要翻译：公开了用于形成微阵列风格包装的技术。将隔离的接触柱的矩阵放置在粘合剂载体上。然后将骰子（直接或间接地）安装在载体上，并且每个管芯电连接到多个相关的触点。然后，以使得触点的至少底部部分暴露以促进与外部装置的电连接的方式封装模具和部分触点。密封剂用于在移除载体之后将触点保持在适当的位置。

3. 发明授权

US07598122B1 Die attach method and microarray leadframe structure 有权
标题翻译：贴片方法和微阵列引线框架结构
公开(公告)号：US07598122B1
公开(公告)日：2009-10-06
申请号：US11372481
申请日：2006-03-08
申请人： Jaime A. Bayan , Nghia Thuc Tu , Lim Fong , Chan Peng Yeen
发明人： Jaime A. Bayan , Nghia Thuc Tu , Lim Fong , Chan Peng Yeen
IPC分类号： H01L21/00
CPC分类号： H01L23/4951 , H01L21/4828 , H01L23/3107 , H01L23/49513 , H01L23/49541 , H01L24/48 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/73265 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In one aspect of the invention, a method of attaching a semiconductor die to a microarray leadframe is described. The method comprises stamping an adhesive onto discrete areas of the microarray leadframe using a multi-pronged stamp tool. The adhesive is applied to the leadframe as a series of dots, each dot corresponding to an associated prong of the stamping tool. In some embodiments the adhesive used to attach the semiconductor die to a leadframe is a black epoxy based adhesive material. In an apparatus aspect of the invention, lead traces in a microarray leadframe are arranged to have tails that extend beyond their associated contact posts on the side of the contact post that is opposite a wire bonding region such that such lead traces extends on two opposing sides of their associated contact posts. The tails do not attach to other structures within the lead frame (such as a die attach structure). The width of at least some of these tailed lead traces in a region that overlies their associated contact post is narrower than their associated contact post. Thus, these narrowed lead traces have extensions that extend beyond their associated contact posts. The extensions provide additional surface area that gives an adhesive applied to the narrowed lead trace (as for example by stamping) room to bleed (flow) along the top surface of the lead trace on both sides of the associated contact pad.
摘要翻译：在本发明的一个方面，描述了将半导体管芯附着到微阵列引线框架的方法。该方法包括使用多管齐下的印模工具将粘合剂冲压到微阵列引线框架的离散区域上。将粘合剂作为一系列点施加到引线框架，每个点对应于冲压工具的相关插脚。在一些实施例中，用于将半导体管芯附接到引线框架的粘合剂是黑色环氧基粘合剂材料。在本发明的装置方面，微阵列引线框架中的导线布置成具有延伸超出其在接触柱侧面的与引线接合区域相对的相关接触柱的尾部，使得这种引线迹线在两个相对侧上延伸的相关联系人员。尾部不附着到引线框架内的其他结构（如模具附接结构）。覆盖在其相关联的接触柱上的区域中的这些尾部引线的至少一些的宽度比其相关联的接触柱窄。因此，这些狭窄的引线迹线具有延伸超出其相关接触柱的延伸。这些延伸部分提供了额外的表面积，其给出了粘合剂施加到狭窄的引线迹线（例如通过冲压）沿着引线迹线的顶表面在相关接触焊盘的两侧上的流出（流动）。

4. 发明授权

US08293573B2 Microarray package with plated contact pedestals 有权
标题翻译：微阵列封装带电镀触点底座
公开(公告)号：US08293573B2
公开(公告)日：2012-10-23
申请号：US12688590
申请日：2010-01-15
申请人： Jaime A. Bayan , Nghia Thuc Tu
发明人： Jaime A. Bayan , Nghia Thuc Tu
IPC分类号： H01L21/00
CPC分类号： H01L23/49541 , H01L21/561 , H01L23/3107 , H01L23/49503 , H01L23/49548 , H01L23/49582 , H01L24/48 , H01L24/97 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/85 , H01L2224/83 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A microarray package includes a leadframe having an array of contact posts, a die carried by the lead frame, and a plurality of bonding wires that electrically connect the die to the lead frame. An encapsulant is included that encapsulates the die, the bonding wire and the leadframe while leaving the distal ends of the contact posts exposed and substantially co-planar with a bottom surface of the microarray package. A plurality of pedestal members is plated to the distal end of a respective contact pad. A distal surface of each pedestal member protrudes outwardly beyond the bottom surface of the microarray package in the range of about 15 μm to about 35 μm.
摘要翻译：微阵列封装包括具有接触柱阵列的引线框架，由引线框架承载的管芯，以及将管芯与引线框架电连接的多个接合线。包括密封剂，其封装模具，接合线和引线框架，同时使接触柱的远端暴露并基本上与微阵列封装的底表面共面。多个基座构件被电镀到相应接触垫的远端。每个基座构件的远侧表面在大约15μm至大约35μm的范围内向外突出超过微阵列封装的底表面。

5. 发明申请

US20110074003A1 FOIL BASED SEMICONDUCTOR PACKAGE 有权
标题翻译：基于FOIL的半导体封装
公开(公告)号：US20110074003A1
公开(公告)日：2011-03-31
申请号：US12571202
申请日：2009-09-30
申请人： Anindya PODDAR , Nghia Thuc TU , Jaime BAYAN , Will WONG , David CHIN
发明人： Anindya PODDAR , Nghia Thuc TU , Jaime BAYAN , Will WONG , David CHIN
IPC分类号： H01L23/28 , H01L21/56
CPC分类号： H01L23/3107 , H01L21/568 , H01L24/97 , H01L2224/16225 , H01L2224/97 , H01L2924/01029 , H01L2924/14 , H01L2224/81 , H01L2924/00
摘要： The present inventions relate to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One embodiment of the present invention involves attaching multiple dice to a foil carrier structure. The foil carrier structure is made of a thin foil that is bonded to a carrier. The dice and at least a portion of the metallic foil is then encapsulated with a molding material. The carrier is removed, leaving behind a molded foil structure. The exposed foil is patterned and etched using photolithographic techniques to define multiple device areas in the foil. Each device area includes multiple conductive lines. Afterwards, portions of the conductive lines are covered with a dielectric material and other portions are left exposed to define multiple bond pads in the device area. The molded foil structure can be singulated to form multiple integrated circuit packages.
摘要翻译：本发明涉及使用薄箔在集成电路封装中形成电互连的方法和布置。本发明的一个实施例涉及将多个骰子附接到箔片载体结构。箔载体结构由结合到载体的薄箔制成。然后将模具和至少一部分金属箔用模制材料包封。移除载体，留下模制的箔结构。使用光刻技术对暴露的箔进行图案化和蚀刻，以在箔中限定多个器件区域。每个设备区域包括多条导线。之后，导电线的一部分被电介质材料覆盖，并且其它部分被暴露以在器件区域中限定多个接合焊盘。模制的箔结构可以被单个化以形成多个集成电路封装。

6. 发明申请

US20110073481A1 FOIL PLATING FOR SEMICONDUCTOR PACKAGING 有权
标题翻译：用于半导体封装的FOIL镀层
公开(公告)号：US20110073481A1
公开(公告)日：2011-03-31
申请号：US12571223
申请日：2009-09-30
申请人： Jaime A. BAYAN , Nghia Thuc TU , Will K. WONG
发明人： Jaime A. BAYAN , Nghia Thuc TU , Will K. WONG
IPC分类号： C25D5/02 , C25D17/06
CPC分类号： C25D5/028 , C25D7/0635 , H01L23/49582 , H01L24/45 , H01L2224/45144 , H01L2224/48639 , H01L2224/85439 , H01L2924/00014 , H01L2924/14 , H01L2224/48 , H01L2924/00
摘要： Arrangements for plating a single surface of a thin foil are described. In one aspect, a metal foil is wrapped tightly at least partially around a plating solution drum. The drum is partially immersed in a plating solution such that the waterline of the metal plating solution is below a break point where the metallic foil strip begins to unwind from the plating solution drum. With this arrangement, one side of the metallic foil strip is exposed to the metal plating solution, while the opposing back side of the metallic foil strip does not come in substantial contact with the metal plating solution. In this manner, the exposed side of the foil is plated while the back surface of the foil is not plated. The drum may be rotated to convey the foil through the plating solution.
摘要翻译：描述了用于镀覆薄箔的单个表面的布置。在一个方面，金属箔至少部分地围绕电镀液桶包裹。将滚筒部分地浸入电镀溶液中，使得金属电镀溶液的水线低于金属箔带开始从电镀液滚筒放卷的断点。通过这种布置，金属箔条的一侧暴露于金属电镀液中，而金属箔带的相反背面不与金属电镀液基本接触。以这种方式，箔的暴露面被镀覆，而箔的背面不被镀覆。滚筒可以旋转以将箔传送通过电镀溶液。

7. 发明授权

US08375577B2 Method of making foil based semiconductor package 有权
标题翻译：制造箔基半导体封装的方法
公开(公告)号：US08375577B2
公开(公告)日：2013-02-19
申请号：US12133335
申请日：2008-06-04
申请人： Will Wong , Nghia Thuc Tu , Jaime Bayan , David Chin
发明人： Will Wong , Nghia Thuc Tu , Jaime Bayan , David Chin
IPC分类号： H01L21/60 , H01L23/495
CPC分类号： H01L23/49582 , H01L21/568 , H01L21/6835 , H01L23/3107 , H01L23/544 , H01L24/29 , H01L24/48 , H01L24/83 , H01L24/85 , H01L24/97 , H01L2221/68345 , H01L2221/68377 , H01L2223/5442 , H01L2223/54426 , H01L2223/54473 , H01L2224/48091 , H01L2224/48247 , H01L2224/83192 , H01L2224/83801 , H01L2224/85001 , H01L2224/85205 , H01L2224/85439 , H01L2224/85455 , H01L2224/85464 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , Y10T29/49121 , Y10T29/49126 , Y10T29/49146 , Y10T29/49156 , Y10T428/12438 , H01L2224/85 , H01L2224/78 , H01L2924/00 , H01L2224/45099 , H01L2224/83205 , H01L2924/00012
摘要： The present inventions relate to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. In one embodiment, a foil carrier structure is formed by ultrasonically bonding portions of a conductive foil to a metallic carrier. The bonded portions define panels in the foil carrier structure. In some embodiments, the foil carrier structure is cut to form multiple isolated panels that are sealed along their peripheries. Each isolated panel may be approximately the size of a conventional leadframe strip or panel. As a result, existing packaging equipment may be used to add dice, bonding wires and molding material to the panel. The ultrasonic welding helps prevent unwanted substances from penetrating the foil carrier structure during such processing steps. After the carrier portion of the molded foil carrier structure is removed, the structure is singulated into integrated circuit packages. Some embodiments relate to methods that utilize some or all of the aforementioned operations. Other embodiments relate to arrangements used in the above processes.
摘要翻译：本发明涉及使用薄箔在集成电路封装中形成电互连的方法和布置。在一个实施例中，通过将导电箔的部分超声波结合到金属载体上来形成箔载体结构。接合部分限定箔载体结构中的面板。在一些实施例中，切割箔载体结构以形成沿其周边密封的多个隔离板。每个隔离的面板可以是常规引线框条或面板的尺寸。因此，可以使用现有的包装设备将骰子，接合线和模制材料添加到面板。超声波焊接有助于防止在这种加工步骤期间不需要的物质渗透到箔片载体结构。在模制的箔载体结构的载体部分被去除之后，将结构分成集成电路封装。一些实施例涉及利用上述操作中的一些或全部的方法。其他实施例涉及上述方法中使用的布置。

8. 发明授权

US08101470B2 Foil based semiconductor package 有权
标题翻译：箔基半导体封装
公开(公告)号：US08101470B2
公开(公告)日：2012-01-24
申请号：US12571202
申请日：2009-09-30
申请人： Anindya Poddar , Nghia Thuc Tu , Jaime Bayan , Will Wong , David Chin
发明人： Anindya Poddar , Nghia Thuc Tu , Jaime Bayan , Will Wong , David Chin
IPC分类号： H01L23/28 , H01L21/56
CPC分类号： H01L23/3107 , H01L21/568 , H01L24/97 , H01L2224/16225 , H01L2224/97 , H01L2924/01029 , H01L2924/14 , H01L2224/81 , H01L2924/00
摘要： The present inventions relate to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One embodiment of the present invention involves attaching multiple dice to a foil carrier structure. The foil carrier structure is made of a thin foil that is bonded to a carrier. The dice and at least a portion of the metallic foil is then encapsulated with a molding material. The carrier is removed, leaving behind a molded foil structure. The exposed foil is patterned and etched using photolithographic techniques to define multiple device areas in the foil. Each device area includes multiple conductive lines. Afterwards, portions of the conductive lines are covered with a dielectric material and other portions are left exposed to define multiple bond pads in the device area. The molded foil structure can be singulated to form multiple integrated circuit packages.
摘要翻译：本发明涉及使用薄箔在集成电路封装中形成电互连的方法和布置。本发明的一个实施例涉及将多个骰子附接到箔片载体结构。箔载体结构由结合到载体的薄箔制成。然后将模具和至少一部分金属箔用模制材料包封。移除载体，留下模制的箔结构。使用光刻技术对暴露的箔进行图案化和蚀刻，以在箔中限定多个器件区域。每个设备区域包括多条导线。之后，导电线的一部分被电介质材料覆盖，并且其它部分被暴露以在器件区域中限定多个接合焊盘。模制的箔结构可以被单个化以形成多个集成电路封装。

9. 发明授权

US07893523B2 Microarray package with plated contact pedestals 有权
标题翻译：微阵列封装带电镀触点底座
公开(公告)号：US07893523B2
公开(公告)日：2011-02-22
申请号：US12688597
申请日：2010-01-15
申请人： Jaime A. Bayan , Nghia Thuc Tu
发明人： Jaime A. Bayan , Nghia Thuc Tu
IPC分类号： H01L23/495
CPC分类号： H01L23/49541 , H01L21/561 , H01L23/3107 , H01L23/49503 , H01L23/49548 , H01L23/49582 , H01L24/48 , H01L24/97 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/85 , H01L2224/83 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A microarray package includes a leadframe having an array of contact posts, a die carried by the lead frame, and a plurality of bonding wires that electrically connect the die to the lead frame. An encapsulant is included that encapsulates the die, the bonding wire and the leadframe while leaving the distal ends of the contact posts exposed and substantially co-planar with a bottom surface of the microarray package. A plurality of pedestal members is plated to the distal end of a respective contact pad. A distal surface of each pedestal member protrudes outwardly beyond the bottom surface of the microarray package in the range of about 15 μm to about 35 μm.
摘要翻译：微阵列封装包括具有接触柱阵列的引线框架，由引线框架承载的管芯，以及将管芯与引线框架电连接的多个接合线。包括密封剂，其封装模具，接合线和引线框架，同时使接触柱的远端暴露并基本上与微阵列封装的底表面共面。多个基座构件被电镀到相应接触垫的远端。每个基座构件的远侧表面在大约15μm至大约35μm的范围内向外突出超过微阵列封装的底表面。

10. 发明申请

US20100046188A1 THIN FOIL SEMICONDUCTOR PACKAGE 有权
标题翻译：薄箔半导体封装
公开(公告)号：US20100046188A1
公开(公告)日：2010-02-25
申请号：US12195704
申请日：2008-08-21
申请人： Jaime A. BAYAN , Nghia Thuc TU , Will Kiang WONG , David CHIN
发明人： Jaime A. BAYAN , Nghia Thuc TU , Will Kiang WONG , David CHIN
IPC分类号： H05K7/02 , H01L21/50
CPC分类号： H01L21/4832 , H01L21/4842 , H01L21/568 , H01L23/3107 , H01L23/49517 , H01L23/49582 , H01L24/48 , H01L2224/451 , H01L2224/48091 , H01L2224/48247 , H01L2224/85464 , H01L2924/00014 , H01L2924/01046 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , Y10T29/49146 , Y10T29/53174 , Y10T29/53178 , Y10T29/53183 , Y10T29/532 , H01L2924/00 , H01L2224/05599 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One such arrangement involves a foil carrier structure, which includes a foil adhered to a carrier having cavities. Some methods of the present invention involve attaching dice to the foil and encapsulating the foil carrier structure in a molding material. In one embodiment, the molding material presses against the foil, which causes portions of the foil to distend into the cavities of the carrier. As a result, recessed and raised areas are formed in the foil. Afterwards, the carrier is removed and portions of the raised areas in the foil are removed through one of a variety of techniques, such as grinding. This process helps define and electrical isolate contact pads in the foil. The resulting molded foil structure may then be singulated into multiple semiconductor packages.
摘要翻译：本发明涉及在集成电路封装中使用薄箔来形成电互连的方法和装置。一种这样的布置涉及箔载体结构，其包括粘附到具有空腔的载体的箔。本发明的一些方法涉及将骰子附接到箔并将箔载体结构封装在模制材料中。在一个实施例中，模制材料压靠箔，这使得箔的一部分膨胀到载体的空腔中。结果，在箔中形成凹凸区域。之后，移除载体，并通过各种技术如研磨来去除箔中的部分凸起区域。该过程有助于限定和电隔离箔中的接触垫。然后将所得的模制箔结构分成多个半导体封装。

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