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1. 发明授权

US5568651A Method for detection of configuration types and addressing modes of a dynamic RAM 失效
标题翻译：用于检测动态RAM的配置类型和寻址模式的方法
公开(公告)号：US5568651A
公开(公告)日：1996-10-22
申请号：US333809
申请日：1994-11-03
申请人： Eitan Medina , Simoni Ben-Michael , Yifat Ben-Shahar , Niamh Darcy
发明人： Eitan Medina , Simoni Ben-Michael , Yifat Ben-Shahar , Niamh Darcy
IPC分类号： G06F12/06 , H04L12/56 , H04Q11/04 , G06F13/00 , H04L12/28
CPC分类号： G06F12/0684 , H04Q11/0478 , H04L2012/5616 , H04L2012/5681
摘要： A method providing automating detection of configuration between an adapter device and a DRAM device. Such a method a determines, in the adapter memory, the DRAM configuration, making it easier to change DRAM configuration in an existing board without the need to modify configuration pins in the existing board. A method for determining a configuration type in an Asynchronous Transfer Mode (ATM) communications network comprising the steps of providing an ATM adapter, the ATM adapter having an ATM adapter memory, providing a DRAM device, the DRAM device having a DRAM configuration, providing a link to connect the ATM adapter and the DRAM device, assuming, in the ATM adapter memory, a first DRAM configuration, verifying the step of assuming, and repeating the steps of assuming and verifying until the first DRAM configuration is determined.
摘要翻译：一种提供在适配器装置和DRAM装置之间自动检测配置的方法。这种方法a在适配器存储器中确定DRAM配置，使得更容易地改变现有板中的DRAM配置，而不需要修改现有板中的配置引脚。一种用于确定异步传输模式（ATM）通信网络中的配置类型的方法，包括以下步骤：提供ATM适配器，所述ATM适配器具有ATM适配器存储器，提供DRAM设备，所述DRAM设备具有DRAM配置，链接以连接ATM适配器和DRAM设备，假设在ATM适配器存储器中，第一DRAM配置，验证假设的步骤，并且重复假定和验证的步骤直到确定第一DRAM配置。

2. 发明授权

US5568470A Method for controlled-latency transfer of transmitt ATM traffic and synchronous feedback over a physical interface 失效
标题翻译：通过物理接口传输ATM业务和同步反馈的受控延迟传输方法
公开(公告)号：US5568470A
公开(公告)日：1996-10-22
申请号：US430945
申请日：1995-04-28
申请人： Michael Ben-Nun , Winthrop J. Wu , Niamh Darcy
发明人： Michael Ben-Nun , Winthrop J. Wu , Niamh Darcy
IPC分类号： H04L12/56 , H04Q11/04 , H04L12/54
CPC分类号： H04Q11/0478 , H04L2012/5615 , H04L2012/563 , H04L2012/5647 , H04L2012/5674 , H04L2012/5681
摘要： In an asynchronous transfer mode (ATM) endnode a method is provided by which ATM cells can experience a small delay from the ATM layer to the PHY layer to transmission on the ATM network. Such an arrangement includes providing the endnode with an ATM layer, the ATM layer having a first-in-first-out (FIFO) queue for transmitting transmit ATM traffic, providing the endnode with a PHY layer, the PHY layer having a FIFO queue for receiving the transmit ATM traffic, providing an interface between the FIFO queue of the ATM layer and the FIFO queue of the PHY layer for the flow of the transmit ATM traffic, providing a signal in the ATM endnode, providing a state machine in the ATM endnode, the state machine monitoring the signal in the ATM endnode, stalling the transfer of the transmit ATM traffic from the FIFO of the ATM layer to the FIFO of the PHY layer over the interface when the signal and the state machine indicate that the FIFO of the PHY layer is full, and transmitting the transmit ATM traffic from the FIFO of the ATM layer to the FIFO of the PHY over the interface. By causing the ATM layer to generate/transfer a continuous stream of cells to the PHY layer, the method can provide cell time indications to allow the ATM layer to synchronize itself to the network.
摘要翻译：在异步传输模式（ATM）终端中，提供了一种方法，由ATM信元可以经历从ATM层到PHY层的小延迟到ATM网络上的传输。这种布置包括向终端提供ATM层，ATM层具有用于发送ATM业务的先入先出（FIFO）队列，为终端提供PHY层，PHY层具有用于接收发送ATM业务，在ATM层的FIFO队列与PHY层的FIFO队列之间提供用于发送ATM业务流的接口，在ATM端节点提供信号，在ATM终端中提供状态机状态机监视ATM端节点中的信号，当信号和状态机指示FIFO的FIFO为止时，阻止将传输ATM业务从ATM层的FIFO传输到PHY层的FIFO PHY层已满，并通过接口从ATM层的FIFO发送ATM流量到PHY的FIFO。通过使ATM层生成/传送连续的小区流到PHY层，该方法可以提供小区时间指示，以允许ATM层将其自身同步到网络。

3. 发明授权

US5319678A Clocking system for asynchronous operations 失效
标题翻译：用于异步操作的时钟系统
公开(公告)号：US5319678A
公开(公告)日：1994-06-07
申请号：US854519
申请日：1992-03-20
申请人： Steven Ho , Niamh Darcy
发明人： Steven Ho , Niamh Darcy
IPC分类号： G06F13/42 , H04L7/02 , H04L7/00
CPC分类号： G06F13/4217 , H04L7/02
摘要： A clock mechanism in modules connected to a bus over which asynchronous operations are performed wherein clock pulses are generated that can clock the transmission or capture of data and the transitioning of acknowledge or synchronization lines. Each clock mechanism generates its clock pulses based on the receipt of signals associated with synchronization or acknowledge bus lines. The clock mechanism includes a multiplexer which provides to a resettable latch a signal associated with the condition of the selected line. The resettable latch, in conjunction with a delay element produces the clock pulses.
摘要翻译：连接到总线的模块中的时钟机制，在其上执行异步操作，其中产生时钟脉冲，其可以对数据的传输或捕获进行定时以及确认或同步线的转换。每个时钟机制基于与同步或确认总线相关联的信号的接收来产生其时钟脉冲。时钟机构包括多路复用器，其向可重置锁存器提供与所选行的条件相关联的信号。可复位锁存器与延迟元件一起产生时钟脉冲。

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