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1. 发明申请

US20090006662A1 OPTIMIZED COLLECTIVES USING A DMA ON A PARALLEL COMPUTER 有权
标题翻译：使用并行计算机上的DMA的优化收集器
公开(公告)号：US20090006662A1
公开(公告)日：2009-01-01
申请号：US11768645
申请日：2007-06-26
申请人： Dong Chen , Dozsa Gabor , Mark E. Giampapa , Phillip Heidelberger
发明人： Dong Chen , Dozsa Gabor , Mark E. Giampapa , Phillip Heidelberger
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Optimizing collective operations using direct memory access controller on a parallel computer, in one aspect, may comprise establishing a byte counter associated with a direct memory access controller for each submessage in a message. The byte counter includes at least a base address of memory and a byte count associated with a submessage. A byte counter associated with a submessage is monitored to determine whether at least a block of data of the submessage has been received. The block of data has a predetermined size, for example, a number of bytes. The block is processed when the block has been fully received, for example, when the byte count indicates all bytes of the block have been received. The monitoring and processing may continue for all blocks in all submessages in the message.
摘要翻译：在一个方面，在并行计算机上优化使用直接存储器访问控制器的集合操作可以包括建立与消息中的每个子消息的直接存储器访问控制器相关联的字节计数器。字节计数器至少包括存储器的基地址和与子消息相关联的字节计数。监视与子消息相关联的字节计数器，以确定是否已经接收到子消息的至少一个数据块。数据块具有预定的大小，例如，多个字节。当块完全接收时，块被处理，例如，当字节计数指示已经接收到块的所有字节时。消息中的所有子消息中的所有块的监视和处理可以继续。

2. 发明授权

US08161248B2 Simplifying and speeding the management of intra-node cache coherence 失效
标题翻译：简化和加快节点内缓存一致性管理
公开(公告)号：US08161248B2
公开(公告)日：2012-04-17
申请号：US12953770
申请日：2010-11-24
申请人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Phillip Heidelberger , Dirk Hoenicke , Martin Ohmacht
发明人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Phillip Heidelberger , Dirk Hoenicke , Martin Ohmacht
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F15/167
CPC分类号： H05K7/20836 , F24F11/77 , G06F9/52 , G06F9/526 , G06F15/17381 , G06F17/142 , G09G5/008 , H04L7/0338
摘要： A method and apparatus for managing coherence between two processors of a two processor node of a multi-processor computer system. Generally the present invention relates to a software algorithm that simplifies and significantly speeds the management of cache coherence in a message passing parallel computer, and to hardware apparatus that assists this cache coherence algorithm. The software algorithm uses the opening and closing of put/get windows to coordinate the activated required to achieve cache coherence. The hardware apparatus may be an extension to the hardware address decode, that creates, in the physical memory address space of the node, an area of virtual memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements.
摘要翻译：一种用于管理多处理器计算机系统的两个处理器节点的两个处理器之间的相干性的方法和装置。通常，本发明涉及一种软件算法，其简化并显着加速了传送并行计算机的消息中的高速缓存一致性的管理以及辅助该高速缓存一致性算法的硬件设备。软件算法使用put / get窗口的打开和关闭来协调激活的所需要的，以实现缓存一致性。硬件设备可以是硬件地址解码的扩展，其在节点的物理存储器地址空间中创建（a）实际不存在的虚拟存储器的区域，并且（b）因此能够立即响应从处理元素读取和写入请求。

3. 发明授权

US07886084B2 Optimized collectives using a DMA on a parallel computer 有权
标题翻译：在并行计算机上使用DMA优化集合
公开(公告)号：US07886084B2
公开(公告)日：2011-02-08
申请号：US11768645
申请日：2007-06-26
申请人： Dong Chen , Dozsa Gabor , Mark E. Giampapa , Phillip Heidelberger
发明人： Dong Chen , Dozsa Gabor , Mark E. Giampapa , Phillip Heidelberger
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/28
摘要： Optimizing collective operations using direct memory access controller on a parallel computer, in one aspect, may comprise establishing a byte counter associated with a direct memory access controller for each submessage in a message. The byte counter includes at least a base address of memory and a byte count associated with a submessage. A byte counter associated with a submessage is monitored to determine whether at least a block of data of the submessage has been received. The block of data has a predetermined size, for example, a number of bytes. The block is processed when the block has been fully received, for example, when the byte count indicates all bytes of the block have been received. The monitoring and processing may continue for all blocks in all submessages in the message.
摘要翻译：在一个方面，在并行计算机上优化使用直接存储器访问控制器的集合操作可以包括建立与消息中的每个子消息的直接存储器访问控制器相关联的字节计数器。字节计数器至少包括存储器的基地址和与子消息相关联的字节计数。监视与子消息相关联的字节计数器，以确定是否已经接收到子消息的至少一个数据块。数据块具有预定的大小，例如，多个字节。当块完全接收时，块被处理，例如，当字节计数指示已经接收到块的所有字节时。消息中的所有子消息中的所有块的监视和处理可以继续。

4. 发明授权

US08509255B2 Hardware packet pacing using a DMA in a parallel computer 有权
标题翻译：在并行计算机中使用DMA的硬件包起搏
公开(公告)号：US08509255B2
公开(公告)日：2013-08-13
申请号：US11768682
申请日：2007-06-26
申请人： Dong Chen , Phillip Heidelberger , Pavlos Vranas
发明人： Dong Chen , Phillip Heidelberger , Pavlos Vranas
IPC分类号： H04L12/28
CPC分类号： G06F13/128
摘要： Method and system for hardware packet pacing using a direct memory access controller in a parallel computer which, in one aspect, keeps track of a total number of bytes put on the network as a result of a remote get operation, using a hardware token counter.
摘要翻译：使用并行计算机中的直接存储器访问控制器的硬件分组起搏的方法和系统，其在一个方面使用硬件令牌计数器来跟踪作为远程获取操作的结果在网络上的总字节数。

5. 发明申请

US20110072219A1 MANAGING COHERENCE VIA PUT/GET WINDOWS 失效
标题翻译：通过输入/获取窗口管理相关性
公开(公告)号：US20110072219A1
公开(公告)日：2011-03-24
申请号：US12953770
申请日：2010-11-24
申请人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Phillip Heidelberger , Dirk Hoenicke , Martin Ohmacht
发明人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Phillip Heidelberger , Dirk Hoenicke , Martin Ohmacht
IPC分类号： G06F12/08
CPC分类号： H05K7/20836 , F24F11/77 , G06F9/52 , G06F9/526 , G06F15/17381 , G06F17/142 , G09G5/008 , H04L7/0338
摘要： A method and apparatus for managing coherence between two processors of a two processor node of a multi-processor computer system. Generally the present invention relates to a software algorithm that simplifies and significantly speeds the management of cache coherence in a message passing parallel computer, and to hardware apparatus that assists this cache coherence algorithm. The software algorithm uses the opening and closing of put/get windows to coordinate the activated required to achieve cache coherence. The hardware apparatus may be an extension to the hardware address decode, that creates, in the physical memory address space of the node, an area of virtual memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements.
摘要翻译：一种用于管理多处理器计算机系统的两个处理器节点的两个处理器之间的相干性的方法和装置。通常，本发明涉及一种软件算法，其简化并显着加速了传送并行计算机的消息中的高速缓存一致性的管理以及辅助该高速缓存一致性算法的硬件设备。软件算法使用put / get窗口的打开和关闭来协调激活的所需要的，以实现缓存一致性。硬件设备可以是硬件地址解码的扩展，其在节点的物理存储器地址空间中创建（a）实际不存在的虚拟存储器的区域，并且（b）因此能够立即响应从处理元素读取和写入请求。

6. 发明申请

US20090003228A1 BAD DATA PACKET CAPTURE DEVICE 失效
标题翻译：坏数据包捕获设备
公开(公告)号：US20090003228A1
公开(公告)日：2009-01-01
申请号：US11768572
申请日：2007-06-26
申请人： Dong Chen , Alan Gara , Phillip Heidelberger , Pavlos Vranas
发明人： Dong Chen , Alan Gara , Phillip Heidelberger , Pavlos Vranas
IPC分类号： H04L12/56
CPC分类号： H04L43/0847
摘要： An apparatus and method for capturing data packets for analysis on a network computing system includes a sending node and a receiving node connected by a bi-directional communication link. The sending node sends a data transmission to the receiving node on the bi-directional communication link, and the receiving node receives the data transmission and verifies the data transmission to determine valid data and invalid data and verify retransmissions of invalid data as corresponding valid data. A memory device communicates with the receiving node for storing the invalid data and the corresponding valid data. A computing node communicates with the memory device and receives and performs an analysis of the invalid data and the corresponding valid data received from the memory device.
摘要翻译：用于捕获数据分组以用于在网络计算系统上进行分析的装置和方法包括通过双向通信链路连接的发送节点和接收节点。发送节点向双向通信链路上的接收节点发送数据传输，接收节点接收数据传输，验证数据传输，确定有效数据和无效数据，并验证无效数据的重传是对应的有效数据。存储装置与接收节点进行通信，用于存储无效数据和对应的有效数据。计算节点与存储器件进行通信，并且接收并执行从存储器件接收的无效数据和对应的有效数据的分析。

7. 发明申请

US20090003203A1 HARDWARE PACKET PACING USING A DMA IN A PARALLEL COMPUTER 有权
标题翻译：使用并行计算机中的DMA的硬件分组
公开(公告)号：US20090003203A1
公开(公告)日：2009-01-01
申请号：US11768682
申请日：2007-06-26
申请人： Dong Chen , Phillip Heidelberger , Pavlos Vranas
发明人： Dong Chen , Phillip Heidelberger , Pavlos Vranas
IPC分类号： H04L1/00
CPC分类号： G06F13/128
摘要： Method and system for hardware packet pacing using a direct memory access controller in a parallel, in one aspect, keeps track of a total number of bytes put on the network as a result of a remote get operation, using a hardware token counter. A remote get message is sent as a plurality of sub remote get packets. Each of the sub remote get packets is sent if the total number of bytes put on the network does not exceed a predetermined number.
摘要翻译：在一方面，使用直接存储器访问控制器并行地进行硬件分组起搏的方法和系统，使用硬件令牌计数器来跟踪作为远程获取操作的结果在网络上的总字节数。作为多个子远程获取分组发送远程获取消息。如果网络上的总字节数不超过预定数量，则发送每个子远程获取数据包。

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