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1. 发明申请

US20120304020A1 SHARED PERFORMANCE MONITOR IN A MULTIPROCESSOR SYSTEM 有权
标题翻译：多处理器系统中的共享性能监视器
公开(公告)号：US20120304020A1
公开(公告)日：2012-11-29
申请号：US13484797
申请日：2012-05-31
申请人： George Chiu , Alan G. Gara , Valentina Salapura
发明人： George Chiu , Alan G. Gara , Valentina Salapura
IPC分类号： G06F11/34
CPC分类号： G06F11/348 , G06F11/3409 , G06F2201/86 , G06F2201/88 , Y02D10/34
摘要： A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU is further programmed to monitor event signals issued from non-processor devices.
摘要翻译：用于监视在多处理器系统中发生的事件的性能的性能监视单元（PMU）和方法。多处理器系统包括多个处理器设备单元，用于产生表示处理器设备中事件发生的信号的每个处理器设备，以及用于性能监控的单个共享计数器资源。性能监视器单元由多处理器系统中的所有处理器核共享。 PMU进一步被编程为监视从非处理器设备发出的事件信号。

2. 发明授权

US08010875B2 Error correcting code with chip kill capability and power saving enhancement 有权
标题翻译：错误纠正代码具有芯片杀死能力和节能增强
公开(公告)号：US08010875B2
公开(公告)日：2011-08-30
申请号：US11768559
申请日：2007-06-26
申请人： Alan G. Gara , Dong Chen , Paul W. Coteus , William T. Flynn , James A. Marcella , Todd Takken , Barry M. Trager , Shmuel Winograd
发明人： Alan G. Gara , Dong Chen , Paul W. Coteus , William T. Flynn , James A. Marcella , Todd Takken , Barry M. Trager , Shmuel Winograd
IPC分类号： G06F11/10
CPC分类号： G06F11/1012
摘要： A method and system are disclosed for detecting memory chip failure in a computer memory system. The method comprises the steps of accessing user data from a set of user data chips, and testing the user data for errors using data from a set of system data chips. This testing is done by generating a sequence of check symbols from the user data, grouping the user data into a sequence of data symbols, and computing a specified sequence of syndromes. If all the syndromes are zero, the user data has no errors. If one of the syndromes is non-zero, then a set of discriminator expressions are computed, and used to determine whether a single or double symbol error has occurred. In the preferred embodiment, less than two full system data chips are used for testing and correcting the user data.
摘要翻译：公开了一种用于检测计算机存储器系统中的存储器芯片故障的方法和系统。该方法包括以下步骤：从一组用户数据芯片访问用户数据，以及使用来自一组系统数据芯片的数据来测试用户数据的错误。该测试通过从用户数据生成检查符号序列来完成，将用户数据分组成数据符号序列，并计算指定的综合征序列。如果所有的综合征为零，则用户数据没有错误。如果其中一个校正子不为零，则计算一组鉴别符表达式，并用于确定是否发生单个或双重符号错误。在优选实施例中，使用少于两个全系统数据芯片来测试和校正用户数据。

3. 发明授权

US07650434B2 Global tree network for computing structures enabling global processing operations 失效
标题翻译：用于计算结构的全局树网络，实现全球处理操作
公开(公告)号：US07650434B2
公开(公告)日：2010-01-19
申请号：US10469000
申请日：2002-02-25
申请人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Burkhard D. Steinmacher-Burow , Todd E. Takken , Pavlos M. Vranas
发明人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Burkhard D. Steinmacher-Burow , Todd E. Takken , Pavlos M. Vranas
IPC分类号： G06F15/16
CPC分类号： G06F15/17337
摘要： A system and method for enabling high-speed, low-latency global tree network communications among processing nodes interconnected according to a tree network structure. The global tree network enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the tree via links to facilitate performance of low-latency global processing operations at nodes of the virtual tree and sub-tree structures. The global operations performed include one or more of: broadcast operations downstream from a root node to leaf nodes of a virtual tree, reduction operations upstream from leaf nodes to the root node in the virtual tree, and point-to-point message passing from any node to the root node. The global tree network is configurable to provide global barrier and interrupt functionality in asynchronous or synchronized manner, and, is physically and logically partitionable.
摘要翻译：一种用于根据树网络结构互连的处理节点之间实现高速，低延迟的全局树网络通信的系统和方法。全局树网络使得能够在具有多个互连的处理节点的计算机结构中执行并行算法操作期间执行集合缩减操作。包括通过链路互连树节点的路由器设备，以便于在虚拟树和子树结构的节点处执行低延迟全局处理操作。执行的全局操作包括以下一个或多个：从根节点向下游到虚拟树的叶节点的广播操作，从叶节点向上到叶节点到虚拟树中的根节点的减少操作，以及从任何节点到根节点。全局树网络可配置为以异步或同步方式提供全局屏障和中断功能，并且在物理和逻辑上可分区。

4. 发明授权

US07617366B2 Method and apparatus for filtering snoop requests using mulitiple snoop caches 失效
标题翻译：使用多播监听高速缓存来过滤窥探请求的方法和装置
公开(公告)号：US07617366B2
公开(公告)日：2009-11-10
申请号：US12113756
申请日：2008-05-01
申请人： Matthias A. Blumrich , Alan G. Gara , Mark E. Giampapa , Martin Ohmacht , Valentina Salapura
发明人： Matthias A. Blumrich , Alan G. Gara , Mark E. Giampapa , Martin Ohmacht , Valentina Salapura
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F12/0822 , G06F12/0831
摘要： A method and apparatus for detecting a cache wrap condition in a computing environment having a processor and a cache. A cache wrap condition is detected when the entire contents of a cache have been replaced, relative to a particular starting state. A set-associative cache is considered to have wrapped when all of the sets within the cache have been replaced. The starting point for cache wrap detection is the state of the cache sets at the time of the previous cache wrap. The method and apparatus is preferably implemented in a snoop filter having filter mechanisms that rely upon detecting the cache wrap condition. These snoop filter mechanisms requiring this information are operatively coupled with cache wrap detection logic adapted to detect the cache wrap event, and perform an indication step to the snoop filter mechanisms. In the various embodiments, cache wrap detection logic is implemented using registers and comparators, loadable counters, or a scoreboard data structure.
摘要翻译：一种用于在具有处理器和高速缓存的计算环境中检测高速缓存包装条件的方法和装置。当高速缓存的全部内容相对于特定的启动状态被替换时，检测到缓存包装条件。当缓存中的所有集合已被替换时，集合关联缓存被认为已被包装。高速缓存包检测的起始点是先前高速缓存包装时高速缓存集的状态。该方法和装置优选地在具有依赖于检测高速缓存包装条件的过滤机构的窥探过滤器中实现。这些需要该信息的窥探过滤机构可操作地与适用于检测高速缓存包裹事件的高速缓存包检测逻辑耦合，并且向窥探过滤机构执行指示步骤。在各种实施例中，使用寄存器和比较器，可加载计数器或记分板数据结构来实现高速缓存封包检测逻辑。

5. 发明授权

US07587516B2 Class network routing 失效
标题翻译：类网络路由
公开(公告)号：US07587516B2
公开(公告)日：2009-09-08
申请号：US10468999
申请日：2002-02-25
申请人： Gyan Bhanot , Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Burkhard D. Steinmacher-Burow , Todd E. Takken , Pavlos M. Vranas
发明人： Gyan Bhanot , Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Burkhard D. Steinmacher-Burow , Todd E. Takken , Pavlos M. Vranas
IPC分类号： G06F15/173 , H04L12/66 , H04L12/50
CPC分类号： H04L45/16 , H04L45/06
摘要： Class network routing is implemented in a network such as a computer network comprising a plurality of parallel compute processors at nodes thereof. Class network routing allows a compute processor to broadcast a message to a range (one or more) of other compute processors in the computer network, such as processors in a column or a row. Normally this type of operation requires a separate message to be sent to each processor. With class network routing pursuant to the invention, a single message is sufficient, which generally reduces the total number of messages in the network as well as the latency to do a broadcast. Class network routing is also applied to dense matrix inversion algorithms on distributed memory parallel supercomputers with hardware class function (multicast) capability. This is achieved by exploiting the fact that the communication patterns of dense matrix inversion can be served by hardware class functions, which results in faster execution times.
摘要翻译：在诸如包括在其节点处的多个并行计算处理器的计算机网络的网络中实现类网络路由。类网络路由允许计算处理器将消息广播到计算机网络中的其他计算处理器的范围（一个或多个），例如列或行中的处理器。通常这种类型的操作需要单独的消息发送到每个处理器。根据本发明的类网络路由，单个消息是足够的，这通常减少了网络中的消息总数以及进行广播的延迟。类网络路由也适用于具有硬件类功能（组播）能力的分布式存储并行超级计算机上的密集矩阵求逆算法。这是通过利用密集矩阵反演的通信模式可以通过硬件类功能来实现的，这导致更快的执行时间。

6. 发明申请

US20090006923A1 COMBINED GROUP ECC PROTECTION AND SUBGROUP PARITY PROTECTION 有权
标题翻译：组合群组保护和子群保障
公开(公告)号：US20090006923A1
公开(公告)日：2009-01-01
申请号：US11768527
申请日：2007-06-26
申请人： Alan G. Gara , Dong Chen , Philip Heidelberger , Martin Ohmacht
发明人： Alan G. Gara , Dong Chen , Philip Heidelberger , Martin Ohmacht
IPC分类号： H03M13/00
CPC分类号： G06F11/1076 , G06F11/1064 , G06F2212/403 , H03M1/0687 , H03M13/13 , H03M13/2707 , H03M13/271 , H03M13/29 , H03M13/616
摘要： A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P.
摘要翻译：公开了用于为给定的n位组提供组合的错误代码保护和子组奇偶校验保护的方法和系统。该方法包括以下步骤：识别用于所述错误保护的冗余位的数量m; 并且构造矩阵P，其中将所述给定的n个比特组与P相乘产生m个冗余纠错码（ECC）保护比特，并且两列P为所述给定组n比特的子组提供奇偶校验保护。在本发明的优选实施例中，矩阵P是通过产生具有三个或更多个奇数个元素的m位宽向量的排列而构成的，其中值为1的元素和其他元素的值为零; 并将所述向量分配给矩阵P的行。

7. 发明申请

US20080263280A1 LOW COMPLEXITY SPECULATIVE MULTITHREADING SYSTEM BASED ON UNMODIFIED MICROPROCESSOR CORE 有权
标题翻译：基于未修改的微处理器核心的低复杂度测量多路复用系统
公开(公告)号：US20080263280A1
公开(公告)日：2008-10-23
申请号：US12147914
申请日：2008-06-27
申请人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
发明人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F9/3828 , G06F9/3842 , G06F9/3851 , G06F12/0815 , G06F2212/507
摘要： A system, method and computer program product for supporting thread level speculative execution in a computing environment having multiple processing units adapted for concurrent execution of threads in speculative and non-speculative modes. Each processing unit includes a cache memory hierarchy of caches operatively connected therewith. The apparatus includes an additional cache level local to each processing unit for use only in a thread level speculation mode, each additional cache for storing speculative results and status associated with its associated processor when handling speculative threads. The additional local cache level at each processing unit are interconnected so that speculative values and control data may be forwarded between parallel executing threads. A control implementation is provided that enables speculative coherence between speculative threads executing in the computing environment.
摘要翻译：一种用于在具有多个处理单元的计算环境中支持线程级推测性执行的系统，方法和计算机程序产品，该处理单元适于以推测和非推测模式并行执行线程。每个处理单元包括与其可操作地连接的高速缓存的高速缓冲存储器层级。该装置包括仅在线程级推测模式中使用的每个处理单元本地的附加高速缓存级别，每个附加高速缓存用于存储推测结果以及处理推测性线程时与其相关联的处理器相关联的状态。在每个处理单元处的附加本地高速缓存级别互连，使得推测值和控制数据可以在并行执行线程之间转发。提供了一种控制实现，其实现在计算环境中执行的推测线程之间的推测性一致性。

8. 发明授权

US07426253B2 Low latency counter event indication 有权
标题翻译：低延迟计数器事件指示
公开(公告)号：US07426253B2
公开(公告)日：2008-09-16
申请号：US11507308
申请日：2006-08-21
申请人： Alan G. Gara , Valentina Salapura
发明人： Alan G. Gara , Valentina Salapura
IPC分类号： G06M3/00
CPC分类号： H03K23/54
摘要： A hybrid counter array device for counting events with interrupt indication includes a first counter portion comprising N counter devices, each for counting signals representing event occurrences and providing a first count value representing lower order bits. An overflow bit device associated with each respective counter device is additionally set in response to an overflow condition. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits. An operatively coupled control device monitors each associated overflow bit device and initiates incrementing a second count value stored at a corresponding memory location in response to a respective overflow bit being set. The incremented second count value is compared to an interrupt threshold value stored in a threshold register, and, when the second counter value is equal to the interrupt threshold value, a corresponding “interrupt arm” bit is set to enable a fast interrupt indication. On a subsequent roll-over of the lower bits of that counter, the interrupt will be fired.
摘要翻译：一种用于对具有中断指示进行计数事件的混合计数器阵列装置，包括包括N个计数器装置的第一计数器部分，每个计数器装置用于计数表示事件发生的信号，并提供表示较低位的第一计数值与每个相应计数器装置相关联的溢出位装置响应于溢出状况被另外设置。混合计数器阵列包括第二计数器部分，其包括具有与N个计数器装置对应的N个可寻址存储器位置的存储器阵列器件，每个可寻址存储器位置用于存储表示较高阶位的第二计数值。操作耦合的控制设备监视每个相关联的溢出位设备并且响应于设置的相应溢出位而启动存储在相应存储器位置的第二计数值的递增。将增加的第二计数值与存储在阈值寄存器中的中断阈值进行比较，并且当第二计数器值等于中断阈值时，相应的“中断臂”位被设置为使能快速中断指示。在该计数器的低位后续翻转时，中断将被触发。

9. 发明申请

US20080155201A1 METHOD AND APPARATUS FOR FILTERING SNOOP REQUESTS USING MULTIPLE SNOOP CACHES 有权
标题翻译：使用多个SNOOP CACHES过滤SNOOP要求的方法和设备
公开(公告)号：US20080155201A1
公开(公告)日：2008-06-26
申请号：US12042958
申请日：2008-03-05
申请人： Matthias A. Blumrich , Alan G. Gara , Valentina Salapura
发明人： Matthias A. Blumrich , Alan G. Gara , Valentina Salapura
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0822 , G06F2212/507 , Y02D10/13
摘要： A method and apparatus for implementing a snoop filter unit associated with a single processor in a multiprocessor system. The snoop filter unit has a plurality of ports, each port receiving snoop requests from exactly one dedicated source. Associated with each port is a snoop cache filter that processes each snoop cache request and records addresses of the most recent snoop requests for exactly one source. The snoop cache filter uses vector encoding to record the occurrence of snoop requests for a sequence of consecutive cache lines. All addresses of snoop requests are added to the snoop cache unless a received snoop cache request matches an entry present in the associated snoop cache, in which case the snoop request is discarded. Otherwise, the associated snoop cache request is enqueued for forwarding to the single processor. Information from all snoop cache filters assigned to all ports in the snoop filter unit are removed in the case that data corresponding to any one of the memory addresses contained in snoop cache filter is loaded in the cache hierarchy of the processor the snoop cache filter is assigned to.
摘要翻译：一种用于在多处理器系统中实现与单个处理器相关联的窥探滤波器单元的方法和装置。监听过滤器单元具有多个端口，每个端口接收来自正好一个专用源的窥探请求。与每个端口相关联的是一个侦听缓存过滤器，用于处理每个侦听缓存请求，并记录最近一次侦听请求的地址。监听高速缓存过滤器使用向量编码来记录连续高速缓存行序列的窥探请求的发生。侦听请求的所有地址都将添加到侦听缓存中，除非接收到的侦听缓存请求与相关侦听缓存中存在的条目匹配，在这种情况下，侦听请求将被丢弃。否则，相关联的侦听缓存请求被排入队列以转发到单个处理器。在分配给窥探过滤器单元中的所有端口的所有侦听缓存过滤器中的信息将被删除，因为与侦听高速缓存过滤器中包含的任何一个存储器地址相对应的数据被加载到处理器的高速缓存层次结构中，该侦听缓存过滤器被分配至。

10. 发明授权

US07383397B2 Method and apparatus for filtering snoop requests using a scoreboard 失效
标题翻译：使用记分板过滤窥探请求的方法和装置
公开(公告)号：US07383397B2
公开(公告)日：2008-06-03
申请号：US11093160
申请日：2005-03-29
申请人： Matthias A. Blumrich , Alan G. Gara , Thomas R. Puzak , Valentina Salapura
发明人： Matthias A. Blumrich , Alan G. Gara , Thomas R. Puzak , Valentina Salapura
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0822 , G06F12/0831 , G06F2212/507 , Y02D10/13
摘要： An apparatus for implementing snooping cache coherence that locally reduces the number of snoop requests presented to each cache in a multiprocessor system. A snoop filter device associated with a single processor includes one or more “scoreboard” data structures that make snoop determinations, i.e., for each snoop request from another processor, to determine if a request is to be forwarded to the processor or, discarded. At least one scoreboard is active, and at least one scoreboard is determined to be historic at any point in time. A snoop determination of the queue indicates that an entry may be in the cache, but does not indicate its actual residence status. In addition, the snoop filter block implementing scoreboard data structures is operatively coupled with a cache wrap detection logic means whereby, upon detection of a cache wrap condition, the content of the active scoreboard is copied into a historic scoreboard and the content of at least one active scoreboard is reset.
摘要翻译：用于实现窥探高速缓存一致性的装置，其本地地减少呈现给多处理器系统中的每个缓存的窥探请求的数量。与单个处理器相关联的窥探过滤器装置包括一个或多个“记分板”数据结构，其进行窥探确定，即，来自另一个处理器的每个窥探请求，以确定请求是否被转发到处理器或被丢弃。至少一个记分牌是活跃的，并且至少一个记分牌被确定为在任何时间点的历史。队列的窥探确定表示一个条目可能在缓存中，但不表示其实际居住状态。此外，实现记分板数据结构的窥探过滤器块与高速缓存包检测逻辑装置可操作地耦合，由此在检测到缓存包装条件时，将活动记分板的内容复制到历史记分板中，并且至少一个活动记分板重置。

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