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1. 发明授权

US08902892B2 Collective network routing 有权
标题翻译：集体网络路由
公开(公告)号：US08902892B2
公开(公告)日：2014-12-02
申请号：US12173073
申请日：2008-07-15
申请人： Dirk Hoenicke
发明人： Dirk Hoenicke
IPC分类号： H04L12/28 , H04L12/741 , H04L12/701 , H04L12/725
CPC分类号： H04L45/54 , H04L45/00 , H04L45/302
摘要： Disclosed are a unified method and apparatus to classify, route, and process injected data packets into a network so as to belong to a plurality of logical networks, each implementing a specific flow of data on top of a common physical network. The method allows to locally identify collectives of packets for local processing, such as the computation of the sum, difference, maximum, minimum, or other logical operations among the identified packet collective. Packets are injected together with a class-attribute and an opcode attribute. Network routers, employing the described method, use the packet attributes to look-up the class-specific route information from a local route table, which contains the local incoming and outgoing directions as part of the specifically implemented global data flow of the particular virtual network.
摘要翻译：公开了将注入的数据分组分类，路由和处理到网络中以便属于多个逻辑网络的统一方法和装置，每个逻辑网络在公共物理网络的顶部上实现特定的数据流。该方法允许本地识别用于本地处理的分组集合，诸如所识别的分组集合之间的总和，差分，最大值，最小值或其他逻辑操作的计算。数据包与类属性和操作码属性一起注入。采用所述方法的网络路由器使用分组属性从本地路由表中查找特定于类的路由信息，该本地路由表包含作为特定虚拟网络的具体实现的全局数据流的一部分的本地进入和离开方向。

2. 发明授权

US07650434B2 Global tree network for computing structures enabling global processing operations 失效
标题翻译：用于计算结构的全局树网络，实现全球处理操作
公开(公告)号：US07650434B2
公开(公告)日：2010-01-19
申请号：US10469000
申请日：2002-02-25
申请人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Burkhard D. Steinmacher-Burow , Todd E. Takken , Pavlos M. Vranas
发明人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Burkhard D. Steinmacher-Burow , Todd E. Takken , Pavlos M. Vranas
IPC分类号： G06F15/16
CPC分类号： G06F15/17337
摘要： A system and method for enabling high-speed, low-latency global tree network communications among processing nodes interconnected according to a tree network structure. The global tree network enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the tree via links to facilitate performance of low-latency global processing operations at nodes of the virtual tree and sub-tree structures. The global operations performed include one or more of: broadcast operations downstream from a root node to leaf nodes of a virtual tree, reduction operations upstream from leaf nodes to the root node in the virtual tree, and point-to-point message passing from any node to the root node. The global tree network is configurable to provide global barrier and interrupt functionality in asynchronous or synchronized manner, and, is physically and logically partitionable.
摘要翻译：一种用于根据树网络结构互连的处理节点之间实现高速，低延迟的全局树网络通信的系统和方法。全局树网络使得能够在具有多个互连的处理节点的计算机结构中执行并行算法操作期间执行集合缩减操作。包括通过链路互连树节点的路由器设备，以便于在虚拟树和子树结构的节点处执行低延迟全局处理操作。执行的全局操作包括以下一个或多个：从根节点向下游到虚拟树的叶节点的广播操作，从叶节点向上到叶节点到虚拟树中的根节点的减少操作，以及从任何节点到根节点。全局树网络可配置为以异步或同步方式提供全局屏障和中断功能，并且在物理和逻辑上可分区。

3. 发明授权

US07174434B2 Low latency memory access and synchronization 失效
标题翻译：低延迟内存访问和同步
公开(公告)号：US07174434B2
公开(公告)日：2007-02-06
申请号：US10468994
申请日：2002-02-25
申请人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Burkhard D. Steinmacher-Burow , Todd E. Takken , Pavlos M. Vranas
发明人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Burkhard D. Steinmacher-Burow , Todd E. Takken , Pavlos M. Vranas
IPC分类号： G06F12/12
CPC分类号： G06F9/52
摘要： A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.
摘要翻译：与弱有序的多处理器系统相关联地提供低延迟存储器系统访问。多处理器中的每个处理器共享资源，并且每个共享资源在锁定设备内具有关联的锁，其提供对多处理器中的多个处理器之间的同步的支持以及资源的有序共享。当处理器拥有与该资源相关联的锁定时，处理器仅具有访问资源的权限，并且处理器拥有锁的尝试仅需要单个加载操作，而不是传统的原子负载后跟存储，使得处理器只执行读取操作，并且硬件锁定装置执行后续的写入操作而不是处理器。还公开了用于非连续数据结构的简单预取。重新定义存储器线，使得除了正常的物理存储器数据之外，每行包括足够大的指针以指向存储器中的任何其他行，其中指针用于确定要预取的存储器行而不是一些其它预测算法。这使得硬件能够有效地预取不连续但重复的存储器访问模式。

4. 发明申请

US20110219280A1 COLLECTIVE NETWORK FOR COMPUTER STRUCTURES 有权
标题翻译：电脑结构的集体网络
公开(公告)号：US20110219280A1
公开(公告)日：2011-09-08
申请号：US13101566
申请日：2011-05-05
申请人： Matthias A. Blumrich , Paul W. Coteus , Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Todd E. Takken , Burkhard D. Steinmacher-Burow , Pavlos M. Vranas
发明人： Matthias A. Blumrich , Paul W. Coteus , Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Todd E. Takken , Burkhard D. Steinmacher-Burow , Pavlos M. Vranas
IPC分类号： H03M13/09 , H04L1/08 , G06F11/10 , G06F11/14
CPC分类号： H04L1/08 , G06F9/46 , G06F11/08 , G06F11/1423 , H03M13/09 , H04L1/0061 , H04L1/1607 , H04L1/1867 , H04L2001/0093 , H04L2001/0097
摘要： A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network and class structures. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to needs of a processing algorithm.
摘要翻译：一种用于实现互连处理节点之间的高速，低延迟全局集体通信的系统和方法。全局集体网络最优地使得能够在具有多个互连处理节点的计算机结构中执行并行算法操作期间执行集体缩减操作。包括通过链路互连网络节点的路由器设备，以便于在虚拟网络和类结构的节点处执行低延迟全局处理操作。全局集体网络可以被配置为以异步或同步方式提供全局屏障和中断功能。当在大规模并行超级计算结构中实现时，全局集体网络根据处理算法的需要在物理上和逻辑上可分割。

5. 发明申请

US20090313439A1 MANAGING COHERENCE VIA PUT/GET WINDOWS 失效
标题翻译：通过输入/获取窗口管理相关性
公开(公告)号：US20090313439A1
公开(公告)日：2009-12-17
申请号：US12543890
申请日：2009-08-19
申请人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht
发明人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht
IPC分类号： G06F12/08
CPC分类号： H05K7/20836 , F24F11/77 , G06F9/52 , G06F9/526 , G06F15/17381 , G06F17/142 , G09G5/008 , H04L7/0338
摘要： A method and apparatus for managing coherence between two processors of a two processor node of a multi-processor computer system. Generally the present invention relates to a software algorithm that simplifies and significantly speeds the management of cache coherence in a message passing parallel computer, and to hardware apparatus that assists this cache coherence algorithm. The software algorithm uses the opening and closing of put/get windows to coordinate the activated required to achieve cache coherence. The hardware apparatus may be an extension to the hardware address decode, that creates, in the physical memory address space of the node, an area of virtual memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements.
摘要翻译：一种用于管理多处理器计算机系统的两个处理器节点的两个处理器之间的相干性的方法和装置。通常，本发明涉及一种软件算法，其简化并显着加速了传送并行计算机的消息中的高速缓存一致性的管理以及辅助该高速缓存一致性算法的硬件设备。软件算法使用put / get窗口的打开和关闭来协调激活的所需要的，以实现缓存一致性。硬件设备可以是硬件地址解码的扩展，其在节点的物理存储器地址空间中创建（a）实际不存在的虚拟存储器的区域，并且（b）因此能够立即响应从处理元素读取和写入请求。

6. 发明授权

US07529895B2 Method for prefetching non-contiguous data structures 失效
标题翻译：预取非连续数据结构的方法
公开(公告)号：US07529895B2
公开(公告)日：2009-05-05
申请号：US11617276
申请日：2006-12-28
申请人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Burkhard D. Steinmacher-Burow , Todd E. Takken , Pavlos M. Vranas
发明人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Burkhard D. Steinmacher-Burow , Todd E. Takken , Pavlos M. Vranas
IPC分类号： G06F13/28
CPC分类号： G06F12/0862 , G06F9/52 , G06F2212/6028
摘要： A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple perfecting for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefect rather than some other predictive algorithm. This enables hardware to effectively prefect memory access patterns that are non-contiguous, but repetitive.
摘要翻译：与弱有序的多处理器系统相关联地提供低延迟存储器系统访问。多处理器中的每个处理器共享资源，并且每个共享资源在锁定设备内具有关联的锁，其提供对多处理器中的多个处理器之间的同步的支持以及资源的有序共享。当处理器拥有与该资源相关联的锁定时，处理器仅具有访问资源的权限，并且处理器拥有锁的尝试仅需要单个加载操作，而不是传统的原子负载后跟存储，使得处理器只执行读取操作，并且硬件锁定装置执行后续的写入操作而不是处理器。还公开了用于非连续数据结构的简单完善。存储器线被重新定义，使得除了正常的物理存储器数据之外，每行包括足够大的指针以指向存储器中的任何其他行，其中指针用于确定哪个存储器行被提供而不是一些其它预测算法。这使得硬件能够有效地预处理不连续但重复的存储器访问模式。

7. 发明申请

US20050081078A1 Deterministic error recovery protocol 失效
标题翻译：确定性错误恢复协议
公开(公告)号：US20050081078A1
公开(公告)日：2005-04-14
申请号：US10674952
申请日：2003-09-30
申请人： Matthias Blumrich , Dong Chen , Alan Gara , Philip Heidelberger , Dirk Hoenicke , Burkhard Steinmacher-Burow , Pavlos Vranas
发明人： Matthias Blumrich , Dong Chen , Alan Gara , Philip Heidelberger , Dirk Hoenicke , Burkhard Steinmacher-Burow , Pavlos Vranas
IPC分类号： G06F11/00 , G06F11/07 , G06F11/14 , H04L29/06 , H04L29/14
CPC分类号： G06F11/1443 , G06F11/0709 , G06F11/0793 , H04L1/0052 , H04L69/28 , H04L69/40 , H04L2001/0092
摘要： Disclosed are an error recovery method and system for use with a communication system having first and second nodes, each of said nodes having a receiver and a sender, the sender of the first node being connected to the receiver of the second node by a first cable, and the sender of the second node being connected to the receiver of the first node by a second cable. The method comprising the step of after one of the nodes detects an error, both of the nodes entering the same defined state. In particular, the receiver of the first node enters an error state, stays in the error state for a defined period of time T, and, after said defined period of time T, enters a wait state. Also, the sender of the first node sends to the receiver of the second node an error message for a defined period of time Te, and after the defined period of time Te, the sender of the first node enters an idle state.
摘要翻译：公开了一种用于与具有第一和第二节点的通信系统一起使用的错误恢复方法和系统，每个所述节点具有接收器和发送器，第一节点的发送器通过第一电缆连接到第二节点的接收器并且第二节点的发送者通过第二电缆连接到第一节点的接收器。所述方法包括在所述节点中的一个检测到错误之后的两个节点进入相同的定义状态的步骤。特别地，第一节点的接收机进入错误状态，在定义的时间段T内保持在错误状态，并且在所述定义的时间段T之后进入等待状态。此外，第一节点的发送方在给定的时间段Te的情况下向第二节点的接收者发送错误消息，并且在定义的时间段Te之后，第一节点的发送者进入空闲状态。

8. 发明申请

US20110072219A1 MANAGING COHERENCE VIA PUT/GET WINDOWS 失效
标题翻译：通过输入/获取窗口管理相关性
公开(公告)号：US20110072219A1
公开(公告)日：2011-03-24
申请号：US12953770
申请日：2010-11-24
申请人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Phillip Heidelberger , Dirk Hoenicke , Martin Ohmacht
发明人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Phillip Heidelberger , Dirk Hoenicke , Martin Ohmacht
IPC分类号： G06F12/08
CPC分类号： H05K7/20836 , F24F11/77 , G06F9/52 , G06F9/526 , G06F15/17381 , G06F17/142 , G09G5/008 , H04L7/0338
摘要： A method and apparatus for managing coherence between two processors of a two processor node of a multi-processor computer system. Generally the present invention relates to a software algorithm that simplifies and significantly speeds the management of cache coherence in a message passing parallel computer, and to hardware apparatus that assists this cache coherence algorithm. The software algorithm uses the opening and closing of put/get windows to coordinate the activated required to achieve cache coherence. The hardware apparatus may be an extension to the hardware address decode, that creates, in the physical memory address space of the node, an area of virtual memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements.
摘要翻译：一种用于管理多处理器计算机系统的两个处理器节点的两个处理器之间的相干性的方法和装置。通常，本发明涉及一种软件算法，其简化并显着加速了传送并行计算机的消息中的高速缓存一致性的管理以及辅助该高速缓存一致性算法的硬件设备。软件算法使用put / get窗口的打开和关闭来协调激活的所需要的，以实现缓存一致性。硬件设备可以是硬件地址解码的扩展，其在节点的物理存储器地址空间中创建（a）实际不存在的虚拟存储器的区域，并且（b）因此能够立即响应从处理元素读取和写入请求。

9. 发明授权

US07793038B2 System and method for programmable bank selection for banked memory subsystems 有权
标题翻译：用于存储存储器子系统的可编程存储体选择的系统和方法
公开(公告)号：US07793038B2
公开(公告)日：2010-09-07
申请号：US11768805
申请日：2007-06-26
申请人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark E. Giampapa , Dirk Hoenicke , Martin Ohmacht , Valentina Salapura , Krishnan Sugavanam
发明人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark E. Giampapa , Dirk Hoenicke , Martin Ohmacht , Valentina Salapura , Krishnan Sugavanam
IPC分类号： G06F12/00
CPC分类号： G06F12/0851 , G06F12/0804 , G06F12/0897 , Y02D10/13
摘要： A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each of the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.
摘要翻译：一种用于使得一个或多个处理器设备能够访问计算环境中的共享存储器的可编程存储器系统和方法，所述共享存储器包括具有用于存储数据的可寻址位置的一个或多个存储器存储结构。该系统包括：与相应的一个或多个处理器设备相关联的一个或多个第一逻辑设备，用于接收物理存储器地址信号的每个第一逻辑设备，并且可编程以在接收到预定地址位值时产生相应的存储器存储结构选择信号在选定的物理存储器地址位置; 以及响应于每个相应选择信号以产生用于选择用于处理器访问的存储器存储结构的地址信号的第二逻辑器件。因此，该系统使每个处理器设备能够分布在一个或多个存储器结构上的计算环境存储器存储访问。

10. 发明授权

US07486619B2 Multidimensional switch network 失效
标题翻译：多维交换机网络
公开(公告)号：US07486619B2
公开(公告)日：2009-02-03
申请号：US10793068
申请日：2004-03-04
申请人： Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Burkhard D. Steinmacher-Burow , Pavlos M. Vranas , Matthias Augustin Blumrich
发明人： Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Burkhard D. Steinmacher-Burow , Pavlos M. Vranas , Matthias Augustin Blumrich
IPC分类号： H04L12/28
CPC分类号： H04L49/1576 , H04L45/06
摘要： Multidimensional switch data networks are disclosed, such as are used by a distributed-memory parallel computer, as applied for example to computations in the field of life sciences. A distributed memory parallel computing system comprises a number of parallel compute nodes and a message passing data network connecting the compute nodes together. The data network connecting the compute nodes comprises a multidimensional switch data network of compute nodes having N dimensions, and a number/array of compute nodes Ln in each of the N dimensions. Each compute node includes an N port routing element having a port for each of the N dimensions. Each compute node of an array of Ln compute nodes in each of the N dimensions connects through a port of its routing element to an Ln port crossbar switch having Ln ports. Several embodiments are disclosed of a 4 dimensional computing system having 65,536 compute nodes.
摘要翻译：公开了多维交换机数据网络，例如由分布式存储器并行计算机使用的，例如应用于生命科学领域的计算。分布式存储器并行计算系统包括多个并行计算节点和将计算节点连接在一起的消息传递数据网络。连接计算节点的数据网络包括具有N维的计算节点的多维交换机数据网络和N个维度中的每一个中的计算节点Ln的数量/数组。每个计算节点包括具有用于N个维度中的每一个的端口的N端口路由元件。每个N维中的Ln计算节点阵列的每个计算节点通过其路由元素的端口连接到具有Ln端口的Ln端口交叉开关。公开了具有65,536个计算节点的四维计算系统的几个实施例。

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