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1. 发明授权

US10381960B2 Circuit for controlling slew rate of a high-side switching element 有权
公开(公告)号：US10381960B2
公开(公告)日：2019-08-13
申请号：US15328608
申请日：2015-07-23
申请人： RENESAS ELECTRONICS EUROPE GMBH
发明人： Hans-Juergen Braun
IPC分类号： H02P1/30 , H02P1/52 , H02P3/00 , H02P7/06 , H02P6/14 , H03K5/04 , H03K17/16
摘要： A circuit (11) for controlling slew rate of a high-side switching element (6) in a load switch (5) is described. The circuit includes a variable current source (20) for setting a slew rate. The circuit also includes an amplifier (15) comprising a first input coupled to a fixed voltage source (19), a second input coupled to the variable current source and an output (18) for a drive signal. A feedback path (26) from an input terminal (13), connected or connectable to an output (14) of the switching element, to the second input of the amplifier, includes a series voltage-differentiating element, such as a capacitor (27).

2. 发明申请

US20160065233A1 Digital-to-Analog Converter 有权
标题翻译：数模转换器
公开(公告)号：US20160065233A1
公开(公告)日：2016-03-03
申请号：US14783321
申请日：2014-04-03
申请人： RENESAS ELECTRONICS EUROPE GMBH
发明人： Bushan Vohora
IPC分类号： H03M1/66 , H03M1/06
CPC分类号： H03M1/661 , H03M1/0626 , H03M1/668 , H03M1/82
摘要： A digital-to-analog converter (DAC) is described. The DAC comprises a resistor having a resistance R and a capacitor having a capacitance C. The DAC comprises a first switching element configured, in response to a first control signal, to couple the capacitor to a first rail via a path having a resistance less than R and a second switching element configured, in response to a second control signal, to couple the capacitor to the first rail through the resistor. The DAC also comprises a third switching element configured, in response to a third control signal, to couple the capacitor to a second rail (8) via a path having a resistance less than R and a fourth switching element configured, in response to a responsive to a fourth control signal, to couple the capacitor to the second through the resistor. The capacitor can be quickly charged or discharged over a period less than RC or less than 0.7 RC. The DAC may comprise a first control element configured to switch on the second switching element before switching on the first switching element and a second control element configured to switch on the fourth switching element before switching on the third switching element.
摘要翻译：描述了数模转换器（DAC）。 DAC包括具有电阻R的电阻器和具有电容C的电容器。DAC包括第一开关元件，该第一开关元件响应于第一控制信号，经由电阻小于 R和第二开关元件，其被配置为响应于第二控制信号，通过电阻器将电容器耦合到第一导轨。 DAC还包括第三开关元件，其被配置为响应于第三控制信号，经由具有小于R的电阻的路径和第四开关元件将电容器耦合到第二导轨（8），响应于响应到第四控制信号，以通过电阻将电容器耦合到第二控制信号。电容器可以在小于RC或小于0.7 RC的时间内快速充电或放电。 DAC可以包括第一控制元件，其被配置为在接通第一开关元件之前接通第二开关元件，以及第二控制元件，其被配置为在接通第三开关元件之前接通第四开关元件。

3. 发明授权

US10833878B2 Integrated circuit with parts activated based on intrinsic features 有权
公开(公告)号：US10833878B2
公开(公告)日：2020-11-10
申请号：US15120207
申请日：2015-02-19
申请人： RENESAS ELECTRONICS EUROPE GMBH
发明人： Fabrice Poulard
IPC分类号： H04L9/32 , G06F21/73 , G06F21/10 , G06F21/72
摘要： A fixed logic integrated circuit is disclosed. The integrated circuit comprises a unique code generator configured to generate a code having a value which is intrinsically unique to the integrated circuit, an enrolment pattern generator configured to generate an enrolment pattern based on the unique code. The integrated circuit is configured to transmit the enrolment pattern to an external enrolment device and to receive enabling data from the external enrolment device. Optionally, the integrated circuit may include memory for storing remotely-generated enabling data. The integrated circuit comprises a configuration file generator configured to generate configuration data using the remotely-generated enabling data and the unique code, and a feature activation module configured to activate and/or disable features of the integrated circuit and/or customise the integrated circuit in dependence upon the configuration data.

4. 发明授权

US10592406B2 Memory access unit and method including generating memory selects to concurrently access a plurality of memories in a multi-dimensional array 有权
公开(公告)号：US10592406B2
公开(公告)日：2020-03-17
申请号：US15524098
申请日：2015-10-15
申请人： RENESAS ELECTRONICS EUROPE GMBH
发明人： Matthias Gruenewald
IPC分类号： G06F12/02 , G06F12/06 , G06F13/16 , G01S13/524 , G01S13/87 , G01S13/28 , G01S13/931 , G01S13/53
摘要： A memory access unit for handling transfers of samples in a d-dimensional array between a one of m data buses, where m≥1, and k*m memories, where k≥2, is disclosed. The memory access unit comprises k address calculators, each address calculator configured to receive a bus address to add a respective offset to generate a sample bus address and to generate, from the sample bus address according to an addressing scheme, a respective address in each of the d dimensions for access along one of the dimensions from the bus address according to an addressing scheme, for accessing a sample. The memory access unit comprises k sample collectors, each sample collector operable to generate a memory select for a one of the k*m memories so as to transfer the sample between a predetermined position in a bus data word and the respective one of the k*m memories. Each sample collector is configured to calculate a respective memory select in dependence upon the address in each of the d dimensions such that each sample collector selects a different one of the k*m memories so as to allow the sample collectors to access k of the k*m memories concurrently. A memory controller may comprise m memory access units for handling transfers of samples in a d-dimensional array between m data buses and k*m memories. An integrated circuit (IC) comprising a memory access unit, and a motor vehicle comprising a computing device having a memory access unit are also disclosed.

5. 发明申请

US20190036706A1 INTEGRATED CIRCUIT WITH ANTI-COUNTERFEITING CAPABILITIES 审中-公开
公开(公告)号：US20190036706A1
公开(公告)日：2019-01-31
申请号：US16071517
申请日：2016-01-20
申请人： RENESAS ELECTRONICS EUROPE GMBH
发明人： Thomas DETERT
IPC分类号： H04L9/32 , G06K19/07 , H04L9/30 , H04L9/14
摘要： An integrated circuit is described. The integrated circuit comprises a one-time programmable non-volatile memory and a memory controller for the one-time programmable non-volatile memory. The memory controller is configured to send a first random number which has been generated in the integrated circuit to a device initialization server. The memory controller is configured, in response to receiving a signed device initialization message from the device initialization server, the signed device initialization message comprising a device initialization message and a corresponding signature, and the device initialization message comprising a second random number and a device identity, to determine whether the first and second random numbers are equal and whether the signature is valid. The memory controller is configured, in response to determining that the first and second random numbers are equal and that the signature is valid to program the device identity into a first part of the one-time programmable non-volatile memory.

6. 发明授权

US10020958B2 CAN FD 有权
公开(公告)号：US10020958B2
公开(公告)日：2018-07-10
申请号：US14888256
申请日：2014-03-31
申请人： Renesas Electronics Europe GmbH
发明人： Roland Lieder , Klaus Turski
IPC分类号： H04L12/40 , H04L12/46 , H04L29/06 , H04L1/00
CPC分类号： H04L12/40032 , H04L1/0002 , H04L12/4013 , H04L12/4625 , H04L69/08 , H04L2012/40215
摘要： A device for allowing a CAN 2.0B controller to participate passively in CAN FD communication is described. The device is configured to identify whether a frame on RXD is a CAN FD frame and, in dependence upon identifying that the frame is a CAN FD frame, to replace a section of the CAN FD frame, including the data phase of the CAN FD frame, with substitute data having a format which complies with CAN 2.0B. The device may be included in a CAN transceiver.

7. 发明申请

US20170078105A1 Integrated Circuit with Parts Activated Based on Intrinsic Features 审中-公开
标题翻译：基于内在特性激活部件的集成电路
公开(公告)号：US20170078105A1
公开(公告)日：2017-03-16
申请号：US15120207
申请日：2015-02-19
申请人： RENESAS ELECTRONICS EUROPE GMBH
发明人： Fabrice Poulard
IPC分类号： H04L9/32 , G06F21/72 , G06F21/73
摘要： A fixed logic integrated circuit is disclosed. The integrated circuit comprises a unique code generator configured to generate a code having a value which is intrinsically unique to the integrated circuit, an enrolment pattern generator configured to generate an enrolment pattern based on the unique code. The integrated circuit is configured to transmit the enrolment pattern to an external enrolment device and to receive enabling data from the external enrolment device. Optionally, the integrated circuit may include memory for storing remotely-generated enabling data. The integrated circuit comprises a configuration file generator configured to generate configuration data using the remotely-generated enabling data and the unique code, and a feature activation module configured to activate and/or disable features of the integrated circuit and/or customise the integrated circuit in dependence upon the configuration data.
摘要翻译：公开了一种固定逻辑集成电路。集成电路包括唯一代码生成器，其被配置为生成具有对于集成电路本质上唯一的值的代码，被配置为基于唯一代码生成注册模式的注册模式生成器。集成电路被配置为将注册模式传送到外部注册设备并且从外部注册设备接收启用数据。可选地，集成电路可以包括用于存储远程产生的使能数据的存储器。集成电路包括配置文件生成器，其被配置为使用远程产生的启用数据和唯一代码来生成配置数据，以及特征激活模块，被配置为激活和/或禁用集成电路的特征和/或定制集成电路依赖于配置数据。

8. 发明申请

US20190280632A1 ADAPTIVE CONTROL SYSTEM 审中-公开
公开(公告)号：US20190280632A1
公开(公告)日：2019-09-12
申请号：US16463054
申请日：2016-11-24
申请人： RENESAS ELECTRONICS EUROPE GMBH
发明人： Suad Jusuf
IPC分类号： H02P21/18 , H02P21/00 , H02P21/26
摘要： An adaptive control system (2) for controlling a plant (3) is disclosed. The adaptive control system comprises a control system (5) configured to generate drive signals (16) for the plant in dependence upon a reference signal (8) and an error signal, and a state observer (17) or state sensor (17′; FIG. 2) configured to generate an estimate of a state of the plant in dependence upon the reference signal. The system comprises an error combiner (12) configured to selectably combine a first error (11) determined from the reference signal and a set of measurements of the plant and a second error (13) determined from the reference and the estimate.

9. 发明申请

US20170329702A1 MEMORY ACCESS UNIT 审中-公开
公开(公告)号：US20170329702A1
公开(公告)日：2017-11-16
申请号：US15524098
申请日：2015-10-15
申请人： RENESAS ELECTRONICS EUROPE GMBH
发明人： Matthias Gruenewald
IPC分类号： G06F12/02 , G06F12/06 , G01S13/53 , G06F13/16
摘要： A memory access unit for handling transfers of samples in a d-dimensional array between a one of m data buses, where m≧1, and k*m memories, where k≧2, is disclosed. The memory access unit comprises k address calculators, each address calculator configured to receive a bus address to add a respective offset to generate a sample bus address and to generate, from the sample bus address according to an addressing scheme, a respective address in each of the d dimensions for access along one of the dimensions from the bus address according to an addressing scheme, for accessing a sample. The memory access unit comprises k sample collectors, each sample collector operable to generate a memory select for a one of the k*m memories so as to transfer the sample between a predetermined position in a bus data word and the respective one of the k*m memories. Each sample collector is configured to calculate a respective memory select in dependence upon the address in each of the d dimensions such that each sample collector selects a different one of the k*m memories so as to allow the sample collectors to access k of the k*m memories concurrently. A memory controller may comprise m memory access units for handling transfers of samples in a d-dimensional array between m data buses and k*m memories.

10. 发明申请

US20170214342A1 CIRCUIT FOR CONTROLLING SLEW RATE OF A HIGH-SIDE SWITCHING ELEMENT 审中-公开
公开(公告)号：US20170214342A1
公开(公告)日：2017-07-27
申请号：US15328608
申请日：2015-07-23
申请人： RENESAS ELECTRONICS EUROPE GMBH
发明人： Hans-Juergen Braun
IPC分类号： H02P6/14 , H03K17/16 , H03K5/04
CPC分类号： H02P6/14 , H03K5/04 , H03K17/166 , H03K2217/0036 , H03K2217/0063
摘要： A circuit (11) for controlling slew rate of a high-side switching element (6) in a load switch (5) is described. The circuit includes a variable current source (20) for setting a slew rate. The circuit also includes an amplifier (15) comprising a first input coupled to a fixed voltage source (19), a second input coupled to the variable current source and an output (18) for a drive signal. A feedback path (26) from an input terminal (13), connected or connectable to an output (14) of the switching element, to the second input of the amplifier, includes a series voltage-differentiating element, such as a capacitor (27).

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