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1. 发明授权

US08593174B1 Omnibus logic element for packing or fracturing 有权
$Omnibus logic element for packing or fracturing$
标题翻译：用于包装或压裂的综合逻辑元件
公开(公告)号：US08593174B1
公开(公告)日：2013-11-26
申请号：US13539007
申请日：2012-06-29
申请人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
发明人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , G06F7/50 , H03K19/017581
摘要： Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.
摘要翻译：公开了可以提供多个有利特征的逻辑元件（LE）。例如，LE可以被配置为实现寄存器打包和/或可破碎的查找表。

2. 发明授权

US08237465B1 Omnibus logic element for packing or fracturing 有权
$Omnibus logic element for packing or fracturing$
标题翻译：用于包装或压裂的综合逻辑元件
公开(公告)号：US08237465B1
公开(公告)日：2012-08-07
申请号：US13050732
申请日：2011-03-17
申请人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
发明人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , G06F7/50 , H03K19/017581
摘要： Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.
摘要翻译：公开了可以提供多个有利特征的逻辑元件（LE）。例如，LE可以被配置为实现寄存器打包和/或可破碎的查找表。

3. 发明授权

US08108812B1 Register retiming technique 有权
标题翻译：注册重新定时技术
公开(公告)号：US08108812B1
公开(公告)日：2012-01-31
申请号：US12749514
申请日：2010-03-30
申请人： Babette van Antwerpen , Michael D. Hutton , Gregg Baeckler , Richard Yuan
发明人： Babette van Antwerpen , Michael D. Hutton , Gregg Baeckler , Richard Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5045
摘要： An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.
摘要翻译：电子自动化系统对逻辑设计执行寄存器重新定时，这可能是可编程逻辑集成电路的逻辑设计。寄存器重新定时是设计中组合逻辑寄存器的移动或重排，以提高最大工作频率或fmax。在一个实现中，该系统包括机器可读代码，其可以存储在计算机上执行的诸如磁盘的计算机可读介质上。系统平衡时间，以便折中关键路径和非关键路径之间的延迟。注册重新定时可能会改变门级设计。

4. 发明授权

US07689955B1 Register retiming technique 失效
标题翻译：注册重新定时技术
公开(公告)号：US07689955B1
公开(公告)日：2010-03-30
申请号：US11513450
申请日：2006-08-30
申请人： Babette van Antwerpen , Michael D. Hutton , Gregg Baeckler , Richard Yuan
发明人： Babette van Antwerpen , Michael D. Hutton , Gregg Baeckler , Richard Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5045
摘要： An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.
摘要翻译：电子自动化系统对逻辑设计执行寄存器重新定时，这可能是可编程逻辑集成电路的逻辑设计。寄存器重新定时是设计中组合逻辑寄存器的移动或重排，以提高最大工作频率或fmax。在一个实现中，该系统包括机器可读代码，其可以存储在计算机上执行的诸如磁盘的计算机可读介质上。系统平衡时间，以便折中关键路径和非关键路径之间的延迟。注册重新定时可能会改变门级设计。

5. 发明授权

US07171633B1 Estimating quality during early synthesis 有权
标题翻译：早期综合评估质量
公开(公告)号：US07171633B1
公开(公告)日：2007-01-30
申请号：US10734905
申请日：2003-12-12
申请人： Yean-Yow Hwang , Babette van Antwerpen , Richard Yuan
发明人： Yean-Yow Hwang , Babette van Antwerpen , Richard Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A computer aided system includes a method of improving the accuracy, optimization, and minimization for the synthesis and mapping of logical functions into the logical structures of a target technology, such as the logic cells (e.g., look-up tables) of a programmable logic integrated circuit. In a specific implementation, the invention incorporates late-stage synthesis operations, such as found during a technology mapping operation, into earlier stage synthesis procedures. These late-stage synthesis operations are used to provide better estimates of delay and area of a final compiled design in order to guide optimization operations.
摘要翻译：计算机辅助系统包括提高逻辑功能的合成和映射到诸如可编程逻辑的逻辑单元（例如，查找表）的目标技术的逻辑结构中的精度，优化和最小化的方法集成电路。在具体实现中，本发明将晚期合成操作（诸如在技术映射操作期间发现）融入到早期阶段合成过程中。这些后期综合操作用于提供对最终编译设计的延迟和面积的更好估计，以指导优化操作。

6. 发明授权

US07167022B1 Omnibus logic element including look up table based logic elements 有权
标题翻译：综合逻辑元素包括基于查询表的逻辑元素
公开(公告)号：US07167022B1
公开(公告)日：2007-01-23
申请号：US10810117
申请日：2004-03-25
申请人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
发明人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , G06F7/50 , H03K19/017581
摘要： Disclosed is an LE that can provide a number of advantageous feature. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.
摘要翻译：公开了可以提供多个有利特征的LE。例如，LE可以提供LUT和输入共享的高效灵活的使用。 LE还可以灵活地使用一个或多个专用加法器并且包括寄存器功能。

7. 发明授权

US08402408B1 Register retiming technique 有权
公开(公告)号：US08402408B1
公开(公告)日：2013-03-19
申请号：US13338776
申请日：2011-12-28
申请人： Babette van Antwerpen , Michael D. Hutton , Gregg Baeckler , Richard Yuan
发明人： Babette van Antwerpen , Michael D. Hutton , Gregg Baeckler , Richard Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5045
摘要： An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.

8. 发明授权

US07911230B1 Omnibus logic element for packing or fracturing 有权
$Omnibus logic element for packing or fracturing$
标题翻译：用于包装或压裂的综合逻辑元件
公开(公告)号：US07911230B1
公开(公告)日：2011-03-22
申请号：US12425342
申请日：2009-04-16
申请人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
发明人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
IPC分类号： H03K19/173
CPC分类号： H03K19/17728 , G06F7/50 , H03K19/017581
摘要： Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.
摘要翻译：公开了可以提供多个有利特征的逻辑元件（LE）。例如，LE可以被配置为实现寄存器打包和/或可破碎的查找表。

9. 发明授权

US07594208B1 Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage 有权
标题翻译：在计算机辅助设计中自动扫描参数以实现最佳性能和资源使用的技术
公开(公告)号：US07594208B1
公开(公告)日：2009-09-22
申请号：US11610392
申请日：2006-12-13
申请人： Terry Borer , Ian Chesal , James Schleicher , David Mendel , Mike Hutton , Boris Ratchev , Yaska Sankar , Babette van Antwerpen , Gregg Baeckler , Richard Yuan , Stephen Brown , Vaughn Betz , Kevin Chan
发明人： Terry Borer , Ian Chesal , James Schleicher , David Mendel , Mike Hutton , Boris Ratchev , Yaska Sankar , Babette van Antwerpen , Gregg Baeckler , Richard Yuan , Stephen Brown , Vaughn Betz , Kevin Chan
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. In one embodiment, the values of the output metrics are averaged for all test compiles that share the same input parameters, but different seeds. In another embodiment, the compile with the best output metrics, as determined by the user, are selected. These techniques allow a user to automatically trade off compile-time to get a better-optimized circuit.
摘要翻译：提供了用于优化可编程集成电路上的电路设计的放置和合成的技术。在对已选择的输入参数编译不同的值后，对电路设计的性能进行分析。然后选择为输出量度产生最佳结果的输入参数值，以将电路设计合成并将其放置在可编程集成电路上。在一个实施例中，对于共享相同输入参数但是不同种子的所有测试编译器，对输出度量的值进行平均。在另一个实施例中，选择由用户确定的具有最佳输出度量的编译。这些技术允许用户自动交换编译时间以获得更优化的电路。

10. 发明授权

US07565388B1 Logic cell supporting addition of three binary words 有权
标题翻译：逻辑单元支持添加三个二进制字
公开(公告)号：US07565388B1
公开(公告)日：2009-07-21
申请号：US10718968
申请日：2003-11-21
申请人： Gregg Baeckler , Martin Langhammer , James Schleicher , Richard Yuan
发明人： Gregg Baeckler , Martin Langhammer , James Schleicher , Richard Yuan
IPC分类号： G06F7/38 , G06F7/50
CPC分类号： G06F7/509 , H03K19/1733
摘要： Logic circuits that support the addition of three binary numbers using hardwired adders are described. In one embodiment, this is accomplished by using a 3:2 compressor (i.e., a Carry Save Adder method), using hardwired adders to add the sums and carrys produced by the 3:2 compression, and sharing carrys data calculated in one logic element (“LE”) with the following LE. In such an embodiment, with the exception of the first and last LEs in a logic array block (“LAB”), each LE in effect lends one look-up table (“LUT”) to the LE below (i.e., the following LE) and borrows one LUT from the LE above (i.e., the previous LE). The LUT being lent or borrowed is one that implements the carry function in the 3:2 compressor model. In another aspect, an embodiment of the present invention provides LEs that include selectors to select signals corresponding to the addition of three binary numbers mode.
摘要翻译：描述了支持使用硬连线加法器添加三个二进制数的逻辑电路。在一个实施例中，这是通过使用3：2压缩器（即，进位保存加法器方法）来实现的，其使用硬连线加法器来添加由3：2压缩产生的和和携带，并且共享携带在一个逻辑元件中计算的数据（“LE”）与以下LE。在这样的实施例中，除了逻辑阵列块（“LAB”）中的第一个和最后一个LE之外，每个LE有效地将一个查找表（“LUT”）提供给下面的LE（即，下面的LE ）并从上面的LE借用一个LUT（即，先前的LE）。借出或借用的LUT是在3：2压缩机模型中实现进位功能的LUT。在另一方面，本发明的实施例提供了包括选择器的LE，用于选择对应于三进制数模式的添加的信号。

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