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1. 发明授权

US07181703B1 Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage 有权
标题翻译：在计算机辅助设计中自动扫描参数以实现最佳性能和资源使用的技术
公开(公告)号：US07181703B1
公开(公告)日：2007-02-20
申请号：US10625505
申请日：2003-07-22
申请人： Terry Borer , Ian Chesal , James Schleicher , David Mendel , Mike Hutton , Boris Ratchev , Yaska Sankar , Babette van Antwerpen , Gregg Baeckler , Richard Yuan , Stephen Brown , Vaughn Betz , Kevin Chan
发明人： Terry Borer , Ian Chesal , James Schleicher , David Mendel , Mike Hutton , Boris Ratchev , Yaska Sankar , Babette van Antwerpen , Gregg Baeckler , Richard Yuan , Stephen Brown , Vaughn Betz , Kevin Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. In one embodiment, the values of the output metrics are averaged for all test compiles that share the same input parameters, but different seeds. In another embodiment, the compile with the best output metrics, as determined by the user, are selected. These techniques allow a user to automatically trade off compile-time to get a better-optimized circuit.
摘要翻译：提供了用于优化可编程集成电路上的电路设计的放置和合成的技术。在对已选择的输入参数编译不同的值后，对电路设计的性能进行分析。然后选择为输出量度产生最佳结果的输入参数值，以将电路设计合成并将其放置在可编程集成电路上。在一个实施例中，对于共享相同输入参数但是不同种子的所有测试编译器，对输出度量的值进行平均。在另一个实施例中，选择由用户确定的具有最佳输出度量的编译。这些技术允许用户自动交换编译时间以获得更优化的电路。

2. 发明授权

US08402408B1 Register retiming technique 有权
公开(公告)号：US08402408B1
公开(公告)日：2013-03-19
申请号：US13338776
申请日：2011-12-28
申请人： Babette van Antwerpen , Michael D. Hutton , Gregg Baeckler , Richard Yuan
发明人： Babette van Antwerpen , Michael D. Hutton , Gregg Baeckler , Richard Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5045
摘要： An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.

3. 发明授权

US07911230B1 Omnibus logic element for packing or fracturing 有权
$Omnibus logic element for packing or fracturing$
标题翻译：用于包装或压裂的综合逻辑元件
公开(公告)号：US07911230B1
公开(公告)日：2011-03-22
申请号：US12425342
申请日：2009-04-16
申请人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
发明人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
IPC分类号： H03K19/173
CPC分类号： H03K19/17728 , G06F7/50 , H03K19/017581
摘要： Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.
摘要翻译：公开了可以提供多个有利特征的逻辑元件（LE）。例如，LE可以被配置为实现寄存器打包和/或可破碎的查找表。

4. 发明授权

US07594208B1 Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage 有权
标题翻译：在计算机辅助设计中自动扫描参数以实现最佳性能和资源使用的技术
公开(公告)号：US07594208B1
公开(公告)日：2009-09-22
申请号：US11610392
申请日：2006-12-13
申请人： Terry Borer , Ian Chesal , James Schleicher , David Mendel , Mike Hutton , Boris Ratchev , Yaska Sankar , Babette van Antwerpen , Gregg Baeckler , Richard Yuan , Stephen Brown , Vaughn Betz , Kevin Chan
发明人： Terry Borer , Ian Chesal , James Schleicher , David Mendel , Mike Hutton , Boris Ratchev , Yaska Sankar , Babette van Antwerpen , Gregg Baeckler , Richard Yuan , Stephen Brown , Vaughn Betz , Kevin Chan
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. In one embodiment, the values of the output metrics are averaged for all test compiles that share the same input parameters, but different seeds. In another embodiment, the compile with the best output metrics, as determined by the user, are selected. These techniques allow a user to automatically trade off compile-time to get a better-optimized circuit.
摘要翻译：提供了用于优化可编程集成电路上的电路设计的放置和合成的技术。在对已选择的输入参数编译不同的值后，对电路设计的性能进行分析。然后选择为输出量度产生最佳结果的输入参数值，以将电路设计合成并将其放置在可编程集成电路上。在一个实施例中，对于共享相同输入参数但是不同种子的所有测试编译器，对输出度量的值进行平均。在另一个实施例中，选择由用户确定的具有最佳输出度量的编译。这些技术允许用户自动交换编译时间以获得更优化的电路。

5. 发明授权

US07565388B1 Logic cell supporting addition of three binary words 有权
标题翻译：逻辑单元支持添加三个二进制字
公开(公告)号：US07565388B1
公开(公告)日：2009-07-21
申请号：US10718968
申请日：2003-11-21
申请人： Gregg Baeckler , Martin Langhammer , James Schleicher , Richard Yuan
发明人： Gregg Baeckler , Martin Langhammer , James Schleicher , Richard Yuan
IPC分类号： G06F7/38 , G06F7/50
CPC分类号： G06F7/509 , H03K19/1733
摘要： Logic circuits that support the addition of three binary numbers using hardwired adders are described. In one embodiment, this is accomplished by using a 3:2 compressor (i.e., a Carry Save Adder method), using hardwired adders to add the sums and carrys produced by the 3:2 compression, and sharing carrys data calculated in one logic element (“LE”) with the following LE. In such an embodiment, with the exception of the first and last LEs in a logic array block (“LAB”), each LE in effect lends one look-up table (“LUT”) to the LE below (i.e., the following LE) and borrows one LUT from the LE above (i.e., the previous LE). The LUT being lent or borrowed is one that implements the carry function in the 3:2 compressor model. In another aspect, an embodiment of the present invention provides LEs that include selectors to select signals corresponding to the addition of three binary numbers mode.
摘要翻译：描述了支持使用硬连线加法器添加三个二进制数的逻辑电路。在一个实施例中，这是通过使用3：2压缩器（即，进位保存加法器方法）来实现的，其使用硬连线加法器来添加由3：2压缩产生的和和携带，并且共享携带在一个逻辑元件中计算的数据（“LE”）与以下LE。在这样的实施例中，除了逻辑阵列块（“LAB”）中的第一个和最后一个LE之外，每个LE有效地将一个查找表（“LUT”）提供给下面的LE（即，下面的LE ）并从上面的LE借用一个LUT（即，先前的LE）。借出或借用的LUT是在3：2压缩机模型中实现进位功能的LUT。在另一方面，本发明的实施例提供了包括选择器的LE，用于选择对应于三进制数模式的添加的信号。

6. 发明授权

US07538579B1 Omnibus logic element 有权
标题翻译：综合逻辑元素
公开(公告)号：US07538579B1
公开(公告)日：2009-05-26
申请号：US11607171
申请日：2006-12-01
申请人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
发明人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , G06F7/50 , H03K19/017581
摘要： Disclosed is an LE that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.
摘要翻译：公开了可以提供许多有利特征的LE。例如，LE可以提供LUT和输入共享的高效灵活的使用。 LE还可以灵活地使用一个或多个专用加法器并且包括寄存器功能。

7. 发明授权

US07671625B1 Omnibus logic element 有权
标题翻译：综合逻辑元素
公开(公告)号：US07671625B1
公开(公告)日：2010-03-02
申请号：US12043087
申请日：2008-03-05
申请人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Michael Hutton , Andy Lee , Rahul Saini , Henry Kim
发明人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Michael Hutton , Andy Lee , Rahul Saini , Henry Kim
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , G06F7/50 , H03K19/017581
摘要： Disclosed is an LE that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.
摘要翻译：公开了可以提供许多有利特征的LE。例如，LE可以提供LUT和输入共享的高效灵活的使用。 LE还可以灵活地使用一个或多个专用加法器并且包括寄存器功能。

8. 发明授权

US07337100B1 Physical resynthesis of a logic design 失效
标题翻译：逻辑设计的物理再合成
公开(公告)号：US07337100B1
公开(公告)日：2008-02-26
申请号：US10461921
申请日：2003-06-12
申请人： Michael D. Hutton , Joachim Pistorius , Babette van Antwerpen , Gregg Baeckler , Richard Yuan , Yean-Yow Hwang
发明人： Michael D. Hutton , Joachim Pistorius , Babette van Antwerpen , Gregg Baeckler , Richard Yuan , Yean-Yow Hwang
IPC分类号： G06F17/50 , G06F9/455 , G01R31/28
CPC分类号： G06F17/5068
摘要： A multiple-pass synthesis technique improves the performance of a design. In a specific embodiment, synthesis is performed in two or more passes. In a first pass, a first synthesis is performed, and in a second or subsequent pass, a second synthesis or resynthesis is performed. During the first synthesis, the logic will be mapped to for example, the logic structures (e.g., logic elements, LUTs, synthesis gates) of the target technology such as a programmable logic device. Alternatively a netlist may be provided from a third party. Before the second synthesis, a fast or abbreviated fit may be performed of the netlist to a specific device (e.g., specific programmable logic device product). Before the second synthesis, the netlist obtained from the first synthesis (or provided by a third party) is unmapped and then the second synthesis is performed. Since a partial fit is performed, the second synthesis has more visibility and optimize the logic better than by using a single synthesis pass. After the second synthesis pass, a more detailed fit is performed.
摘要翻译：多通道合成技术提高了设计的性能。在具体实施方案中，以两次或更多次通过进行合成。在第一次通过中，执行第一次合成，并且在第二次或随后的过程中进行第二次合成或再合成。在第一合成期间，逻辑将被映射到例如目标技术的逻辑结构（例如，逻辑元件，LUT，合成门），诸如可编程逻辑器件。或者，可以从第三方提供网表。在第二合成之前，可以将网表快速或缩写配合到特定设备（例如，特定的可编程逻辑设备产品）。在第二次合成之前，从第一次合成（或由第三方提供）获得的网表被未映射，然后进行第二次合成。由于执行部分拟合，所以第二合成比通过使用单个合成通路更好的可见性和优化逻辑。在第二次合成之后，进行更详细的拟合。

9. 发明授权

US07120883B1 Register retiming technique 有权
公开(公告)号：US07120883B1
公开(公告)日：2006-10-10
申请号：US10446650
申请日：2003-05-27
申请人： Babette van Antwerpen , Michael D. Hutton , Gregg Baeckler , Richard Yuan
发明人： Babette van Antwerpen , Michael D. Hutton , Gregg Baeckler , Richard Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5045
摘要： An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.

10. 发明授权

US07350176B1 Techniques for mapping to a shared lookup table mask 有权
标题翻译：映射到共享查找表掩码的技术
公开(公告)号：US07350176B1
公开(公告)日：2008-03-25
申请号：US10622923
申请日：2003-07-17
申请人： Gregg Baeckler , Michael Hutton
发明人： Gregg Baeckler , Michael Hutton
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Techniques for combining lookup tables on a programmable integrated circuit are provided. Lookup tables (LUTS) in a design for a programmable circuit can be combined into one mask if they implement the same function. Any two LUTs in a design can be compared to determine if they implement the same function by rearranging the input signals of one of the LUTs with respect to the input terminals of that LUT. Pairs of LUTs can be rejected if they do not share at least N common input signals, or if they have more than M unique input signals.
摘要翻译：提供了在可编程集成电路上组合查找表的技术。可编程电路设计中的查找表（LUTS）可以组合成一个掩码，如果它们实现相同的功能。可以将设计中的任何两个LUT进行比较，以通过相对于该LUT的输入端重新排列一个LUT的输入信号来确定它们是否实现相同的功能。如果它们不共享至少N个公共输入信号，或者如果它们具有多于M个唯一的输入信号，则可以拒绝对的LUT。

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