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1. 发明申请

US20110122710A1 METHOD AND APPARATUS FOR GENERATING A SEQUENCE OF CLOCK SIGNALS 失效
标题翻译：用于产生时钟信号序列的方法和装置
公开(公告)号：US20110122710A1
公开(公告)日：2011-05-26
申请号：US13021223
申请日：2011-02-04
申请人： Ronnie M. Harrison
发明人： Ronnie M. Harrison
IPC分类号： G11C8/18 , G11C7/10
CPC分类号： G11C7/22 , G11C7/1078 , G11C7/109 , G11C7/222 , G11C8/08 , G11C8/10 , G11C11/4076 , G11C11/4093 , H03L7/07 , H03L7/0812 , H03L7/0891
摘要： A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The inner delay-locked loop includes a voltage controlled delay line that delays a reference clock applied to its input by a plurality of respective delays. Two of the clock signals in the sequence are applied to a phase detector so that the signals at the outputs of the delay line have predetermined phases relative to each other. The outer delay-locked loop is formed by a voltage controlled delay circuit that delays the command clock by a voltage controlled delay to provide the reference clock to the delay line of the inner delay-locked loop. The outer delay-locked loop also includes a phase detector that compares the command clock to one of the clock signals in the sequence generated by the delay line. The outer delay-locked loop thus locks one of the clock signals in the sequence to the command clock. As a result, all of the clock signals in the sequence generated by the delay line have respective predetermined phases relative to the phase of the command clock. One of the clock signals in the sequence is selected by a multiplexer to clock a command data latch at a time corresponding to the delay in coupling a command data bit to the latch.
摘要翻译：时钟发生器电路从主时钟信号产生彼此相位相位的时钟信号序列。时钟发生器由内部和外部延迟锁定环形成。内部延迟锁定环路包括电压控制延迟线，其延迟通过多个相应延迟施加到其输入的参考时钟。序列中的两个时钟信号被施加到相位检测器，使得延迟线的输出处的信号相对于彼此具有预定的相位。外部延迟锁定环由电压控制延迟电路形成，该延迟电路通过电压控制延迟延迟命令时钟，以将参考时钟提供给内部延迟锁定环路的延迟线。外延迟锁定环还包括相位检测器，其将命令时钟与由延迟线产生的序列中的一个时钟信号进行比较。外延迟锁定环因此将序列中的一个时钟信号锁定到命令时钟。结果，由延迟线产生的序列中的所有时钟信号相对于命令时钟的相位具有相应的预定相位。序列中的一个时钟信号由多路复用器选择，以在与命令数据位耦合到锁存器的延迟相对应的时间对命令数据锁存器进行时钟。

2. 发明授权

US07889593B2 Method and apparatus for generating a sequence of clock signals 有权
标题翻译：用于产生时钟信号序列的方法和装置
公开(公告)号：US07889593B2
公开(公告)日：2011-02-15
申请号：US11897837
申请日：2007-08-31
申请人： Ronnie M. Harrison
发明人： Ronnie M. Harrison
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/1078 , G11C7/109 , G11C7/222 , G11C8/08 , G11C8/10 , G11C11/4076 , G11C11/4093 , H03L7/07 , H03L7/0812 , H03L7/0891
摘要： A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The inner delay-locked loop includes a voltage controlled delay line that delays a reference clock applied to its input by a plurality of respective delays. Two of the clock signals in the sequence are applied to a phase detector so that the signals at the outputs of the delay line have predetermined phases relative to each other. The outer delay-locked loop is formed by a voltage controlled delay circuit that delays the command clock by a voltage controlled delay to provide the reference clock to the delay line of the inner delay-locked loop. The outer delay-locked loop also includes a phase detector that compares the command clock to one of the clock signals in the sequence generated by the delay line. The outer delay-locked loop thus locks one of the clock signals in the sequence to the command clock. As a result, all of the clock signals in the sequence generated by the delay line have respective predetermined phases relative to the phase of the command clock. One of the clock signals in the sequence is selected by a multiplexer to clock a command data latch at a time corresponding to the delay in coupling a command data bit to the latch.
摘要翻译：时钟发生器电路从主时钟信号产生彼此相位相位的时钟信号序列。时钟发生器由内部和外部延迟锁定环形成。内部延迟锁定环路包括电压控制延迟线，其延迟通过多个相应延迟施加到其输入的参考时钟。序列中的两个时钟信号被施加到相位检测器，使得延迟线的输出处的信号相对于彼此具有预定的相位。外部延迟锁定环由电压控制延迟电路形成，该延迟电路通过电压控制延迟延迟命令时钟，以将参考时钟提供给内部延迟锁定环路的延迟线。外延迟锁定环还包括相位检测器，其将命令时钟与由延迟线产生的序列中的一个时钟信号进行比较。外延迟锁定环因此将序列中的一个时钟信号锁定到命令时钟。结果，由延迟线产生的序列中的所有时钟信号相对于命令时钟的相位具有相应的预定相位。序列中的一个时钟信号由多路复用器选择，以在与命令数据位耦合到锁存器的延迟相对应的时间对命令数据锁存器进行时钟。

3. 发明授权

US07746959B2 Method and system for generating reference voltages for signal receivers 有权
标题翻译：用于产生信号接收机参考电压的方法和系统
公开(公告)号：US07746959B2
公开(公告)日：2010-06-29
申请号：US11433322
申请日：2006-05-11
申请人： Brent Keeth , Joo S. Choi , George E. Pax , Ronnie M. Harrison , David Ovard , Dragos Dimitriu , Troy A. Manning , Roy E. Greeff , Greg King , Brian Johnson
发明人： Brent Keeth , Joo S. Choi , George E. Pax , Ronnie M. Harrison , David Ovard , Dragos Dimitriu , Troy A. Manning , Roy E. Greeff , Greg King , Brian Johnson
IPC分类号： H04L25/06
CPC分类号： H04L25/062
摘要： A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.
摘要翻译：用于产生用于存储器件信号接收器的参考电压的方法和系统以校准模式或正常操作模式工作。在校准模式下，参考电压的幅度逐渐变化，并且数字信号图案在每个参考电压下耦合到接收器。分析接收机的输出以确定接收机是否可以在每个参考电压电平下准确地传递信号模式。记录允许接收器精确地通过信号图案的参考电压范围，并且在该范围的大致中点处计算最终参考电压。在正常操作期间将该最终参考电压施加到接收器。

4. 发明授权

US07145376B2 Method and circuitry for reducing duty cycle distortion in differential delay lines 有权
标题翻译：差分延迟线减少占空比失真的方法和电路
公开(公告)号：US07145376B2
公开(公告)日：2006-12-05
申请号：US10932668
申请日：2004-09-01
申请人： Ronnie M. Harrison , Brent Keeth
发明人： Ronnie M. Harrison , Brent Keeth
IPC分类号： H03H11/26
CPC分类号： H03K5/1565 , H03K5/133 , H03K2005/00208
摘要： A method and circuitry are provided for reducing duty cycle distortion in differential solid state delay lines. The differential solid state delay lines of the present invention include a plurality of delay line cells or stages connected in series. Because there may be asymmetry associated with the physical layout of each individual delay line cell or stage, it is advantageous to cross-connect every x stage of an n-stage delay line. Method, integrated circuit, electronic system and substrate embodiments including the differential solid state delay lines are also disclosed.
摘要翻译：提供了一种用于减小差分固态延迟线中的占空比失真的方法和电路。本发明的差分固态延迟线包括串联连接的多个延迟线单元或级。因为可能存在与每个单独的延迟线单元或级的物理布局相关联的不对称性，所以交叉连接n级延迟线的每个x级是有利的。还公开了包括差分固态延迟线的方法，集成电路，电子系统和衬底实施例。

5. 发明授权

US06680874B1 Delay lock loop circuit useful in a synchronous system and associated methods 失效
公开(公告)号：US06680874B1
公开(公告)日：2004-01-20
申请号：US10230750
申请日：2002-08-29
申请人： Ronnie M. Harrison
发明人： Ronnie M. Harrison
IPC分类号： G11C800
CPC分类号： G11C8/18 , H03K23/542 , H03K23/66 , H03L7/0814 , H03L7/085 , H03L7/0896 , H03L7/095 , H03L2207/18
摘要： A method and circuitry for a delay lock loop useful in synchronizing the accessing of a memory array with a system clock is disclosed. In a preferred embodiment, the delay lock loop includes a variable delay element. The delay of the variable delay element is initially set to a minimum delay value. The system clock is then frequency divided and sent to the variable delay element, the output of which will ultimately be used to access the memory array in a synchronized manner with the system clock. The frequency divided clock and the output of the variable delay element are input to a phase detector, which creates a control signal for adjusting the delay of the variable delay element. After the signals are determined to be locked by the phase detector, an undivided clock signal version of the clock signal is sent to the variable delay element, and a frequency divided version of the output of the variable delay element is sent to the phase detector in lieu of the previous output of the variable delay element.

6. 发明授权

US06011732A Synchronous clock generator including a compound delay-locked loop 失效
标题翻译：同步时钟发生器包括复合延迟锁定环
公开(公告)号：US06011732A
公开(公告)日：2000-01-04
申请号：US915185
申请日：1997-08-20
申请人： Ronnie M. Harrison , Brent Keeth
发明人： Ronnie M. Harrison , Brent Keeth
IPC分类号： G11C7/22 , G11C7/00
CPC分类号： G11C7/222 , G11C7/22
摘要： A synchronous clock generator is comprised of a delay-locked loop for producing a plurality of signals in response to an external clock signal. Each of the plurality of signals is delayed a predetermined period of time with respect to the external clock signal. A plurality of multiplexers is responsive to the plurality of signals for producing at least one clock signal in response to control signals input to the plurality of multiplexers. A clock driver is provided for driving the clock signal. A variable delay circuit is positioned to delay the external clock signal before input to the delay-locked loop. A compound feedback loop is responsive to certain of the plurality of signals for producing a control signal input to the variable delay circuit.
摘要翻译：同步时钟发生器包括用于响应于外部时钟信号产生多个信号的延迟锁定环路。多个信号中的每一个相对于外部时钟信号被延迟预定的时间段。响应于输入到多个多路复用器的控制信号，多个复用器响应多个信号以产生至少一个时钟信号。提供时钟驱动器来驱动时钟信号。可变延迟电路定位成在输入到延迟锁定环路之前延迟外部时钟信号。复合反馈回路响应于多个信号中的某些信号，以产生输入到可变延迟电路的控制信号。

7. 发明授权

US4062041A Input voltage controlled oscillator circuit for a television signal time base corrector 失效
标题翻译：用于电视信号时基校正器的输入压控振荡器电路
公开(公告)号：US4062041A
公开(公告)日：1977-12-06
申请号：US540025
申请日：1975-01-10
申请人： Michael W. Tallent , Lee E. Scaggs , Allan L. Swain , Ronnie M. Harrison , William B. Hendershot, III
发明人： Michael W. Tallent , Lee E. Scaggs , Allan L. Swain , Ronnie M. Harrison , William B. Hendershot, III
IPC分类号： H04N5/073 , H04N9/896 , H04N5/76 , H04N9/46
CPC分类号： H04N5/0736 , H04N9/896
摘要： An input voltage controlled oscillator circuit for a digital video time base corrector used to process television signals to remove time base errors introduced during signal recording, reproducing, or transmission. In the time base corrector, incoming video signals are converted from analog-to-digital form, temporarily stored in a memory unit at a clocking rate which varies in a manner generally proportional to the time base errors, and the stored signals are fetched at a standard clocking rate.The input voltage controlled oscillator circuit generates the clock signals for performing the analog-to-digital conversion and for storing the digital signals in the memory unit. The frequency of the clock signals varies in accordance with the time base errors in the composite sync and burst portions of the incoming video signals.The VCO circuit includes an oscillator for generating an integral multiple of the clock signal train, a first phase lock loop controlled by the frequency of successive composite sync pulses in the incoming video signal, a second phase lock loop controlled by the colorburst portion of successive lines of video information, a gated integrator coupled to the second phase lock loop for integrating successive ones of the VCO control signals generated by the second phase lock loop over a plurality of successive lines of video, and means for enabling the gated integrator during the colorburst portion of successive lines of video.The VCO circuit further includes means for disabling the gating means and the gated integrator when one of the colorburst portions of the video signals lies below a predetermined threshold.
摘要翻译：一种用于数字视频时基校正器的输入压控振荡器电路，用于处理电视信号以消除在信号记录，再现或传输期间引入的时基误差。在时基校正器中，输入的视频信号从模数形式转换，以与时基误差大致成比例的方式变化的时钟速率临时存储在存储器单元中，并且存储的信号以标准时钟速率。

8. 发明授权

US08433023B2 Method and apparatus for generating a phase dependent control signal 失效
标题翻译：用于产生相位相关控制信号的方法和装置
公开(公告)号：US08433023B2
公开(公告)日：2013-04-30
申请号：US13354702
申请日：2012-01-20
申请人： Ronnie M. Harrison
发明人： Ronnie M. Harrison
IPC分类号： H03D3/24 , H03L7/06 , G06F1/04
CPC分类号： G11C7/1072 , G11C7/222 , H03D13/004 , H03K5/131 , H03K5/133 , H03K5/135 , H03L7/07 , H03L7/0812 , H03L7/085 , H03L7/087 , H03L7/0896
摘要： A computer system with a phase detector that generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating select signals having duty cycles corresponding to the phase relationship between the clock edges of the first and second clock signals. The phase detector also includes a charge pump that receives select signals from the phase detector circuits and produces an increasing or decreasing control signal when the first and second clock signals do not have the predetermined phase relationship, and a non-varying control signal when the first and second clock signals do have the predetermined phase relationship. The delay value of a voltage-controlled delay circuit and the phase relationship between the first and second clock signals to a predetermined phase relationship are thereby adjusted.
摘要翻译：一种具有相位检测器的计算机系统，其根据第一和第二时钟信号之间的相位关系产生相位相关的控制信号。相位检测器包括接收第一和第二时钟信号的第一和第二相位检测器电路，并产生具有对应于第一和第二时钟信号的时钟沿之间的相位关系的占空比的选择信号。相位检测器还包括电荷泵，其在相位检测器电路接收选择信号，并且当第一和第二时钟信号不具有预定的相位关系时产生增加或减小的控制信号，当第一和第二时钟信号不具有预定的相位关系时，并且第二时钟信号具有预定的相位关系。由此调整压控延迟电路的延迟值和第一和第二时钟信号之间的相位关系到预定的相位关系。

9. 发明授权

US06952462B2 Method and apparatus for generating a phase dependent control signal 失效
公开(公告)号：US06952462B2
公开(公告)日：2005-10-04
申请号：US09991198
申请日：2001-11-20
申请人： Ronnie M. Harrison
发明人： Ronnie M. Harrison
IPC分类号： G11C7/10 , H03D13/00 , H03K5/13 , H03K5/135 , H03L7/07 , H03L7/081 , H03L7/085 , H03L7/087 , H03L7/089 , H04L12/50 , H03D3/00
CPC分类号： G11C7/1072 , G11C7/222 , H03D13/004 , H03K5/131 , H03K5/133 , H03K5/135 , H03L7/07 , H03L7/0812 , H03L7/085 , H03L7/087 , H03L7/0896
摘要： A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating select signals having duty cycles corresponding to the phase relationship between the clock edges of the first and second clock signals. The phase detector also includes a charge pump that receives select signals from the phase detector circuits and produces an increasing or decreasing control signal when the first and second clock signals do not have the predetermined phase relationship, and a non-varying control signal when the first and second clock signals do have the predetermined phase relationship. The control signal may be used to adjust the delay value of a voltage-controlled delay circuit in order to adjust the phase relationship between the first and second clock signals to have a predetermined phase relationship.

10. 发明授权

US06249165B1 Interlaced delay-locked loops for controlling memory-circuit timing 失效
标题翻译：用于控制存储器电路时序的隔行延迟锁定环路
公开(公告)号：US06249165B1
公开(公告)日：2001-06-19
申请号：US09259625
申请日：1999-02-26
申请人： Ronnie M. Harrison
发明人： Ronnie M. Harrison
IPC分类号： H03H1126
CPC分类号： H03L7/0805 , H03K5/133 , H03K5/135 , H03K5/26 , H03L7/07 , H03L7/0812 , H03L7/0896 , H03L7/10 , H03L2207/14
摘要： In digital circuits, such as memory circuits, it is sometimes necessary to delay one signal a precise amount of time relative a reference signal. One way to do this is to feed the reference signal to a delay-locked loop which generates a set of signals, each delayed a different amount relative the reference signal. However, as circuits get faster and faster, conventional delay-locked loops require the addition of extra interpolation circuitry to generate smaller delays, and thus consume considerable power and circuit space. Accordingly, the inventor devised a circuit which interlaces and synchronizes two delay-locked loops, each including a number of controllable delay elements linked in a chain. In one embodiment, the first loop produces a sequence of clock signals delayed an even number of delay periods relative a reference clock signal, and the second loop produces a sequence of clock signals delayed an odd number of delay periods relative the reference clock signal. In addition, the first and second loops are synchronized.
摘要翻译：在诸如存储器电路的数字电路中，有时需要相对于参考信号延迟一个信号精确的时间量。一种这样做的方法是将参考信号馈送到延迟锁定环路，该环路产生一组信号，每个信号相对于参考信号延迟不同的量。然而，随着电路越来越快，传统的延迟锁定环路需要额外的内插电路来产生更小的延迟，从而消耗相当大的功率和电路空间。因此，发明人设计了一种电路，其将两个延迟锁定环交错并同步，每个延迟锁定环包括链接在一起的多个可控延迟元件。在一个实施例中，第一循环产生相对于参考时钟信号延迟偶数个延迟周期的时钟信号序列，并且第二循环产生相对于参考时钟信号延迟奇数个延迟周期的时钟信号序列。此外，第一和第二循环是同步的。

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