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1. 发明授权

US08570078B2 CDR circuit 失效
标题翻译： CDR电路
公开(公告)号：US08570078B2
公开(公告)日：2013-10-29
申请号：US13425347
申请日：2012-03-20
申请人： Kiyohito Sato
发明人： Kiyohito Sato
IPC分类号： H03L7/06
CPC分类号： H03L7/0807 , H03L2207/14 , H04L7/0083 , H04L7/033
摘要： A CDR circuit includes a clock recovery circuit that generates, from an external clock, a first clock with which data of a received data signal is to be sampled and a second clock with which an edge of the received data signal is to be sampled and adjusts phases of the first clock and the second clock. The CDR circuit includes a phase detecting circuit that outputs a result of sampling of the received data signal with the first clock as a data sampling result and a result of sampling of the received data signal with the second clock as an edge sampling result. The CDR circuit includes a result comparing circuit that determines that a false lock condition has occurred and outputs a false lock condition detection signal if the edge sampling result matches with the data pattern.
摘要翻译： CDR电路包括时钟恢复电路，该时钟恢复电路从外部时钟产生要对其接收的数据信号的数据进行采样的第一时钟，以及接收的数据信号的边缘将被采样的第二时钟，并且调整第一个时钟和第二个时钟的相位。 CDR电路包括相位检测电路，其以第一时钟作为数据采样结果输出接收到的数据信号的采样结果，并且以第二时钟作为边缘采样结果对接收到的数据信号进行采样的结果。如果边缘采样结果与数据模式一致，则CDR电路包括确定发生错误锁定状态的结果比较电路，并输出假锁定状态检测信号。

2. 发明授权

US08350596B1 Clock loss detection circuit for PLL clock switchover 有权
标题翻译：用于PLL时钟切换的时钟丢失检测电路
公开(公告)号：US08350596B1
公开(公告)日：2013-01-08
申请号：US12748320
申请日：2010-03-26
申请人： Lip Kai Soh
发明人： Lip Kai Soh
IPC分类号： H03K5/19
CPC分类号： H03K5/1534 , H03K19/00346 , H03L2207/14
摘要： A clock loss detection circuit is presented. The clock loss detection has two edge detection circuits and a clock loss detect counter circuit. Each edge detection circuit includes a reset signal circuit that generates a reset signal in response to a transition of a clock signal, and the reset signal circuit is connected to a clock input of the edge detection circuit. Each edge detection circuit also has a multiplexer connected to the reset signal circuit, and another multiplexer connected to the clock input. The clock loss detect counter circuit is connected to the edge detection circuits so that the clock loss detect counter circuit receives the reset signal from the second edge detection circuit and the clock signal from the first edge detection circuit.
摘要翻译：提出了一种时钟损耗检测电路。时钟损耗检测具有两个边沿检测电路和一个时钟损耗检测计数器电路。每个边缘检测电路包括响应于时钟信号的转变而产生复位信号的复位信号电路，并且复位信号电路连接到边缘检测电路的时钟输入端。每个边缘检测电路还具有连接到复位信号电路的多路复用器，另一个多路复用器连接到时钟输入。时钟损耗检测计数器电路连接到边缘检测电路，使得时钟损耗检测计数器电路接收来自第二边缘检测电路的复位信号和来自第一边缘检测电路的时钟信号。

3. 发明授权

US08264261B2 Method and apparatus for the controlled delay of an input signal 有权
标题翻译：用于输入信号的受控延迟的方法和装置
公开(公告)号：US08264261B2
公开(公告)日：2012-09-11
申请号：US12891972
申请日：2010-09-28
申请人： Werner Grollitsch
发明人： Werner Grollitsch
IPC分类号： H03L7/06
CPC分类号： H03L7/0816 , H03L7/089 , H03L2207/14
摘要： An apparatus for the controlled delay of an input signal includes a signal input for receiving an input signal. The input signal is supplied to a delay line with a multiplicity of delay elements. Outputs of the delay elements allow respective differently delayed phase signals to be tapped off. Furthermore, a register line with a multiplicity of register elements is provided. The register elements are each associated with one of the delay elements. Each of the register elements has a reset input and a clock input. The reset inputs are coupled to the signal input. The outputs of the delay elements are each coupled to the clock input of the register element associated therewith.
摘要翻译：用于输入信号的受控延迟的装置包括用于接收输入信号的信号输入。输入信号被提供给具有多个延迟元件的延迟线。延迟元件的输出允许相应的不同延迟的相位信号被分接。此外，提供了具有多个寄存器元件的寄存器线。寄存器元件各自与延迟元件之一相关联。每个寄存器元件具有复位输入和时钟输入。复位输入耦合到信号输入端。延迟元件的输出各自耦合到与其相关联的寄存器元件的时钟输入。

4. 再颁专利

USRE43201E1 DLL circuit and camcorder using DLL circuit 有权
标题翻译： DLL电路和摄像机使用DLL电路
公开(公告)号：USRE43201E1
公开(公告)日：2012-02-21
申请号：US12056927
申请日：2008-03-27
申请人： Yasushi Matsuno
发明人： Yasushi Matsuno
IPC分类号： H03L7/00
CPC分类号： H03L7/0812 , H03L2207/14 , H04N5/23212 , H04N5/335
摘要： A DLL circuit which can prevent transition to a pseudo lock state is provided. The DLL circuit includes a delay stage to which a reference clock is input and in which variable delay elements D able to change an amount of delay are connected in a plurality of stages, a phase comparator (PH Comp) which compares the phase of the reference clock to the phase of one delay signal extracted from the delay stage, a delay control circuit which performs delay control of the delay element in the delay stage on the basis of the comparison result by the phase-comparison means, and a DFF which detects a phase relationship of at least two delay signals extracted from the delay stage to discriminate a state which is not a normal lock state and controls the delay control circuit to perform state transition to the normal lock state.
摘要翻译：提供了可以防止转换到伪锁定状态的DLL电路。 DLL电路包括输入参考时钟的延迟级，其中能够改变延迟量的可变延迟元件D以多级连接;相位比较器（PH Comp），其比较参考的相位时钟到从延迟级提取的一个延迟信号的相位，延迟控制电路，其基于相位比较装置的比较结果执行延迟级中的延迟元件的延迟控制;以及DFF，其检测从延迟级提取的至少两个延迟信号的相位关系来区分不是正常锁定状态的状态，并且控制延迟控制电路以执行到正常锁定状态的状态转换。

5. 发明申请

US20110074480A1 Method and Apparatus for the Controlled Delay of an Input Signal 有权
标题翻译：用于控制输入信号延迟的方法和装置
公开(公告)号：US20110074480A1
公开(公告)日：2011-03-31
申请号：US12891972
申请日：2010-09-28
申请人： Werner Grollitsch
发明人： Werner Grollitsch
IPC分类号： H03L7/06 , H03H11/26
CPC分类号： H03L7/0816 , H03L7/089 , H03L2207/14
摘要： An apparatus for the controlled delay of an input signal includes a signal input for receiving an input signal. The input signal is supplied to a delay line with a multiplicity of delay elements. Outputs of the delay elements allow respective differently delayed phase signals to be tapped off. Furthermore, a register line with a multiplicity of register elements is provided. The register elements are each associated with one of the delay elements. Each of the register elements has a reset input and a clock input. The reset inputs are coupled to the signal input. The outputs of the delay elements are each coupled to the clock input of the register element associated therewith.
摘要翻译：用于输入信号的受控延迟的装置包括用于接收输入信号的信号输入。输入信号被提供给具有多个延迟元件的延迟线。延迟元件的输出允许相应的不同延迟的相位信号被分接。此外，提供了具有多个寄存器元件的寄存器线。寄存器元件各自与延迟元件之一相关联。每个寄存器元件具有复位输入和时钟输入。复位输入耦合到信号输入端。延迟元件的输出各自耦合到与其相关联的寄存器元件的时钟输入。

6. 发明申请

US20110032009A1 DELAY LOCKED LOOP CIRCUIT 有权
标题翻译：延迟锁定环路
公开(公告)号：US20110032009A1
公开(公告)日：2011-02-10
申请号：US12844620
申请日：2010-07-27
申请人： Masaaki Iwane
发明人： Masaaki Iwane
IPC分类号： H03L7/085
CPC分类号： H03L7/0816 , H03L7/0891 , H03L7/0895 , H03L7/095 , H03L2207/14
摘要： A delay locked loop circuit comprising a VCDL which outputs a feedback clock by delaying an input clock in accordance with a magnitude of a control voltage, a phase comparator which detects a phase difference between the feedback clock and a reference clock by comparing the feedback clock with the reference clock, and outputs an Up-signal for raising the control voltage and a Down-signal for lowering the control voltage in accordance with the phase difference, a control voltage generation circuit which determines the control voltage in accordance with the Up-signal and the Down-signal, and outputs the control voltage to the VCDL, and a reset circuit which resets the phase comparator based on a logical OR between the reference clock and a first intermediate clock which is a signal obtained by delaying the input clock by the VCDL and is output before the feedback clock.
摘要翻译：一种延迟锁定环电路，包括通过根据控制电压的幅度延迟输入时钟来输出反馈时钟的VCDL;相位比较器，其通过将反馈时钟与参考时钟进行比较来检测反馈时钟与参考时钟之间的相位差参考时钟，并输出用于提高控制电压的Up信号和用于根据相位差降低控制电压的Down信号;控制电压发生电路，其根据Up信号确定控制电压;以及 Down信号，并将控制电压输出到VCDL;以及复位电路，其基于参考时钟与作为通过VCDL延迟输入时钟而获得的信号的第一中间时钟之间的逻辑或复位相位比较器并在反馈时钟之前输出。

7. 发明授权

US07366269B2 False lock detection circuit and false lock detection method, PLL circuit and clock data recovery method, communication device and communication method, and optical disk reproducing device and optical disk reproducing method 失效
标题翻译：假锁检测电路和假锁检测方法，PLL电路和时钟数据恢复方法，通信装置和通信方法以及光盘再现装置和光盘再现方法
公开(公告)号：US07366269B2
公开(公告)日：2008-04-29
申请号：US11108741
申请日：2005-04-19
申请人： Hiroki Ishida , Takashi Nishimura
发明人： Hiroki Ishida , Takashi Nishimura
IPC分类号： H04L7/00
CPC分类号： H03L7/095 , G11B20/18 , H03L7/087 , H03L7/113 , H03L7/18 , H03L2207/14 , H04L7/0083 , H04L7/044
摘要： Disclosed herein is a false lock detection circuit including: a data signal input section receiving an input of a data signal; a clock signal input section receiving an input of a clock signal generated from the data signal; a pattern detector obtaining the data signal on a basis of the clock signal, and detecting a data pattern in which adjacent pieces of data at at least three consecutive bits differ from each other; a phase period shift detector detecting a shift between periods of phases at a change point of the data signal and a change point of the clock signal; and a determining section determining whether a false lock has occurred on a basis of results of detection of the pattern detector and the phase period shift detector.
摘要翻译：这里公开了一种假锁定检测电路，包括：数据信号输入部，接收数据信号的输入; 时钟信号输入部分，接收从数据信号产生的时钟信号的输入; 模式检测器基于时钟信号获取数据信号，并且检测其中至少三个连续位相邻的相邻数据段彼此不同的数据模式; 相位周期移位检测器，检测在数据信号的变化点和时钟信号的变化点的相位周期之间的偏移; 以及确定部，其基于图案检测器和相位周期移位检测器的检测结果来确定是否发生了假锁。

8. 发明授权

US07268629B2 System and method for lock detection of a phase-locked loop circuit 失效
标题翻译：锁相环电路锁定检测系统及方法
公开(公告)号：US07268629B2
公开(公告)日：2007-09-11
申请号：US11137072
申请日：2005-05-25
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： H03L7/00
CPC分类号： H03L7/095 , H03L7/089 , H03L7/0895 , H03L2207/14 , Y10S331/02
摘要： Systems and methods for detecting phase-locked loop circuit lock. In particular, a lock detector configured to detect PLL stability for a user-defined period of time prior to asserting a PLL-lock-detected output. Stability may be indicated by a counter inserted into a PLL circuit and arranged between a phase-frequency detector and a charge pump. Because the counter value is acted upon by the phase-frequency detector, PLL lock is indicated by counter value stability. The digital counter value may be provided to a digital charge pump and a lock detector simultaneously. The lock detector includes registers and difference detectors to determine when the difference between counter values is below a user-defined tolerance. The lock detector may include a variable timer to avoid false indications of lock which may occur when counter values are sampled with the same frequency as a fluctuation frequency of the counter value.
摘要翻译：用于检测锁相环电路锁的系统和方法。特别地，锁定检测器被配置为在断言PLL锁定检测到的输出之前检测用户定义的时间段的PLL稳定性。稳定性可以由插入PLL电路中的计数器指示并且布置在相位频率检测器和电荷泵之间。由于计数器值由相位频率检测器作用，PLL锁定由计数器值稳定性指示。数字计数器值可以同时提供给数字电荷泵和锁定检测器。锁定检测器包括寄存器和差分检测器，用于确定计数器值之间的差异何时低于用户定义的公差。锁定检测器可以包括可变定时器，以避免在以与计数器值的波动频率相同的频率对计数器值进行采样时可能发生的锁定的错误指示。

9. 发明授权

US07072242B2 Semiconductor integrated circuit device 失效
公开(公告)号：US07072242B2
公开(公告)日：2006-07-04
申请号：US10965845
申请日：2004-10-18
申请人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
发明人： Yuichi Okuda , Masaru Kokubo , Yoshinobu Nakagome , Hideharu Yahata , Hiroki Miyashita
IPC分类号： G11C8/00
CPC分类号： H03L7/107 , G11C5/025 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/12 , G11C11/4076 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/12005 , H03L7/0814 , H03L7/0898 , H03L7/1072 , H03L2207/14
摘要： A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

10. 发明申请

US20060129869A1 Data de-skew method and system 失效
公开(公告)号：US20060129869A1
公开(公告)日：2006-06-15
申请号：US11218331
申请日：2005-09-01
申请人： Norm Hendrickson , Andrew Schmitt , Timothy Coe
发明人： Norm Hendrickson , Andrew Schmitt , Timothy Coe
IPC分类号： G06F1/12
CPC分类号： H03L7/0814 , H03L7/087 , H03L2207/14 , H04J3/04 , H04J3/0602 , H04L7/0337 , H04L7/04 , H04L25/14 , H04L69/14 , H04L69/22
摘要： Systems and methods for deskewing parallel data lines using at least one extra channel in parallel to the parallel data lines to carry data for comparing to data on the parallel data lines.

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