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    • 2. 发明授权
    • Processor-memory module performance acceleration in fabric-backplane enterprise servers
    • Fabric-backplane企业服务器中的处理器内存模块性能加速
    • US08868790B2
    • 2014-10-21
    • US11057036
    • 2005-02-12
    • Thomas Dean LovettSharad MehrotraCosmos NicolaouNakul Pratap SaraiyaShreyas B. ShahMyron H. WhiteRajesh K. JagannathanMangesh Shingane
    • Thomas Dean LovettSharad MehrotraCosmos NicolaouNakul Pratap SaraiyaShreyas B. ShahMyron H. WhiteRajesh K. JagannathanMangesh Shingane
    • G06F15/16H04L12/66H04L12/931H04L12/46H04L12/933H04L1/00
    • H04L49/10H04L1/0061H04L12/4645H04L49/00H04L49/357H04L49/45H04L49/602H04L49/70
    • A hybrid server and multi-layer switch system architecture, referred to hereinafter as the Enterprise Fabric (EF) architecture, forms the basis for a number of Enterprise Server (ES) chassis embodiments. Each ES embodiment generally includes one or more Processor Memory Modules (PMMs, each generally having one or more symmetric multiprocessor complexes), one or more Network Modules, and a System Control Module (SCM). The SCM includes a cellified switching-fabric core (SF) and a System Intelligence Module (SIM). Each PMM has one or more resident Virtual IO Controller (VIOC) adapters. Each VIOC is a specialized I/O controller that includes embedded layer-2 forwarding and filtering functions and tightly couples the PMM to the SF. Thus the layer-2 switch functionality within the ES chassis is distributed over all of the SCM, NM, and PMM modules. Through the use of VIOC/VNIC device drivers, host operating system software (Host O/S) running on the PMMs is presented with a plurality of Virtual Network Interface Cards (VNICs). In some embodiments, each VNIC behaves as a high-performance Ethernet interface at the full disposal of the Host O/S. In other embodiments, at least some of the VNICs behave as high-performance Fibre Channel Host Bus Adapters.
    • 以下称为企业​​架构(EF)架构的混合服务器和多层交换机系统架构构成了许多企业服务器(ES)机箱实施例的基础。 每个ES实施例通常包括一个或多个处理器存储器模块(PMM,每个通常具有一个或多个对称多处理器复合体),一个或多个网络模块和系统控制模块(SCM)。 SCM包括单元化交换矩阵核心(SF)和系统智能模块(SIM)。 每个PMM都有一个或多个驻留的虚拟IO控制器(VIOC)适配器。 每个VIOC是一个专门的I / O控制器,包括嵌入式二层转发和过滤功能,并将PMM紧密耦合到SF。 因此,ES机箱中的第2层交换机功能分布在所有SCM,NM和PMM模块上。 通过使用VIOC / VNIC设备驱动程序,在PMM上运行的主机操作系统软件(Host O / S)具有多个虚拟网络接口卡(VNIC)。 在一些实施例中,每个VNIC在主机O / S的完全处置时表现为高性能以太网接口。 在其他实施例中,至少一些VNIC表现为高性能光纤通道主机总线适配器。
    • 7. 发明申请
    • Enhanced Routing Grid System and Method
    • 增强路由网格系统和方法
    • US20090070726A1
    • 2009-03-12
    • US12062360
    • 2008-04-03
    • Sharad MehrotraParsotam T. PatelJoe T. RahmehJeanette N. Sutherland
    • Sharad MehrotraParsotam T. PatelJoe T. RahmehJeanette N. Sutherland
    • G06F17/50
    • G06F17/5077
    • Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for example, speed, manufacturability or noise tolerance. This cost information can be related to terrain costs as well as shape costs to provide multidimensional cost information for connections. Processing such higher information cost data is made more efficient with an additive process that is less demanding than a computationally intensive iterative multiplication process. Various methods are also disclosed for shifting and adjusting routing grids to improve use of available space or reduce run time in routing. In another embodiment, a parallel processing scheme is used to process multiple regions on multiple processors simultaneously without creating conflicts, that could arise, for example, when two processors try to route a trace on the same gridpoint.
    • 提供了路由系统和方法,其具有用于优化和评估网表连接的可能路由的各种策略。 在一个实施例中,数据结构或矩阵提供加权的成本相关数据,以评估连接或分段将对感兴趣的属性(例如速度,可制造性或噪声容限)提出的影响。 该成本信息可以与地形成本以及形状成本相关联,以提供用于连接的多维成本信息。 使用比计算密集型迭代乘法过程要求低的加法过程,处理这种更高信息成本数据变得更有效。 还公开了用于移动和调整路由网格以改进对可用空间的使用或减少路由中的运行时间的各种方法。 在另一个实施例中,使用并行处理方案来同时处理多个处理器上的多个区域而不会产生冲突,例如当两个处理器尝试在同一网格点上路由跟踪时可能出现冲突。
    • 8. 发明授权
    • Querying encrypted data in a relational database system
    • 查询关系数据库系统中的加密数据
    • US07500111B2
    • 2009-03-03
    • US10449421
    • 2003-05-30
    • Vahit Hakan HacigumusBalakrishna Raghavendra IyerSharad Mehrotra
    • Vahit Hakan HacigumusBalakrishna Raghavendra IyerSharad Mehrotra
    • H04K1/00H04L9/00G06F11/30G06F17/00G06F9/44G06F17/30
    • G06F17/30471G06F17/30501H04L9/0894
    • A client-server relational database system, wherein data from the client computer is encrypted by the client computer and hosted by the server computer, the encrypted data is operated upon by the server computer, using one or more operators selected from a group of operators comprising: (a) inequality logic operators, (b) aggregation operators, and (c) wildcard matching operators, to produce an intermediate results set, the intermediate results set is sent from the server computer to the client computer, and the intermediate results set is decrypted and filtered by the client computer to produce actual results. The group of operators is limited because the encrypted results set, when decrypted, includes inaccuracies therein. The client computer applies a set of correction procedures to the decrypted results set to remove the inaccuracies therein.
    • 一种客户机 - 服务器关系数据库系统,其中来自客户端计算机的数据由客户端计算机加密并由服务器计算机托管,加密数据由服务器计算机使用从一组运营商中选择的一个或多个运营商来操作,该运营商包括 :(a)不等式逻辑运算符,(b)聚合运算符和(c)通配符匹配运算符,产生中间结果集,中间结果集从服务器计算机发送到客户端计算机,中间结果集为 由客户端计算机进行解密和过滤,以产生实际结果。 操作员组是有限的,因为在解密时加密的结果集包含不准确的内容。 客户端计算机对解密的结果集应用一组校正过程以消除其中的不准确之处。
    • 10. 发明授权
    • Apparatus and method for queueing structures in a multi-level non-blocking cache subsystem
    • 在多级非阻塞缓存子系统中排队结构的装置和方法
    • US06226713B1
    • 2001-05-01
    • US09009815
    • 1998-01-21
    • Sharad Mehrotra
    • Sharad Mehrotra
    • G06F1208
    • G06F12/0897G06F12/0859
    • A multi-level cache and method for operation thereof is presented for processing multiple cache system accesses simultaneously and handling the interactions between the queues of the cache levels. The cache unit includes a non-blocking cache receiving data access requests from a functional unit in a processor, and a miss queue storing entries corresponding to data access requests not serviced by the non-blocking cache. A victim queue stores entries of the non-blocking cache which have been evicted from the non-blocking cache, while a write queue buffers write requests into the non-blocking cache. Controller logic is provided for controlling interaction between the miss queue and the victim queue. Controller logic is also provided for controlling interaction between the miss queue and the write queue. Controller logic is also provided for controlling interaction between the victim queue and the miss queue for processing cache misses.
    • 提出了一种多级缓存及其操作方法,用于同时处理多个缓存系统访问并处理高速缓存级别队列之间的交互。 高速缓存单元包括接收来自处理器中的功能单元的数据访问请求的非阻塞高速缓存,以及存储对应于未被非阻塞高速缓存服务的数据访问请求的条目的未命中队列。 受害者队列存储已经从非阻塞缓存中逐出的非阻塞缓存的条目,而写入队列将写入请求缓冲到非阻塞高速缓存中。 提供控制器逻辑用于控制未命中队列和受害队列之间的交互。 还提供控制器逻辑以控制未命中队列与写队列之间的交互。 还提供控制器逻辑,用于控制受害队列与未命中队列之间的交互以处理高速缓存未命中。