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1. 发明授权

US08482959B2 Method of programming, erasing and repairing a memory device 有权
标题翻译：编程，擦除和修复存储设备的方法
公开(公告)号：US08482959B2
公开(公告)日：2013-07-09
申请号：US13324759
申请日：2011-12-13
申请人： Swaroop Kaza , Sameer Haddad
发明人： Swaroop Kaza , Sameer Haddad
IPC分类号： G11C11/00 , G11C11/36
CPC分类号： G11C11/5685 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2213/15 , G11C2213/79
摘要： A method of repairing a memory device is provided. If an erase process is unsuccessful, a repair process is performed. A programmed state of the memory device is determined, A subsequent erase process dependent on the programmed state is performed. Also, a method of programming and erasing a memory device is provided. The memory device includes first and second electrodes and a switching layer therebetween. A first on-state resistance characteristic of the memory device is provided in programming the memory device by application of a first voltage to the gate of a transistor in series with the memory device. Other on-state resistance characteristics of the memory device, different from the first on-state resistance characteristic, may be provided by application of other voltages, different from the first voltage, to the gate of the transistor.
摘要翻译：提供了修复存储器件的方法。如果擦除过程不成功，则执行修复过程。确定存储器件的编程状态。执行取决于编程状态的后续擦除过程。另外，提供了编程和擦除存储器件的方法。存储器件包括第一和第二电极以及它们之间的开关层。提供存储器件的第一导通电阻特性，通过将第一电压施加到与存储器件串联的晶体管的栅极来对存储器件进行编程。可以通过将不同于第一电压的其他电压施加到晶体管的栅极来提供不同于第一导通电阻特性的存储器件的其他导通电阻特性。

2. 发明申请

US20120276706A1 DAMASCENE METAL-INSULATOR-METAL (MIM) DEVICE IMPROVED SCALEABILITY 有权
标题翻译：大金属金属绝缘体 - 金属（MIM）器件改进的可扩展性
公开(公告)号：US20120276706A1
公开(公告)日：2012-11-01
申请号：US13529284
申请日：2012-06-21
申请人： Suzette K. PANGRLE , Steven AVANZINO , Sameer HADDAD , Michael VANBUSKIRK , Manuj RATHOR , James XIE , Kevin SONG , Christie MARRIAN , Bryan CHOO , Fei WANG , Jeffery A. SHIELDS
发明人： Suzette K. PANGRLE , Steven AVANZINO , Sameer HADDAD , Michael VANBUSKIRK , Manuj RATHOR , James XIE , Kevin SONG , Christie MARRIAN , Bryan CHOO , Fei WANG , Jeffery A. SHIELDS
IPC分类号： H01L21/02
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146 , H01L45/1633 , H01L45/1675 , H01L45/1683
摘要： A present method of fabricating a memory device includes the steps of providing a dielectric layer;, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body Filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.
摘要翻译：本发明的制造存储器件的方法包括以下步骤：提供电介质层;在电介质层中提供开口，在开口中提供第一导电体，在开口中提供开关体，第一导电体和开关体填充开口，并在开关体上设置第二导电体。在替代实施例中，在第一介电层上提供第二电介质层，并且开关体设置在第二电介质层的开口中。

3. 发明授权

US08232175B2 Damascene metal-insulator-metal (MIM) device with improved scaleability 有权
标题翻译：大马士革金属绝缘体金属（MIM）装置，具有改进的可扩展性
公开(公告)号：US08232175B2
公开(公告)日：2012-07-31
申请号：US11521204
申请日：2006-09-14
申请人： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael VanBuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffrey A. Shields
发明人： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael VanBuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffrey A. Shields
IPC分类号： H01L21/20
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146 , H01L45/1633 , H01L45/1675 , H01L45/1683
摘要： A present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.
摘要翻译：制造存储器件的现有方法包括以下步骤：提供电介质层，在介电层中提供开口，在开口中提供第一导电体，在开口中提供开关体，第一导电体和开关体填充物并且在开关体上设置第二导电体。在替代实施例中，在第一介电层上提供第二电介质层，并且开关体设置在第二电介质层的开口中。

4. 发明授权

US08084770B2 Test structures for development of metal-insulator-metal (MIM) devices 有权
标题翻译：金属 - 绝缘体 - 金属（MIM）器件的开发测试结构
公开(公告)号：US08084770B2
公开(公告)日：2011-12-27
申请号：US12313089
申请日：2008-11-17
申请人： Steven Avanzino , Suzette K. Pangrle , Manuj Rathor , An Chen , Sameer Haddad , Nicholas Tripsas , Matthew Buynoski
发明人： Steven Avanzino , Suzette K. Pangrle , Manuj Rathor , An Chen , Sameer Haddad , Nicholas Tripsas , Matthew Buynoski
IPC分类号： H01L29/10
CPC分类号： H01L22/32
摘要： In the present electronic test structure comprising, a conductor is provided, overlying a substrate. An electronic device overlies a portion of the conductor and includes a first electrode connected to the conductor, a second electrode, and an insulating layer between the first and second electrodes. A portion of the conductor is exposed for access thereto.
摘要翻译：在本发明的电子测试结构中，提供了覆盖基板的导体。电子器件覆盖导体的一部分，并且包括连接到导体的第一电极，第二电极和在第一和第二电极之间的绝缘层。导体的一部分被暴露以便进入其中。

5. 发明申请

US20110253968A1 RESISTIVE MEMORY ARRAY USING P-I-N DIODE SELECT DEVICE AND METHODS OF FABRICATION THEREOF 有权
标题翻译：使用P-I-N二极管选择器件的电阻存储器阵列及其制造方法
公开(公告)号：US20110253968A1
公开(公告)日：2011-10-20
申请号：US13165652
申请日：2011-06-21
申请人： Seungmoo CHOI , Sameer HADDAD
发明人： Seungmoo CHOI , Sameer HADDAD
IPC分类号： H01L29/868 , H01L21/02 , H01L45/00 , H01L21/329
CPC分类号： H01L27/2409 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C17/06 , H01L21/2256 , H01L27/24 , H01L27/2463 , H01L29/6609 , H01L29/868 , H01L45/1608
摘要： An electronic structure includes a resistive memory device, and a P-I-N diode in operative association with the resistive memory device. A plurality of such electronic structures are used in a resistive memory array, with the P-I-N diodes functioning as select devices in the array. Methods are provided for fabricating such resistive memory device—P-I-N diode structures.
摘要翻译：电子结构包括电阻性存储器件和与电阻式存储器件可操作地相关联的P-I-N二极管。在电阻式存储器阵列中使用多个这样的电子结构，其中P-I-N二极管用作阵列中的选择器件。提供了制造这种电阻式存储器件-P-I-N二极管结构的方法。

6. 发明授权

US07830015B2 Memory device with improved data retention 有权
标题翻译：具有改善数据保留性能的内存设备
公开(公告)号：US07830015B2
公开(公告)日：2010-11-09
申请号：US11089708
申请日：2005-03-25
申请人： Zhida Lan , Sameer Haddad , Steven Avanzino
发明人： Zhida Lan , Sameer Haddad , Steven Avanzino
IPC分类号： H01L23/48
CPC分类号： G11C13/0009 , G11C2213/11 , G11C2213/15 , G11C2213/34 , G11C2213/56 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/1641 , H01L2924/0002 , H01L2924/00
摘要： The present memory device include first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrodes and into which ions from the passive layer may be provided, and from which the ions may be provided into the passive layer. The active layer is made up of a base material and an impurity therein. The combined the material and impurity have a lower diffusion coefficient than the base material alone.
摘要翻译：本存储器件包括第一和第二电极，第一和第二电极之间的无源层以及第一和第二电极之间的有源层，并且可以提供来自被动层的离子，并且可以从其提供离子进入被动层。有源层由基材和杂质构成。材料和杂质的组合具有比单独的基材更低的扩散系数。

7. 发明授权

US07384800B1 Method of fabricating metal-insulator-metal (MIM) device with stable data retention 有权
标题翻译：制造金属绝缘体金属（MIM）器件的方法，具有稳定的数据保留
公开(公告)号：US07384800B1
公开(公告)日：2008-06-10
申请号：US11633942
申请日：2006-12-05
申请人： Steven Avanzino , Sameer Haddad , An Chen , Yi-Ching Jean Wu , Suzette K. Pangrle , Jeffrey A. Shields
发明人： Steven Avanzino , Sameer Haddad , An Chen , Yi-Ching Jean Wu , Suzette K. Pangrle , Jeffrey A. Shields
IPC分类号： H01L21/00
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1633 , H01L45/1675 , Y10T29/49002
摘要： In the method of fabricating a metal-insulator-metal (MIM) device, a first electrode of α-Ta is provided. The Ta of the first electrode is oxidized to form a Ta2O5 layer on the first electrode. A second electrode of β-Ta is provided on the Ta2O5 layer. Such a device exhibits strong data retention, along with resistance to performance degradation under high temperatures.
摘要翻译：在制造金属 - 绝缘体 - 金属（MIM）器件的方法中，提供了α-Ta的第一电极。在第一电极上氧化第一电极的Ta以形成Ta 2 O 5 O 5层。 β-Ta的第二电极设置在Ta 2 O 5层上。这种器件表现出强大的数据保持性，同时耐高温下的性能降解。

8. 发明申请

US20080132068A1 Damascene metal-insulator-metal (MIM) device 有权
标题翻译：大马士革金属绝缘子金属（MIM）器件
公开(公告)号：US20080132068A1
公开(公告)日：2008-06-05
申请号：US11633929
申请日：2006-12-05
申请人： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael VanBuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffrey A. Shields
发明人： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael VanBuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffrey A. Shields
IPC分类号： H01L21/44
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/122 , H01L45/1233 , H01L45/146 , H01L45/1666
摘要： The present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening in the dielectric layer, providing a switching body in the opening, and providing a second conductive body in the opening.
摘要翻译：制造存储器件的本方法包括以下步骤：提供电介质层，在电介质层中提供开口，在电介质层的开口中提供第一导电体，在开口中提供开关体，并提供第二导电体在开口处。

9. 发明授权

US06737703B1 Memory array with buried bit lines 失效
标题翻译：内存阵列带埋线
公开(公告)号：US06737703B1
公开(公告)日：2004-05-18
申请号：US10095512
申请日：2002-03-12
申请人： Richard Fastow , Sameer Haddad , Yu Sun
发明人： Richard Fastow , Sameer Haddad , Yu Sun
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115
摘要： In a memory device, a substrate has a plurality of source/drain regions in the substrate. Between the source/drain regions are trenches filled with oxide. Individual bit lines in the form of conductive regions are provided in the substrate, each bit line being under and running along the oxide in a trench. Each bit line connects to source/drain regions by means of connecting conductive regions extending from that bit line to source/drain regions.
摘要翻译：在存储器件中，衬底在衬底中具有多个源极/漏极区域。在源极/漏极区之间是填充有氧化物的沟槽。导电区域形式的单个位线设置在衬底中，每个位线沿着沟槽中的氧化物在下面并且沿着其延伸。每个位线通过将从该位线延伸的导电区域连接到源极/漏极区域而连接到源极/漏极区域。

10. 发明授权

US06583009B1 Innovative narrow gate formation for floating gate flash technology 有权
标题翻译：用于浮栅闪存技术的创新窄门形成
公开(公告)号：US06583009B1
公开(公告)日：2003-06-24
申请号：US10178106
申请日：2002-06-24
申请人： Angela T. Hui , Kelwin Ko , Hiroyuki Kinoshita , Sameer Haddad , Yu Sun
发明人： Angela T. Hui , Kelwin Ko , Hiroyuki Kinoshita , Sameer Haddad , Yu Sun
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115 , Y10S438/952
摘要： The present invention relates to a method of forming a stacked gate flash memory cell and comprises forming a tunnel oxide layer, a first conductive layer, an interpoly dielectric layer, and a second conductive layer in succession over a semiconductor substrate. The method further comprises forming a sacrificial layer over the second conductive layer, and patterning the sacrificial layer to form a sacrificial layer feature having at least one lateral sidewall edge associated therewith. A sidewall spacer is then formed against the lateral sidewall edge of the sacrificial layer, wherein the spacer has a width associated therewith, and the patterned sacrificial layer feature is removed. Finally, the second conductive layer, the interpoly dielectric and the first conductive layer are patterned using the spacer as a hard mask, and defining the stacked gate, wherein a width of the stacked gate is a function of the spacer width.
摘要翻译：本发明涉及一种形成层叠栅极闪存单元的方法，包括在半导体衬底上连续形成隧道氧化物层，第一导电层，多晶硅间介质层和第二导电层。该方法还包括在第二导电层上形成牺牲层，以及图案化牺牲层以形成具有与其相关联的至少一个侧向侧壁边缘的牺牲层特征。然后在牺牲层的横向侧壁边缘上形成侧壁间隔物，其中间隔件具有与其相关联的宽度，并且去除图案化的牺牲层特征。最后，使用间隔物作为硬掩模来图案化第二导电层，多晶硅间电介质和第一导电层，并且限定堆叠栅极，其中堆叠栅极的宽度是间隔物宽度的函数。

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