专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09112035B2 Semiconductor substrate, field-effect transistor, integrated circuit, and method for fabricating semiconductor substrate 有权
标题翻译：半导体衬底，场效晶体管，集成电路以及半导体衬底的制造方法
公开(公告)号：US09112035B2
公开(公告)日：2015-08-18
申请号：US13410872
申请日：2012-03-02
申请人： Hisashi Yamada , Masahiko Hata , Masafumi Yokoyama , Mitsuru Takenaka , Shinichi Takagi , Tetsuji Yasuda , Hideki Takagi , Yuji Urabe
发明人： Hisashi Yamada , Masahiko Hata , Masafumi Yokoyama , Mitsuru Takenaka , Shinichi Takagi , Tetsuji Yasuda , Hideki Takagi , Yuji Urabe
IPC分类号： H01L29/02 , H01L29/786 , H01L21/762 , H01L29/49 , H01L29/51 , H01L29/66
CPC分类号： H01L29/78681 , H01L21/76251 , H01L21/76256 , H01L29/4966 , H01L29/517 , H01L29/66742
摘要： A semiconductor substrate includes a substrate, an insulating layer, and a semiconductor layer. The insulating layer is over and in contact with the substrate. The insulating layer includes at least one of an amorphous metal oxide and an amorphous metal nitride. The semiconductor layer is over and in contact with the insulating layer. The semiconductor layer is formed by crystal growth.
摘要翻译：半导体衬底包括衬底，绝缘层和半导体层。绝缘层在衬底上并与衬底接触。绝缘层包括无定形金属氧化物和无定形金属氮化物中的至少一种。半导体层在绝缘层上方并与之接触。半导体层通过晶体生长形成。

2. 发明授权

US08518543B2 DLC-coated sliding member and method for producing the same 有权
标题翻译： DLC涂层滑动构件及其制造方法
公开(公告)号：US08518543B2
公开(公告)日：2013-08-27
申请号：US12866196
申请日：2009-02-03
申请人： Makoto Kano , Takahiro Horiuchi , Shinichi Takagi , Masao Kumagai , Eiji Shimodaira , Yoshio Miyasaka
发明人： Makoto Kano , Takahiro Horiuchi , Shinichi Takagi , Masao Kumagai , Eiji Shimodaira , Yoshio Miyasaka
IPC分类号： B32B9/00
CPC分类号： C23C24/04 , C23C16/0281 , C23C16/26 , C23C28/044 , C23C28/046 , F16C33/043 , F16C2206/04 , F16C2240/54
摘要： A sliding member is produced by forming hardening layers with two-layered structure on surface of a substrate metal with a Vickers hardness of not more than Hv300, such as aluminum or magnesium alloy for example, and then forming a DLC film having surface roughness defined as maximum height roughness Rz of 1 to 10 μm further on the hardening layers. The above-described hardening layers are composed of a first hardening layer dispersed with heavy metal particles, preferably made of tungsten and/or tantalum in the substrate metal, and a second hardening layer formed under the first hardening layer.
摘要翻译：通过在例如铝或镁合金等维氏硬度不高于Hv300的基板金属的表面上形成具有两层结构的硬化层，然后形成表面粗糙度定义为硬化层上的最大高度粗糙度Rz为1〜10μm。上述硬化层由在基板金属中分散有优选由钨和/或钽制成的重金属颗粒的第一硬化层和在第一硬化层下形成的第二硬化层构成。

3. 发明授权

US08431459B2 Semiconductor wafer, semiconductor device, and method of manufacturing a semiconductor device 有权
标题翻译：半导体晶片，半导体器件以及半导体器件的制造方法
公开(公告)号：US08431459B2
公开(公告)日：2013-04-30
申请号：US12934233
申请日：2009-03-26
申请人： Mitsuru Takenaka , Shinichi Takagi , Masahiko Hata , Osamu Ichikawa
发明人： Mitsuru Takenaka , Shinichi Takagi , Masahiko Hata , Osamu Ichikawa
IPC分类号： H01L21/00
CPC分类号： H01L29/7787 , H01L21/28264 , H01L29/205 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/78648 , H01L29/78681
摘要： It is an objective of the present invention to form a favorable interface between an oxide layer and a group 3-5 compound semiconductor using a practical and simple method.Provided is a semiconductor wafer comprising a first semiconductor layer that is a group 3-5 compound not containing arsenic and that lattice matches or pseudo-lattice matches with InP; and a second semiconductor layer that is formed to contact the first semiconductor layer, is a group 3-5 compound semiconductor layer that lattice matches or pseudo-lattice matches with InP, and can be selectively oxidized relative to the first semiconductor layer. Also provided is a semiconductor device comprising a first semiconductor layer that is a group 3-5 compound not containing arsenic and that lattice matches or pseudo-lattice matches with InP; an oxide layer formed by selectively oxidizing, relative to the first semiconductor layer, at least a portion of a second semiconductor layer that is a group 3-5 compound formed to contact the first semiconductor layer and that lattice matches or pseudo-lattice matches with InP; and a control electrode that adds an electric field to a channel formed in the first semiconductor layer.
摘要翻译：本发明的目的是使用实用和简单的方法在氧化物层和3-5族化合物半导体之间形成良好的界面。提供了包括第一半导体层的半导体晶片，其是不含砷的组3-5化合物，并且晶格匹配或伪晶格与InP匹配; 和形成为与第一半导体层接触的第二半导体层是与InP晶格匹配或伪晶格匹配的组3-5化合物半导体层，并且可相对于第一半导体层选择性地氧化。还提供了一种半导体器件，其包括第一半导体层，其是不含砷的组3-5化合物，并且晶格匹配或伪晶格与InP匹配; 通过相对于第一半导体层选择性地氧化形成为与第一半导体层接触的组3-5化合物的第二半导体层的至少一部分，并且晶格匹配或伪晶格匹配的InP形成的氧化物层 ; 以及将电场与形成在第一半导体层中的沟道相加的控制电极。

4. 发明申请

US20120228673A1 FIELD-EFFECT TRANSISTOR, SEMICONDUCTOR WAFER, METHOD FOR PRODUCING FIELD-EFFECT TRANSISTOR AND METHOD FOR PRODUCING SEMICONDUCTOR WAFER 失效
标题翻译：场效应晶体管，半导体晶体管，生产场效应晶体管的方法和生产半导体晶体管的方法
公开(公告)号：US20120228673A1
公开(公告)日：2012-09-13
申请号：US13413216
申请日：2012-03-06
申请人： Masahiko HATA , Hisashi Yamada , Noboru Fukuhara , Shinichi Takagi , Mitsuru Takenaka , Masafumi Yokoyama , Tetsuji Yasuda , Yuji Urabe , Noriyuki Miyata , Taro Itatani , Hiroyuki Ishii
发明人： Masahiko HATA , Hisashi Yamada , Noboru Fukuhara , Shinichi Takagi , Mitsuru Takenaka , Masafumi Yokoyama , Tetsuji Yasuda , Yuji Urabe , Noriyuki Miyata , Taro Itatani , Hiroyuki Ishii
IPC分类号： H01L29/78 , H01L21/336 , H01L21/20
CPC分类号： H01L29/7786 , H01L21/26553 , H01L29/4966 , H01L29/517 , H01L29/66318 , H01L29/66522
摘要： Provided is a field-effect transistor including a gate insulating layer, a first semiconductor crystal layer in contact with the gate insulating layer, and a second semiconductor crystal layer lattice-matching or pseudo lattice-matching the first semiconductor crystal layer. Here, the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer are arranged in the order of the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer, the first semiconductor crystal layer is made of Inx1Ga1-x1Asy1P1-y1 (0
摘要翻译：提供了一种场效应晶体管，其包括栅极绝缘层，与栅极绝缘层接触的第一半导体晶体层和第二半导体晶体层与第一半导体晶体层的晶格匹配或伪晶格匹配。这里，栅绝缘层，第一半导体晶体层和第二半导体晶体层按栅极绝缘层，第一半导体晶体层和第二半导体晶体层的顺序排列，第一半导体晶体层被制成的In x Ga 1-x As y 1 P 1-y 1（0

5. 发明申请

US20110147805A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110147805A1
公开(公告)日：2011-06-23
申请号：US13037049
申请日：2011-02-28
申请人： Toshifumi Irisawa , Shinichi Takagi , Naoharu Sugiyama
发明人： Toshifumi Irisawa , Shinichi Takagi , Naoharu Sugiyama
IPC分类号： H01L29/04
CPC分类号： H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/1054 , H01L29/42392 , H01L29/7842 , H01L29/785 , H01L29/78684
摘要： A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a direction.
摘要翻译：半导体器件包括绝缘体层和具有n沟道的n沟道MIS晶体管和具有ap沟道的pMIS晶体管，其形成在绝缘体层上，其中n沟道MIS晶体管的n沟道由Si 层在沟道长度方向上具有单轴拉伸应变，p沟道MIS晶体管的p沟道由沟道长度方向上具有单轴压缩应变的SiGe或Ge层形成，并且沟道长度方向 n沟道MIS晶体管和p沟道MIS晶体管是<110>方向。

6. 发明授权

US07622773B2 Semiconductor device including multi-gate metal-insulator-semiconductor (MIS) transistor 有权
标题翻译：包括多栅极金属 - 绝缘体 - 半导体（MIS）晶体管的半导体器件
公开(公告)号：US07622773B2
公开(公告)日：2009-11-24
申请号：US11705450
申请日：2007-02-13
申请人： Toshifumi Irisawa , Toshinori Numata , Shinichi Takagi , Naoharu Sugiyama
发明人： Toshifumi Irisawa , Toshinori Numata , Shinichi Takagi , Naoharu Sugiyama
IPC分类号： H01L27/12
CPC分类号： H01L29/7853 , H01L29/66636 , H01L29/66795 , H01L29/78687
摘要： In a semiconductor device including a multi-gate MIS transistor having a channel on a plurality of surfaces, a gate electrode is formed on a gate insulating film on side surfaces of an island-like semiconductor layer formed along a given direction on an insulating film, and source/drain electrodes are formed in contact with the semiconductor layer. The semiconductor layer has a plurality of side surfaces along the given direction. All angles formed by adjacent side surfaces are larger than 90°. A section perpendicular to the given direction is vertically and horizontally symmetrical.
摘要翻译：在包括在多个表面上具有沟道的多栅极MIS晶体管的半导体器件中，在绝缘膜上沿着给定方向形成的岛状半导体层的侧表面上的栅极绝缘膜上形成栅电极，并且源极/漏极形成为与半导体层接触。半导体层具有沿给定方向的多个侧表面。由相邻侧面形成的所有角度大于90°。垂直于给定方向的部分垂直和水平对称。

7. 发明授权

US07507634B2 Method for fabricating a localize SOI in bulk silicon substrate including changing first trenches formed in the substrate into unclosed empty space by applying heat treatment 有权
标题翻译：用于制造体硅衬底中的定位SOI的方法，包括通过施加热处理将衬底中形成的第一沟槽改变为未封闭的空间
公开(公告)号：US07507634B2
公开(公告)日：2009-03-24
申请号：US11812490
申请日：2007-06-19
申请人： Tsutomu Sato , Mie Matsuo , Ichiro Mizushima , Yoshitaka Tsunashima , Shinichi Takagi
发明人： Tsutomu Sato , Mie Matsuo , Ichiro Mizushima , Yoshitaka Tsunashima , Shinichi Takagi
IPC分类号： H01L21/764 , H01L27/12
CPC分类号： H01L27/10805 , B82Y20/00 , G02B6/122 , G02B6/1225 , G02B2006/12097 , H01L21/3247 , H01L21/7624 , H01L21/76283 , H01L21/76289 , H01L21/764 , H01L21/84 , H01L27/10894 , H01L27/10897 , H01L27/12 , H01L27/1203 , H01L29/0657 , H01L29/7842 , H01L29/78603 , H01L29/78639
摘要： To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate.
摘要翻译：通过在半导体衬底的表面上二维地形成沟槽，然后对半导体衬底进行热处理，将多个沟槽改变为一个平坦的空间。

8. 发明授权

US07313292B2 Optical component using optical transmission element joining metal holder 有权
标题翻译：使用光传输元件接合金属支架的光学部件
公开(公告)号：US07313292B2
公开(公告)日：2007-12-25
申请号：US10941940
申请日：2004-09-16
申请人： Yoshihiro Hashimoto , Ken Matsuoka , Shinichi Takagi , Katsunori Suzuki , Tetsutsugu Hamano
发明人： Yoshihiro Hashimoto , Ken Matsuoka , Shinichi Takagi , Katsunori Suzuki , Tetsutsugu Hamano
IPC分类号： G02B6/12 , G02B6/32 , G02B6/02
CPC分类号： G02B7/025 , G02B7/008 , G02B7/028
摘要： An optical component comprises an optical transmission element (e.g., an optical lens) whose circumferential wall partially joins a metal holder via a joining material (e.g., a low melting point glass), wherein stress is normally applied to the optical transmission element in a compression direction when joining the metal holder. The optical transmission element is inserted into a through hole of the metal holder, and the joining material is kept in a bank actualized by a tapered portion formed in proximity to one end of the through hole of the metal holder. This prevents tensile stress from being applied to the optical transmission element; thus, it is possible to avoid the occurrence of cracks and separations in the optical transmission element; and it is possible to avoid the occurrence of errors in optical characteristics, regardless of variations of the environmental temperature, so that, the optical component is improved in reliability.
摘要翻译：光学部件包括光学传输元件（例如，光学透镜），其周壁通过接合材料（例如，低熔点玻璃）部分地连接金属保持器，其中应力通常以压缩方式施加到光传输元件连接金属支架时的方向。光传输元件插入到金属保持器的通孔中，并且接合材料保持在由金属保持器的通孔的一端附近形成的锥形部分实现的堤岸中。这防止了拉伸应力施加到光传输元件上; 因此，可以避免在光传输元件中发生裂纹和分离; 并且不管环境温度的变化如何，可以避免出现光学特性的误差，从而提高了光学部件的可靠性。

9. 发明授权

US07235456B2 Method of making empty space in silicon 有权
标题翻译：在硅中制造空白空间的方法
公开(公告)号：US07235456B2
公开(公告)日：2007-06-26
申请号：US11340594
申请日：2006-01-27
申请人： Tsutomu Sato , Mie Matsuo , Ichiro Mizushima , Yoshitaka Tsunashima , Shinichi Takagi
发明人： Tsutomu Sato , Mie Matsuo , Ichiro Mizushima , Yoshitaka Tsunashima , Shinichi Takagi
IPC分类号： H01L21/764 , H01L27/12
CPC分类号： H01L27/10805 , B82Y20/00 , G02B6/122 , G02B6/1225 , G02B2006/12097 , H01L21/3247 , H01L21/7624 , H01L21/76283 , H01L21/76289 , H01L21/764 , H01L21/84 , H01L27/10894 , H01L27/10897 , H01L27/12 , H01L27/1203 , H01L29/0657 , H01L29/7842 , H01L29/78603 , H01L29/78639
摘要： To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate.
摘要翻译：通过在半导体衬底的表面上二维地形成沟槽，然后对半导体衬底进行热处理，将多个沟槽改变为一个平坦的空间。

10. 发明授权

US07217958B2 Feed through structure for optical semiconductor package 有权
标题翻译：光学半导体封装的馈通结构
公开(公告)号：US07217958B2
公开(公告)日：2007-05-15
申请号：US11542230
申请日：2006-10-04
申请人： Hiroshi Aruga , Shinichi Takagi , Kiyohide Sakai
发明人： Hiroshi Aruga , Shinichi Takagi , Kiyohide Sakai
IPC分类号： H01L33/00
CPC分类号： G02B6/4292 , G02B6/4201 , G02B6/4204 , G02B6/4206 , G02B6/421 , G02B6/4279 , H01L2224/48091 , H01S5/02212 , H01S5/02216 , H01S5/02248 , H01S5/02284 , H01S5/0427 , H01S5/06226 , H01L2924/00014
摘要： Includes a stem with a hole, a dielectric sealed into the hole of the stem and including a pair of pin insertion holes, and a pair of high frequency signal pins that penetrate and fit into the pair of pin insertion holes of the dielectric, and constituting differential lines connected to an optical semiconductor element.
摘要翻译：包括具有孔的杆，密封在杆的孔中的电介质，并且包括一对针插入孔和一对穿透并配合到电介质的一对针插入孔中的高频信号针，并且构成连接到光学半导体元件的差分线。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式