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1. 发明授权

US06560624B1 Method of executing each of division and remainder instructions and data processing device using the method 失效
标题翻译：使用该方法执行每个分割和余数指令和数据处理设备的方法
公开(公告)号：US06560624B1
公开(公告)日：2003-05-06
申请号：US09477001
申请日：2000-01-03
申请人： Sugako Otani , Hiroyuki Kondo
发明人： Sugako Otani , Hiroyuki Kondo
IPC分类号： G06F752
CPC分类号： G06F7/535 , G06F9/3001 , G06F9/3016 , G06F9/30167 , G06F9/325 , G06F2207/3816 , G06F2207/5352
摘要： A data processing device comprises an instruction decoding unit for decoding a code of either a division instruction or a remainder instruction applied thereto, the instruction code having a size field for storing data size information. When a control unit receives a decoded result from the instruction decoding unit, the decoded result indicating the data size information stored in the size field of the instruction code, it presets a number of times that one loop iteration comprised of steps required for executing either the division instruction or the remainder instruction is to be carried out, based on the data size information. An ALU disposed within an arithmetic unit performs the loop iteration for either the division instruction or the remainder instruction only the number of times preset by the control unit.
摘要翻译：数据处理装置包括：指令解码单元，用于解码分配指令或应用于其的余数指令的代码，所述指令代码具有用于存储数据大小信息的大小字段。当控制单元从指令解码单元接收到解码结果时，指示存储在指令代码的大小字段中的数据大小信息的解码结果，它预设一次循环迭代的次数，该循环迭代包括执行任一将根据数据大小信息执行除法指令或余数指令。设置在算术单元内的ALU对分割指令或余数指令执行循环迭代，仅执行由控制单元预设的次数。

2. 发明申请

US20100299751A1 MICROCOMPUTER HAVING A PROTECTION FUNCTION IN A REGISTER 有权
标题翻译：在注册机中具有保护功能的微型计算机
公开(公告)号：US20100299751A1
公开(公告)日：2010-11-25
申请号：US12783252
申请日：2010-05-19
申请人： Sugako OTANI , Hiroyuki Kondo
发明人： Sugako OTANI , Hiroyuki Kondo
IPC分类号： G06F12/14 , G06F9/30
CPC分类号： G06F9/30123 , G06F9/30054 , G06F9/30138 , G06F9/30189 , G06F9/3861
摘要： A control unit controls execution of an instruction according to a decode result of an instruction code. A GRA register stores an access attribute for each of the plurality of general-purpose registers. A mode storage unit stores modes for controlling an operation of a CPU. When the control unit makes a request for access to the general-purpose register, register access allowance determining circuit determines whether the access to the general-purpose register in question is to be allowed or not, depending on the access attribute stored in the GRA register and the mode stored in the mode storage unit. Therefore, the number of the general-purpose registers used corresponding to the mode can be changed, and efficiency of use of the general-purpose registers can be optimized.
摘要翻译：控制单元根据指令代码的解码结果控制指令的执行。 GRA寄存器存储多个通用寄存器中的每一个的访问属性。模式存储单元存储用于控制CPU的操作的模式。当控制单元请求访问通用寄存器时，寄存器访问允许确定电路根据存储在GRA寄存器中的访问属性来确定是否允许访问通用寄存器以及存储在模式存储单元中的模式。因此，可以改变与模式对应使用的通用寄存器的数量，并且可以优化通用寄存器的使用效率。

3. 发明申请

US20130326539A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20130326539A1
公开(公告)日：2013-12-05
申请号：US14000188
申请日：2012-02-20
申请人： Sugako Otani , Hiroyuki Kondo
发明人： Sugako Otani , Hiroyuki Kondo
IPC分类号： G06F9/54
CPC分类号： G06F9/54 , G06F11/2007 , G06F11/3024 , G06F11/3089 , G06F11/3476 , G06F11/348 , Y02D10/34
摘要： A semiconductor device includes first and second central processing units (0, 3) and a set of monitoring registers (60) provided inside or outside the second central processing unit (3). Information representing an internal state of the first central processing unit (0) is transferred from the first central processing unit (0) to the set of monitoring registers (60) during execution of a program, and the set of monitoring registers (60) holds such transferred information. The set of monitoring registers (60) is mapped in a memory space of the second central processing unit (3).
摘要翻译：半导体器件包括设置在第二中央处理单元（3）内部或外部的第一和第二中央处理单元（0,3）和一组监视寄存器（60）。表示第一中央处理单元（0）的内部状态的信息在执行程序期间从第一中央处理单元（0）传送到监视寄存器组（60），并且该组监视寄存器（60）保持这样的转移信息。监视寄存器（60）的集合被映射到第二中央处理单元（3）的存储器空间中。

4. 发明授权

US06463520B1 Processor for executing instruction codes of two different lengths and device for inputting the instruction codes 失效
标题翻译：用于执行两种不同长度的指令代码的处理器和用于输入指令代码的装置
公开(公告)号：US06463520B1
公开(公告)日：2002-10-08
申请号：US08811005
申请日：1997-03-04
申请人： Sugako Otani , Shunichi Iwata
发明人： Sugako Otani , Shunichi Iwata
IPC分类号： G06E1500
CPC分类号： G06F9/30145 , G06F9/3005 , G06F9/30149 , G06F9/30152 , G06F9/3016 , G06F9/30167 , G06F9/30181 , G06F9/322
摘要： Exemplary embodiments of the present invention are directed toward a technique which facilitates the process instruction codes in processor. According to the present invention, a memory device is provided which comprises a plurality of 2N-bit word boundaries, where N is greater than or equal to one. The processor of the present invention executes instruction codes of a 2N-bit length and a N-bit length. The instruction codes are stored in the memory device is such a way that the 2-N bit word boundaries contains either a single 2N-bit instruction code or two N-bit instruction codes. The most significant bit of each instruction code serves as a instruction format identifier which controls the execution (or decoding) sequence of the instruction codes. As a result, only two transfer paths from an instruction fetch portion to an instruction decode portion of the processor are necessary thereby reducing the hardware requirement of the processor and increasing system throughput.
摘要翻译：本发明的示例性实施例涉及促进处理器中的处理指令代码的技术。根据本发明，提供一种包括多个2N位字边界的存储器件，其中N大于或等于1。本发明的处理器执行2N位长度和N位长度的指令代码。指令码存储在存储器件中，使得2-N位字边界包含单个2N位指令代码或两个N位指令代码。每个指令代码的最高有效位用作控制指令代码的执行（或解码）序列的指令格式标识符。结果，仅需要从处理器的指令提取部分到指令解码部分的两个传送路径，从而减少处理器的硬件需求并提高系统吞吐量。

5. 发明授权

US06209079B1 Processor for executing instruction codes of two different lengths and device for inputting the instruction codes 有权
标题翻译：用于执行两种不同长度的指令代码的处理器和用于输入指令代码的装置
公开(公告)号：US06209079B1
公开(公告)日：2001-03-27
申请号：US09562643
申请日：2000-05-01
申请人： Sugako Otani , Shunichi Iwata
发明人： Sugako Otani , Shunichi Iwata
IPC分类号： G06F930
CPC分类号： G06F9/30145 , G06F9/3005 , G06F9/30149 , G06F9/30152 , G06F9/3016 , G06F9/30167 , G06F9/30181 , G06F9/322
摘要： For a processor having instruction codes of two instruction lengths (16 bits and 32 bits), methods of locating the instruction codes are limited to two types: (1) two 16-bit instruction codes are stored within 32-bit word boundaries, and (2) a single 32-bit instruction code is stored intactly within the 32-bit word boundaries. A branch destination address is specified only on the 32-bit word boundary. The MSB of each instruction code serves as a 1-bit instruction length identifier for controlling the execution sequence of the instruction codes. This provides two transfer paths from an instruction fetch portion to an instruction decode portion within the processor, achieving reduction in code side and in the amount of hardware and, accordingly, the increase in operating speed.
摘要翻译：对于具有两个指令长度（16位和32位）的指令代码的处理器，定位指令代码的方法被限制为两种类型：（1）两个16位指令代码存储在32位字边界内，并且（ 2）单个32位指令代码完整地存储在32位字边界内。分支目的地址仅在32位字边界上指定。每个指令代码的MSB用作1位指令长度标识符，用于控制指令代码的执行顺序。这提供了从处理器内的指令获取部分到指令解码部分的两个传送路径，实现了代码侧的减少和硬件的数量以及相应的操作速度的提高。

6. 发明授权

US08789169B2 Microcomputer having a protection function in a register 有权
标题翻译：微机在寄存器中具有保护功能
公开(公告)号：US08789169B2
公开(公告)日：2014-07-22
申请号：US12783252
申请日：2010-05-19
申请人： Sugako Otani , Hiroyuki Kondo
发明人： Sugako Otani , Hiroyuki Kondo
IPC分类号： G06F21/00
CPC分类号： G06F9/30123 , G06F9/30054 , G06F9/30138 , G06F9/30189 , G06F9/3861
摘要： A control unit controls execution of an instruction according to a decode result of an instruction code. A GRA register stores an access attribute for each of the plurality of general-purpose registers. A mode storage unit stores modes for controlling an operation of a CPU. When the control unit makes a request for access to the general-purpose register, register access allowance determining circuit determines whether the access to the general-purpose register in question is to be allowed or not, depending on the access attribute stored in the GRA register and the mode stored in the mode storage unit. Therefore, the number of the general-purpose registers used corresponding to the mode can be changed, and efficiency of use of the general-purpose registers can be optimized.
摘要翻译：控制单元根据指令代码的解码结果控制指令的执行。 GRA寄存器存储多个通用寄存器中的每一个的访问属性。模式存储单元存储用于控制CPU的操作的模式。当控制单元请求访问通用寄存器时，寄存器访问允许确定电路根据存储在GRA寄存器中的访问属性来确定是否允许访问通用寄存器以及存储在模式存储单元中的模式。因此，可以改变与模式对应使用的通用寄存器的数量，并且可以优化通用寄存器的使用效率。

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