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1. 发明授权

US08604725B2 Semiconductor device and drive method of electrostatic actuator 失效
标题翻译：静电执行器的半导体器件和驱动方法
公开(公告)号：US08604725B2
公开(公告)日：2013-12-10
申请号：US13719924
申请日：2012-12-19
申请人： Tamio Ikehashi , Takayuki Miyazaki , Hiroyuki Hara
发明人： Tamio Ikehashi , Takayuki Miyazaki , Hiroyuki Hara
IPC分类号： H01L41/04
CPC分类号： H02N1/006
摘要： According to one embodiment, a semiconductor device includes an electrostatic actuator including first and second lower electrodes, an upper electrode, and an insulating film provided between the upper electrode and the first and second lower electrodes, the first lower electrode and upper electrode configuring a first variable capacitance element, the second lower electrode and upper electrode configuring a second variable capacitance element, a first fixed capacitance element connected to the first lower electrode, a second fixed capacitance element connected to the second lower electrode, and a detection circuit connected to the upper electrode and configured to detect a charge amount stored in the insulating film.
摘要翻译：根据一个实施例，半导体器件包括静电致动器，其包括第一和第二下部电极，上部电极和设置在上部电极与第一和第二下部电极之间的绝缘膜，第一下部电极和上部电极构成第一可变电容元件，第二下电极和构成第二可变电容元件的上电极，连接到第一下电极的第一固定电容元件，连接到第二下电极的第二固定电容元件，以及连接到上电极的检测电路电极，并且被配置为检测存储在绝缘膜中的电荷量。

2. 发明授权

US08274324B2 Electrostatic actuator apparatus 有权
标题翻译：静电执行机构
公开(公告)号：US08274324B2
公开(公告)日：2012-09-25
申请号：US13444953
申请日：2012-04-12
申请人： Tamio Ikehashi
发明人： Tamio Ikehashi
IPC分类号： G05F1/10 , H01G5/00
CPC分类号： H02M3/07 , H02M3/44 , H02N1/006
摘要： According to one embodiment, an electrostatic actuator apparatus includes a first voltage generation circuit configured to generate a first voltage, a first switch connected between the first voltage generation circuit and a first node, a second voltage generation circuit configured to generate a second voltage, a second switch connected between the second voltage generation circuit and a second node, a capacitor connected between the first node and the second node, an electrostatic actuator having a drive electrode connected to the first node, and a control circuit configured to perform an operation of sequentially turning on the first switch, turning off the first switch and turning on the second switch when the electrostatic actuator is driven.
摘要翻译：根据一个实施例，静电致动器装置包括：第一电压产生电路，被配置为产生第一电压;连接在第一电压产生电路和第一节点之间的第一开关;被配置为产生第二电压的第二电压产生电路; 连接在第二电压产生电路和第二节点之间的第二开关，连接在第一节点和第二节点之间的电容器，具有连接到第一节点的驱动电极的静电致动器，以及被配置为执行顺序地操作的控制电路打开第一个开关，当静电执行器被驱动时，关闭第一个开关并打开第二个开关。

3. 发明申请

US20100237929A1 VOLTAGE GENERATING CIRCUIT FOR ELECTROSTATIC MEMS ACTUATOR 有权
标题翻译：用于静电MEMS致动器的电压发生电路
公开(公告)号：US20100237929A1
公开(公告)日：2010-09-23
申请号：US12649809
申请日：2009-12-30
申请人： Tamio Ikehashi
发明人： Tamio Ikehashi
IPC分类号： H03K17/687
CPC分类号： H02M3/07 , H02N1/006
摘要： A plurality of capacitors each of which has a first and a second electrode. A plurality of first switches is connected between the first electrodes of the plurality of capacitors and a first power supply. A plurality of second switches is connected between the second electrodes of the plurality of capacitors and a second power supply. A plurality of resistances each of which is connected between the first electrode of one of the plurality of capacitors and the second electrode of another capacitor and which connect the plurality of capacitors in series, a voltage for driving an actuator being output from the last stage of the plurality of capacitors connected in series.
摘要翻译：多个电容器，每个电容器具有第一和第二电极。多个第一开关连接在多个电容器的第一电极和第一电源之间。多个第二开关连接在多个电容器的第二电极和第二电源之间。多个电阻被连接在多个电容器中的一个电容器的第一电极和另一个电容器的第二电极之间并且串联连接多个电容器，用于驱动致动器的电压从最后阶段多个电容串联连接。

4. 发明授权

US07317652B2 Semiconductor device, nonvolatile semiconductor memory, system including a plurality of semiconductor devices or nonvolatile semiconductor memories, electric card including semiconductor device or nonvolatile semiconductor memory, and electric device with which this electric card can be used 有权
标题翻译：半导体器件，非易失性半导体存储器，包括多个半导体器件或非易失性半导体存储器的系统，包括半导体器件或非易失性半导体存储器的电卡，以及可以使用该电卡的电子器件
公开(公告)号：US07317652B2
公开(公告)日：2008-01-08
申请号：US11203393
申请日：2005-08-12
申请人： Kazushige Kanda , Kenichi Imamiya , Hiroshi Nakamura , Ken Takeuchi , Tamio Ikehashi
发明人： Kazushige Kanda , Kenichi Imamiya , Hiroshi Nakamura , Ken Takeuchi , Tamio Ikehashi
IPC分类号： G11C5/14
CPC分类号： G11C5/143 , G11C17/18
摘要： A semiconductor device of this invention includes a first circuit for initializing a predetermined circuit in accordance with the level of a power source voltage, a second circuit for controlling the output from the first circuit by activation or deactivation, and an activation control circuit for activating or deactivating the second circuit in accordance with external input.
摘要翻译：本发明的半导体器件包括用于根据电源电压的电平初始化预定电路的第一电路，用于通过激活或去激活来控制来自第一电路的输出的第二电路，以及用于激活或去激活的激活控制电路，根据外部输入禁用第二电路。

5. 发明申请

US20070138608A1 Device with beam structure, and semiconductor device 失效
标题翻译：具有光束结构的器件和半导体器件
公开(公告)号：US20070138608A1
公开(公告)日：2007-06-21
申请号：US11438690
申请日：2006-05-23
申请人： Tamio Ikehashi
发明人： Tamio Ikehashi
IPC分类号： H01L23/495
CPC分类号： B81B3/0072 , H01G5/18 , H01L41/0933 , H01L41/094 , H01L2924/0002 , H01L2924/00
摘要： A device with a beam structure includes a substrate, an anchor and a cavity which are provided on and over the substrate, respectively, and a beam structure which is provided on the anchor and over the cavity, extends in a first direction and includes a plurality of convex portions and a plurality of concave portions, each of the convex portions having such a stress gradient as to provide a convex warp, and each of the concave portions having such a stress gradient as to provide a concave warp. The convex portions and the concave portions are alternately repeatedly arranged.
摘要翻译：具有光束结构的装置包括分别设置在基板上和上方的基板，锚和空腔，并且设置在锚固件上并在空腔上方的梁结构在第一方向上延伸并且包括多个的凸部和多个凹部，每个凸部具有提供凸翘曲的应力梯度，并且每个凹部具有提供凹弯曲的应力梯度。凸部和凹部交替重复配置。

6. 发明申请

US20050125595A1 Non-volatile semiconductor memory 失效
公开(公告)号：US20050125595A1
公开(公告)日：2005-06-09
申请号：US11032165
申请日：2005-01-11
申请人： Ken Takeuchi , Tamio Ikehashi , Toshihiko Himeno
发明人： Ken Takeuchi , Tamio Ikehashi , Toshihiko Himeno
IPC分类号： G06F12/16 , G11C16/02 , G11C16/06 , G11C16/20 , G11C29/04 , G06F13/00
CPC分类号： G11C16/20
摘要： A non-volatile semiconductor memory device includes a memory cell array having a plurality of non-volatile memory cells, a decode circuit configured to decode address data as input thereto to select a memory cell from the memory cell array, and a data sense circuit configured to detect and amplify the data of the selected memory cell of the memory cell array. The memory cell array includes an initial setup data region with initial setup data and status data being programmed thereinto. The initial setup data is used for determination of memory operating conditions, and the status data indicates whether the initial setup data region is presently normal or not in functionality.

7. 发明申请

US20050052930A1 Semiconductor memory device including page latch circuit 有权
标题翻译：半导体存储器件包括页锁存电路
公开(公告)号：US20050052930A1
公开(公告)日：2005-03-10
申请号：US10968303
申请日：2004-10-20
申请人： Junichiro Noda , Tamio Ikehashi , Kenichi Imamiya
发明人： Junichiro Noda , Tamio Ikehashi , Kenichi Imamiya
IPC分类号： G11C29/02 , G11C11/34
CPC分类号： G11C29/02
摘要： A semiconductor memory device having a data latch circuit has plural bit lines to which a reprogrammable memory cell is connected, a data bus on which data is transferred, a latch circuit latching the data transferred on the data bus, a read out circuit connected to the data bus, and a data transfer circuit group to directly transfer the data latched in the latch circuit to the read out circuit without transferring it to the memory cell.
摘要翻译：具有数据锁存电路的半导体存储器件具有连接有可再编程存储单元的多个位线，数据总线上传送数据，锁存电路锁存数据总线上传送的数据，读出电路连接到数据总线和数据传输电路组，将锁存在锁存电路中的数据直接传送到读出电路，而不将其传送到存储单元。

8. 发明授权

US06674318B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US06674318B2
公开(公告)日：2004-01-06
申请号：US10231082
申请日：2002-08-30
申请人： Kazushige Kanda , Tamio Ikehashi , Ken Takeuchi , Kenichi Imamiya
发明人： Kazushige Kanda , Tamio Ikehashi , Ken Takeuchi , Kenichi Imamiya
IPC分类号： G05F110
CPC分类号： G11C7/062
摘要： A semiconductor integrated circuit includes a limiter circuit for outputting a voltage determining flag in order to set a boosted voltage level of a booster circuit to be a predetermined value, and a monitoring circuit for monitoring a monitoring node of the limiter circuit to output a monitoring signal for the stabilization of a boosted voltage to a first external terminal. The monitoring circuit detects a first level change of the voltage determining flag from “H” to “L” after the starting of the operation of the limiter circuit, by means of a comparator, to which an external power supply voltage and external reference voltage supplied from second and third external terminals are given, and thereafter, outputs a monitoring signal for holding a constant logical level during the operation of the limiter circuit. In order to provide a voltage trimming function, a voltage intended to be set in an external terminal may be given from the outside to deactivate a feedback system of the limiter circuit to operate a resistance value of the limiter circuit to detect and store a limiter flag. Thus, there is provided a semiconductor integrated circuit capable of simply monitoring the output voltage state of an internal power supply circuit by the external terminal and easily trimming an internal voltage.
摘要翻译：半导体集成电路包括限幅电路，用于输出电压确定标志，以便将升压电路的升压电压设定为预定值;以及监视电路，用于监视限幅器电路的监视节点以输出监视信号用于稳定第一外部端子的升压电压。监控电路通过比较器检测在限制器电路的操作开始之后电压确定标志从“H”到“L”的第一电平变化，供给外部电源电压和外部参考电压给出第二和第三外部端子，然后在限幅器电路的操作期间输出用于保持恒定逻辑电平的监视信号。为了提供电压调整功能，可以从外部给出旨在设置在外部端子中的电压以去激活限幅器电路的反馈系统，以操作限幅器电路的电阻值以检测和存储限幅器标志。因此，提供了能够简单地通过外部端子监视内部电源电路的输出电压状态并容易地修整内部电压的半导体集成电路。

9. 发明授权

US06646930B2 Non-volatile semiconductor memory 失效
公开(公告)号：US06646930B2
公开(公告)日：2003-11-11
申请号：US09968983
申请日：2001-10-03
申请人： Ken Takeuchi , Tamio Ikehashi , Toshihiko Himeno
发明人： Ken Takeuchi , Tamio Ikehashi , Toshihiko Himeno
IPC分类号： G11C700
CPC分类号： G11C16/20
摘要： A non-volatile semiconductor memory device includes a memory cell array having a plurality of non-volatile memory cells, a decode circuit configured to decode address data as input thereto to select a memory cell from the memory cell array, and a data sense circuit configured to detect and amplify the data of the selected memory cell of the memory cell array. The memory cell array includes an initial setup data region with initial setup data and status data being programmed thereinto. The initial setup data is used for determination of memory operating conditions, and the status data indicates whether the initial setup data region is presently normal or not in functionality.

10. 发明授权

US06507518B2 Fail number detecting circuit of flash memory 有权
公开(公告)号：US06507518B2
公开(公告)日：2003-01-14
申请号：US09985017
申请日：2001-11-01
申请人： Koji Hosono , Tamio Ikehashi , Tomoharu Tanaka , Kenichi Imamiya , Hiroshi Nakamura , Ken Takeuchi
发明人： Koji Hosono , Tamio Ikehashi , Tomoharu Tanaka , Kenichi Imamiya , Hiroshi Nakamura , Ken Takeuchi
IPC分类号： G11C1606
CPC分类号： G11C16/3445 , G11C16/3436 , G11C16/3459
摘要： A semiconductor memory device includes a memory cell array, a plurality of latch circuits, first circuit, second circuit and third circuit. The memory cell array has electrically rewritable nonvolatile memory cells arranged therein. The plurality of latch circuits temporarily hold data read out from the memory cell array. The first circuit is configured to generate a first current varying in proportion to “1” or “0” of binary logical data of one end of the plurality of latch circuits. The second circuit is configured to generate a second preset current. The third circuit is configured to compare the first current with the second current. The number of “1” or “0” of binary logical data of one end of the plurality of latch circuits is detected based on the result of comparison between the first current and the second current.

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