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1. 发明授权

US07774580B2 Array processor having reconfigurable data transfer capabilities 有权
标题翻译：阵列处理器具有可重新配置的数据传输能力
公开(公告)号：US07774580B2
公开(公告)日：2010-08-10
申请号：US11077561
申请日：2005-03-11
申请人： Miyoshi Saito , Hisanori Fujisawa , Hideki Yoshizawa , Tetsu Tanizawa , Ichiro Kasama , Tetsuo Kawano , Kazuaki Imafuku , Hiroshi Furukawa , Shiro Uriu , Mitsuharu Wakayoshi
发明人： Miyoshi Saito , Hisanori Fujisawa , Hideki Yoshizawa , Tetsu Tanizawa , Ichiro Kasama , Tetsuo Kawano , Kazuaki Imafuku , Hiroshi Furukawa , Shiro Uriu , Mitsuharu Wakayoshi
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F15/8007
摘要： A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.
摘要翻译：可重构操作装置由能够通过使用一段给定的第一配置数据并且彼此同时操作的多个操作单元组成，能够重新配置自身; RAMs 构成操作装置所需的各种处理器元件; 互连所述操作单元，所述RAM和所述不同处理器元件的资源间网络，以与所述资源的位置和种类无关的统一传送时间在连接到其之间的资源之间执行数据传输，并且可通过使用给定的第二配置数据来重新配置; 以及存储第一和第二配置数据的配置存储器。配置数据从外部存储装置加载到配置存储器上，并且基于从多个操作单元可获得的数据，将第一和第二配置数据以适当的顺序和定时提供给可重构处理器资源。

2. 发明申请

US20060010306A1 Reconfigurable operation apparatus 有权
标题翻译：可重构操作装置
公开(公告)号：US20060010306A1
公开(公告)日：2006-01-12
申请号：US11077561
申请日：2005-03-11
申请人： Miyoshi Saito , Hisanori Fujisawa , Hideki Yoshizawa , Tetsu Tanizawa , Ichiro Kasama , Tetsuo Kawano , Kazuaki Imafuku , Hiroshi Furukawa , Shiro Uriu , Mitsuharu Wakayoshi
发明人： Miyoshi Saito , Hisanori Fujisawa , Hideki Yoshizawa , Tetsu Tanizawa , Ichiro Kasama , Tetsuo Kawano , Kazuaki Imafuku , Hiroshi Furukawa , Shiro Uriu , Mitsuharu Wakayoshi
IPC分类号： G06F15/00
CPC分类号： G06F15/8007
摘要： A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.
摘要翻译：可重构操作装置由能够通过使用一段给定的第一配置数据并且彼此同时操作的多个操作单元组成，能够重新配置自身; RAMs 构成操作装置所需的各种处理器元件; 互连所述操作单元，所述RAM和所述不同处理器元件的资源间网络，以与所述资源的位置和种类无关的统一传送时间在连接到其之间的资源之间执行数据传输，并且可通过使用给定的第二配置数据来重新配置; 以及存储第一和第二配置数据的配置存储器。配置数据从外部存储装置加载到配置存储器上，并且基于从多个操作单元可获得的数据，将第一和第二配置数据以适当的顺序和定时提供给可重构处理器资源。

3. 发明授权

US07822888B2 Data buffer control which controls selection of path and operation of data buffer, based on stored configuration information 有权
标题翻译：数据缓存控制，根据存储的配置信息控制数据缓冲区的路径选择和操作
公开(公告)号：US07822888B2
公开(公告)日：2010-10-26
申请号：US10973094
申请日：2004-10-26
申请人： Miyoshi Saito , Hisanori Fujisawa , Ichiro Kasama , Tetsuo Kawano , Kazuaki Imafuku , Hiroshi Furukawa , Shiro Uriu , Mitsuharu Wakayoshi
发明人： Miyoshi Saito , Hisanori Fujisawa , Ichiro Kasama , Tetsuo Kawano , Kazuaki Imafuku , Hiroshi Furukawa , Shiro Uriu , Mitsuharu Wakayoshi
IPC分类号： G06F3/00 , G06F5/00 , G06F13/00 , G06F13/28
CPC分类号： G06F15/7867
摘要： An operation apparatus includes a sequencer controlling states of a plurality of operation devices and a configuration memory storing therein configuration information as setting information for each state in the operation device. In the operation apparatus, a path which requires a data buffer and another path which requires no such a data buffer are provided for inputting data to the operation device, a data buffer control part is provided for controlling selection from these two paths and operation of the data buffer, and contents of path selection and operation control of the data buffer carried out by the data buffer control part are set according to the configuration information.
摘要翻译：一种操作装置，包括：控制多个操作装置的状态的定序器和配置存储器，其中配置信息作为操作装置中的每个状态的设置信息。在操作装置中，提供需要数据缓冲器的路径和不需要这样的数据缓冲器的另一路径，用于向操作装置输入数据，提供数据缓冲器控制部分，用于控制从这两个路径的选择和操作数据缓冲器，以及由数据缓冲器控制部分执行的数据缓冲器的路径选择和操作控制的内容根据配置信息来设置。

4. 发明申请

US20060004940A1 Operation apparatus, operation apparatus control method, program and computer readable information recording medium 有权
标题翻译：操作装置，操作装置控制方法，程序和计算机可读信息记录介质
公开(公告)号：US20060004940A1
公开(公告)日：2006-01-05
申请号：US10973094
申请日：2004-10-26
申请人： Miyoshi Saito , Hisanori Fujisawa , Ichiro Kasama , Tetsuo Kawano , Kazuaki Imafuku , Hiroshi Furukawa , Shiro Uriu , Mitsuharu Wakayoshi
发明人： Miyoshi Saito , Hisanori Fujisawa , Ichiro Kasama , Tetsuo Kawano , Kazuaki Imafuku , Hiroshi Furukawa , Shiro Uriu , Mitsuharu Wakayoshi
IPC分类号： G06F12/00
CPC分类号： G06F15/7867
摘要： An operation apparatus includes a sequencer controlling states of a plurality of operation devices and a configuration memory storing therein configuration information as setting information for each state in the operation device. In the operation apparatus, a path which requires a data buffer and another path which requires no such a data buffer are provided for inputting data to the operation device, a data buffer control part is provided for controlling selection from these two paths and operation of the data buffer, and contents of path selection and operation control of the data buffer carried out by the data buffer control part are set according to the configuration information.
摘要翻译：一种操作装置，包括：控制多个操作装置的状态的定序器和配置存储器，其中配置信息作为操作装置中的每个状态的设置信息。在操作装置中，提供需要数据缓冲器的路径和不需要这样的数据缓冲器的另一路径，用于向操作装置输入数据，提供数据缓冲器控制部分，用于控制从这两个路径的选择和操作数据缓冲器，以及由数据缓冲器控制部分执行的数据缓冲器的路径选择和操作控制的内容根据配置信息来设置。

5. 发明授权

US07908453B2 Semiconductor device having a dynamically reconfigurable circuit configuration 有权
标题翻译：具有动态可重构电路结构的半导体器件
公开(公告)号：US07908453B2
公开(公告)日：2011-03-15
申请号：US11167310
申请日：2005-06-28
申请人： Tetsuo Kawano , Hiroshi Furukawa , Ichiro Kasama , Kazuaki Imafuku , Toshiaki Suzuki , Miyoshi Saito
发明人： Tetsuo Kawano , Hiroshi Furukawa , Ichiro Kasama , Kazuaki Imafuku , Toshiaki Suzuki , Miyoshi Saito
IPC分类号： G06F13/00
CPC分类号： G06F12/0646 , G06F13/1694 , G06F15/7867
摘要： A semiconductor device includes a plurality of memories, a sequencer which outputs configuration information, and a memory reconfiguring circuit which reconfigures the memory area in accordance with the configuration information supplied from the sequencer. Since the memory reconfiguring circuit dynamically changes the allocation of the memories, it is possible to reconfigure the memory configuration and freely change the memory size in accordance with the purpose of use.
摘要翻译：半导体器件包括多个存储器，输出配置信息的定序器和根据从定序器提供的配置信息重新配置存储器区域的存储器重配置电路。由于存储器重新配置电路动态地改变存储器的分配，所以可以根据使用目的重新配置存储器配置并自由地改变存储器大小。

6. 发明申请

US20060004979A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060004979A1
公开(公告)日：2006-01-05
申请号：US11167310
申请日：2005-06-28
申请人： Tetsuo Kawano , Hiroshi Furukawa , Ichiro Kasama , Kazuaki Imafuku , Toshiaki Suzuki , Miyoshi Saito
发明人： Tetsuo Kawano , Hiroshi Furukawa , Ichiro Kasama , Kazuaki Imafuku , Toshiaki Suzuki , Miyoshi Saito
IPC分类号： G06F12/00
CPC分类号： G06F12/0646 , G06F13/1694 , G06F15/7867
摘要： A semiconductor device includes a plurality of memories, a sequencer which outputs configuration information, and a memory reconfiguring circuit which reconfigures the memory area in accordance with the configuration information supplied from the sequencer. Since the memory reconfiguring circuit dynamically changes the allocation of the memories, it is possible to reconfigure the memory configuration and freely change the memory size in accordance with the purpose of use.
摘要翻译：半导体器件包括多个存储器，输出配置信息的定序器和根据从定序器提供的配置信息重新配置存储器区域的存储器重配置电路。由于存储器重新配置电路动态地改变存储器的分配，所以可以根据使用目的重新配置存储器配置并自由地改变存储器大小。

7. 发明授权

US07694108B2 Reconfigurable semiconductor device capable of controlling output timing of data 有权
标题翻译：能够控制数据的输出定时的可重构半导体器件
公开(公告)号：US07694108B2
公开(公告)日：2010-04-06
申请号：US11504763
申请日：2006-08-16
申请人： Miyoshi Saito , Hisanori Fujisawa
发明人： Miyoshi Saito , Hisanori Fujisawa
IPC分类号： G06F15/76 , H04B1/69
CPC分类号： G06F15/7867
摘要： An arithmetic unit capable of reconfiguring circuitry in accordance with configuration data supplied includes a data processing unit performing a processing using input data; an output data maintenance unit maintaining the result of the processing to output it as an output data; and an output valid signal control unit outputting an output valid signal indicating whether or not the output data is valid, in which an output timing of a valid data to outside the arithmetic unit can be controlled optionally by controlling the output timing of the output valid signal.
摘要翻译：能够根据提供的配置数据重新配置电路的算术单元包括使用输入数据执行处理的数据处理单元; 输出数据维护单元，保持处理结果以将其输出为输出数据; 以及输出有效信号控制单元，输出表示输出数据是否有效的输出有效信号，其中可以通过控制输出有效信号的输出定时来控制有效数据到运算单元外部的输出定时。

8. 发明授权

US07849288B2 Alternately selecting memory units to store and retrieve configuration information in respective areas for a plurality of processing elements to perform pipelined processes 有权
标题翻译：替代地选择存储器单元以存储和检索用于多个处理元件的各个区域中的配置信息以执行流水线处理
公开(公告)号：US07849288B2
公开(公告)日：2010-12-07
申请号：US11546284
申请日：2006-10-12
申请人： Hisanori Fujisawa , Miyoshi Saito , Toshihiro Ozawa
发明人： Hisanori Fujisawa , Miyoshi Saito , Toshihiro Ozawa
IPC分类号： G06F15/80
CPC分类号： G06F15/7867
摘要： A reconfigurable circuit and control method therefor, capable of enhancing efficiency of implementation of a pipeline process in processing elements and improve processing performance. Processing elements are reconfigured to form a circuit based on configuration information and execute a prescribed process. Memory units store configuration information for the processing elements. A memory switching unit switches the plurality of memory units to store therein the configuration information on the stages of a pipeline process to be performed by the processing elements. A configuration information output unit switches the memory units to output therefrom the configuration information to the plurality of processing elements.
摘要翻译：一种可重构电路及其控制方法，能够提高处理元件中流水线处理的效率，提高处理性能。重新配置处理元件以形成基于配置信息的电路并执行规定的处理。存储单元存储处理元件的配置信息。存储器切换单元切换多个存储单元以在其中存储由处理元件执行的流水线处理的阶段的配置信息。配置信息输出单元切换存储单元以从其输出配置信息到多个处理元件。

9. 发明授权

US07391234B2 Circuit and circuit connecting method 失效
标题翻译：电路和电路连接方法
公开(公告)号：US07391234B2
公开(公告)日：2008-06-24
申请号：US11395125
申请日：2006-04-03
申请人： Hisanori Fujisawa , Miyoshi Saito
发明人： Hisanori Fujisawa , Miyoshi Saito
IPC分类号： H04L12/56 , H03K19/173
CPC分类号： H04L49/15 , H04L49/101 , H04L49/1515 , H04L49/557
摘要： A network structure configures a blocking network having constraint against such a combination of said network input terminal and network output terminal as to make it unfeasible to further connect, when connecting first network input terminals to first network output terminals, second network input terminals to any one of the second network output terminals, and operation elements and the network output terminals are connected so as to minimize a constraint strength between the plurality of network output terminals inputting to the same operation element with respect to the constraint strength defined as the number of network input terminals contained in tuples of network input terminals to which the two network output terminals in the network output terminals can not be simultaneously connected.
摘要翻译：网络结构配置阻塞网络，其具有对所述网络输入终端和网络输出终端的这种组合的约束，使得当将第一网络输入终端连接到第一网络输出终端时将第二网络输入终端连接到任何一个的第二网络输出端子，并且操作元件和网络输出端子被连接，以便将输入到相同操作元件的多个网络输出端子之间的约束强度相对于被定义为网络输入的数量的约束强度最小化网络输出端子中的两个网络输出端子不能同时连接的网络输入端子的元组中包含的终端。

10. 发明申请

US20070234013A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20070234013A1
公开(公告)日：2007-10-04
申请号：US11504763
申请日：2006-08-16
申请人： Miyoshi Saito , Hisanori Fujisawa
发明人： Miyoshi Saito , Hisanori Fujisawa
IPC分类号： G06F15/00
CPC分类号： G06F15/7867
摘要： An arithmetic unit capable of reconfiguring circuitry in accordance with configuration data supplied includes a data processing unit performing a processing using input data; an output data maintenance unit maintaining the result of the processing to output it as an output data; and an output valid signal control unit outputting an output valid signal indicating whether or not the output data is valid, in which an output timing of a valid data to outside the arithmetic unit can be controlled optionally by controlling the output timing of the output valid signal.
摘要翻译：能够根据提供的配置数据重新配置电路的算术单元包括使用输入数据执行处理的数据处理单元; 输出数据维护单元，保持处理结果以将其输出为输出数据; 以及输出有效信号控制单元，输出表示输出数据是否有效的输出有效信号，其中可以通过控制输出有效信号的输出定时来控制有效数据到运算单元外部的输出定时。

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