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1. 发明授权

US09146896B2 Computer system including reconfigurable arithmetic device with network of processor elements 有权
标题翻译：计算机系统包括具有处理器元件网络的可重构运算器件
公开(公告)号：US09146896B2
公开(公告)日：2015-09-29
申请号：US12795462
申请日：2010-06-07
申请人： Hiroshi Furukawa , Ichiro Kasama
发明人： Hiroshi Furukawa , Ichiro Kasama
IPC分类号： G06F15/78 , G06F9/30 , G06F9/38
CPC分类号： G06F9/3001 , G06F9/30145 , G06F9/34 , G06F9/3879 , G06F9/3897 , G06F12/02 , G06F15/7867 , G06F2212/1021
摘要： A computer system that includes a central processing unit, a random-access-memory interface, a random-access memory whose addresses are allocated in an address space of the random-access-memory interface, and a reconfigurable arithmetic device is described herein. The reconfigurable arithmetic device includes input terminals, output terminals, a network of plurality of processor elements, a built-in random-access memory, a control unit, an inter-processor-element network and a configuration-data memory. In accordance with configuration on data from the configuration-data memory, the inter processor-element network is capable of changing the connection state of the input terminals and the output terminals to input ports and output ports of the plurality of processor elements, and the arithmetic function of the reconfigurable arithmetic device is capable of being dynamically changed.
摘要翻译：本文描述了一种包括中央处理单元，随机存取存储器接口，其地址分配在随机存取存储器接口的地址空间中的随机存取存储器的计算机系统，以及可重构运算装置。可重构算术装置包括输入端子，输出端子，多个处理器元件的网络，内置随机存取存储器，控制单元，处理器间元件网络和配置数据存储器。根据来自配置数据存储器的数据配置，处理器间网络能够将输入端子和输出端子的连接状态改变为多个处理器元件的输入端口和输出端口，并且算术能够动态地改变可重构运算装置的功能。

2. 发明申请

US20110246747A1 RECONFIGURABLE CIRCUIT USING VALID SIGNALS AND METHOD OF OPERATING RECONFIGURABLE CIRCUIT 审中-公开
标题翻译：使用有效信号的可重构电路和操作可重新配置电路的方法
公开(公告)号：US20110246747A1
公开(公告)日：2011-10-06
申请号：US13073691
申请日：2011-03-28
申请人： Takashi HANAI , Kiyomitsu Katou , Takahiro Kubota , Junji Sahoda , Ichiro Kasama , Kyoji Sato , Shinichi Sutou
发明人： Takashi HANAI , Kiyomitsu Katou , Takahiro Kubota , Junji Sahoda , Ichiro Kasama , Kyoji Sato , Shinichi Sutou
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F15/7867 , G06F9/3897
摘要： A reconfigurable circuit includes a data execution unit including a plurality of execution elements, each of which performs execution with respect to plural data upon the plural data being all in a valid state, and holds valid-state output data indicative of a result of the execution at an output node while all the plural data are in the valid state, a data selecting unit configured to connect between the execution elements in a reconfigurable manner, and a data input unit configured to supply input data to a series of execution elements to perform a series of executions, wherein a valid or invalid state of given data is specified by a valid signal accompanying and forming a pair with the given data, and the input data supplied from the data input unit to the data execution unit are fixed to valid-state constant data while the series of executions are performed.
摘要翻译：可重构电路包括：数据执行单元，包括多个执行元素，每个执行元素在多个数据全部处于有效状态时对多个数据执行执行，并且保存指示执行结果的有效状态输出数据在所有多个数据处于有效状态的输出节点处，被配置为以可重新配置的方式连接执行元件之间的数据选择单元和被配置为向一系列执行元件提供输入数据以执行一系列执行，其中给定数据的有效或无效状态由伴随并与给定数据形成一对的有效信号指定，并且从数据输入单元提供给数据执行单元的输入数据被固定为有效状态执行一系列执行时的常数数据。

3. 发明申请

US20110185152A1 RECONFIGURABLE CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：可重构电路和半导体集成电路
公开(公告)号：US20110185152A1
公开(公告)日：2011-07-28
申请号：US12973730
申请日：2010-12-20
申请人： Shinichi Sutou , Ichiro Kasama , Kyoji Sato , Takashi Hanai , Kiyomitsu Katou , Takahiro Kubota , Junji Sahoda
发明人： Shinichi Sutou , Ichiro Kasama , Kyoji Sato , Takashi Hanai , Kiyomitsu Katou , Takahiro Kubota , Junji Sahoda
IPC分类号： G06F15/76
CPC分类号： G06F15/7867 , G06F9/3012 , G06F9/30141 , G06F9/3877
摘要： A reconfigurable circuit includes a plurality of processing elements and an input/output data interface unit, and the reconfigurable circuit is configured to control connections of the plurality of processing elements for each context. The input/output data interface unit is configured to hold operation input data which is input to the plurality of processing elements and operation output data which is output from the plurality of processing elements. The input/output data interface unit includes a plurality of ports, and a plurality of registers. The registers are configured to be connected to the plurality of ports, and to include m (m being an integer of 2 or more) number of banks in a depth direction.
摘要翻译：可重构电路包括多个处理元件和输入/输出数据接口单元，并且可重构电路被配置为控制每个上下文的多个处理元件的连接。输入/输出数据接口单元被配置为保持输入到多个处理元件的操作输入数据和从多个处理元件输出的操作输出数据。输入/输出数据接口单元包括多个端口和多个寄存器。这些寄存器被配置为连接到多个端口，并且在深度方向上包括m（m为2以上的整数）个组。

4. 发明授权

US07908453B2 Semiconductor device having a dynamically reconfigurable circuit configuration 有权
标题翻译：具有动态可重构电路结构的半导体器件
公开(公告)号：US07908453B2
公开(公告)日：2011-03-15
申请号：US11167310
申请日：2005-06-28
申请人： Tetsuo Kawano , Hiroshi Furukawa , Ichiro Kasama , Kazuaki Imafuku , Toshiaki Suzuki , Miyoshi Saito
发明人： Tetsuo Kawano , Hiroshi Furukawa , Ichiro Kasama , Kazuaki Imafuku , Toshiaki Suzuki , Miyoshi Saito
IPC分类号： G06F13/00
CPC分类号： G06F12/0646 , G06F13/1694 , G06F15/7867
摘要： A semiconductor device includes a plurality of memories, a sequencer which outputs configuration information, and a memory reconfiguring circuit which reconfigures the memory area in accordance with the configuration information supplied from the sequencer. Since the memory reconfiguring circuit dynamically changes the allocation of the memories, it is possible to reconfigure the memory configuration and freely change the memory size in accordance with the purpose of use.
摘要翻译：半导体器件包括多个存储器，输出配置信息的定序器和根据从定序器提供的配置信息重新配置存储器区域的存储器重配置电路。由于存储器重新配置电路动态地改变存储器的分配，所以可以根据使用目的重新配置存储器配置并自由地改变存储器大小。

5. 发明授权

US07822888B2 Data buffer control which controls selection of path and operation of data buffer, based on stored configuration information 有权
标题翻译：数据缓存控制，根据存储的配置信息控制数据缓冲区的路径选择和操作
公开(公告)号：US07822888B2
公开(公告)日：2010-10-26
申请号：US10973094
申请日：2004-10-26
申请人： Miyoshi Saito , Hisanori Fujisawa , Ichiro Kasama , Tetsuo Kawano , Kazuaki Imafuku , Hiroshi Furukawa , Shiro Uriu , Mitsuharu Wakayoshi
发明人： Miyoshi Saito , Hisanori Fujisawa , Ichiro Kasama , Tetsuo Kawano , Kazuaki Imafuku , Hiroshi Furukawa , Shiro Uriu , Mitsuharu Wakayoshi
IPC分类号： G06F3/00 , G06F5/00 , G06F13/00 , G06F13/28
CPC分类号： G06F15/7867
摘要： An operation apparatus includes a sequencer controlling states of a plurality of operation devices and a configuration memory storing therein configuration information as setting information for each state in the operation device. In the operation apparatus, a path which requires a data buffer and another path which requires no such a data buffer are provided for inputting data to the operation device, a data buffer control part is provided for controlling selection from these two paths and operation of the data buffer, and contents of path selection and operation control of the data buffer carried out by the data buffer control part are set according to the configuration information.
摘要翻译：一种操作装置，包括：控制多个操作装置的状态的定序器和配置存储器，其中配置信息作为操作装置中的每个状态的设置信息。在操作装置中，提供需要数据缓冲器的路径和不需要这样的数据缓冲器的另一路径，用于向操作装置输入数据，提供数据缓冲器控制部分，用于控制从这两个路径的选择和操作数据缓冲器，以及由数据缓冲器控制部分执行的数据缓冲器的路径选择和操作控制的内容根据配置信息来设置。

6. 发明授权

US07783693B2 Reconfigurable circuit 有权
标题翻译：可重构电路
公开(公告)号：US07783693B2
公开(公告)日：2010-08-24
申请号：US11442971
申请日：2006-05-31
申请人： Ichiro Kasama , Masato Miyake
发明人： Ichiro Kasama , Masato Miyake
IPC分类号： G06F7/38
CPC分类号： G06F9/3001 , G06F7/5443 , G06F7/57 , G06F7/607 , G06F9/30094 , G06F9/345 , G06F9/3885 , G06F9/3897 , G06F15/7867 , G06F15/8015
摘要： A reconfigurable circuit is provided, which includes a first arithmetic unit that performs addition or subtraction of a first input data and a second input data and outputs output data, and a first selector that selects an output data of the first arithmetic unit or a third input data and outputs the selected one as the first input data to the first arithmetic unit.
摘要翻译：提供了一种可重构电路，其包括执行第一输入数据和第二输入数据的加法或减法并输出输出数据的第一算术单元，以及选择第一运算单元或第三输入的输出数据的第一选择器数据并将所选择的一个作为第一输入数据输出到第一运算单元。

7. 发明授权

US07580963B2 Semiconductor device having an arithmetic unit of a reconfigurable circuit configuration in accordance with stored configuration data and a memory storing fixed value data to be supplied to the arithmetic unit, requiring no data area for storing fixed value data to be set in a configuration memory 有权
标题翻译：具有根据存储的配置数据的可重新配置电路配置的运算单元和存储要提供给运算单元的固定值数据的存储器的半导体器件，不需要用于存储待配置的配置存储器中的固定值数据的数据区域
公开(公告)号：US07580963B2
公开(公告)日：2009-08-25
申请号：US11035055
申请日：2005-01-14
申请人： Tetsuo Kawano , Hiroshi Furukawa , Ichiro Kasama , Kazuaki Imafuku , Toshiaki Suzuki
发明人： Tetsuo Kawano , Hiroshi Furukawa , Ichiro Kasama , Kazuaki Imafuku , Toshiaki Suzuki
IPC分类号： G06F7/38
CPC分类号： G06F15/7867
摘要： A semiconductor device includes a configuration memory for storing configuration data, an arithmetic unit whose circuit configuration can be reconfigured in accordance with the configuration data, and a fixed value memory for storing fixed value data to be supplied to the arithmetic unit. Since the configuration data and fixed value data to be supplied to the arithmetic unit are stored in the different memories, no data area for storing the fixed value data need be set in the configuration memory. This makes it possible to supply a predetermined fixed value to the arithmetic unit by storing only information for reading out fixed value data from the fixed value memory.
摘要翻译：半导体器件包括用于存储配置数据的配置存储器，可根据配置数据重新配置其电路配置的算术单元和用于存储要提供给运算单元的固定值数据的固定值存储器。由于将要提供给运算单元的配置数据和固定值数据存储在不同的存储器中，所以不需要在配置存储器中设置用于存储固定值数据的数据区域。这使得可以通过仅存储用于从固定值存储器读出固定值数据的信息来向运算单元提供预定的固定值。

8. 发明申请

US20070198619A1 Reconfigurable circuit 有权
标题翻译：可重构电路
公开(公告)号：US20070198619A1
公开(公告)日：2007-08-23
申请号：US11442971
申请日：2006-05-31
申请人： Ichiro Kasama , Masato Miyake
发明人： Ichiro Kasama , Masato Miyake
IPC分类号： G06F15/00
CPC分类号： G06F9/3001 , G06F7/5443 , G06F7/57 , G06F7/607 , G06F9/30094 , G06F9/345 , G06F9/3885 , G06F9/3897 , G06F15/7867 , G06F15/8015
摘要： A reconfigurable circuit is provided, which includes a first arithmetic unit that performs addition or subtraction of a first input data and a second input data and outputs output data, and a first selector that selects an output data of the first arithmetic unit or a third input data and outputs the selected one as the first input data to the first arithmetic unit.
摘要翻译：提供了一种可重构电路，其包括执行第一输入数据和第二输入数据的加法或减法并输出输出数据的第一算术单元，以及选择第一运算单元或第三输入的输出数据的第一选择器数据并将所选择的一个作为第一输入数据输出到第一运算单元。

9. 发明申请

US20070150707A1 PROCESSOR AND PIPELINE RECONFIGURATION CONTROL METHOD 审中-公开
标题翻译：处理器和管道重新配置控制方法
公开(公告)号：US20070150707A1
公开(公告)日：2007-06-28
申请号：US11681350
申请日：2007-03-02
申请人： Shiro URIU , Mitsuharu Wakayoshi , Tetsuo Kawano , Hiroshi Furukawa , Ichiro Kasama , Kazuaki Imafuku , Toshiaki Suzuki
发明人： Shiro URIU , Mitsuharu Wakayoshi , Tetsuo Kawano , Hiroshi Furukawa , Ichiro Kasama , Kazuaki Imafuku , Toshiaki Suzuki
IPC分类号： G06F15/00
CPC分类号： G06F15/7867 , G06F9/30181 , G06F9/3836 , G06F9/3869 , G06F9/3897
摘要： A reconfigurable processor calculates execution times of configuration for executing pipeline processing from hardware configuration information, and fixes a clock cycle until processing ends. A counter compares the fixed clock cycle with the actual number of elapsed clocks, and, when the number of elapsed clocks equals the clock cycle, it is determined that pipeline processing has ended, and a configuration controller is notified of this.
摘要翻译：可重构处理器根据硬件配置信息计算执行流水线处理的配置执行时间，并修复时钟周期，直到处理结束为止。计数器将固定时钟周期与实际经过的时钟数进行比较，当经过的时钟数等于时钟周期时，确定流水线处理已经结束，并且通知配置控制器。

10. 发明申请

US20060004979A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060004979A1
公开(公告)日：2006-01-05
申请号：US11167310
申请日：2005-06-28
申请人： Tetsuo Kawano , Hiroshi Furukawa , Ichiro Kasama , Kazuaki Imafuku , Toshiaki Suzuki , Miyoshi Saito
发明人： Tetsuo Kawano , Hiroshi Furukawa , Ichiro Kasama , Kazuaki Imafuku , Toshiaki Suzuki , Miyoshi Saito
IPC分类号： G06F12/00
CPC分类号： G06F12/0646 , G06F13/1694 , G06F15/7867
摘要： A semiconductor device includes a plurality of memories, a sequencer which outputs configuration information, and a memory reconfiguring circuit which reconfigures the memory area in accordance with the configuration information supplied from the sequencer. Since the memory reconfiguring circuit dynamically changes the allocation of the memories, it is possible to reconfigure the memory configuration and freely change the memory size in accordance with the purpose of use.
摘要翻译：半导体器件包括多个存储器，输出配置信息的定序器和根据从定序器提供的配置信息重新配置存储器区域的存储器重配置电路。由于存储器重新配置电路动态地改变存储器的分配，所以可以根据使用目的重新配置存储器配置并自由地改变存储器大小。

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