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1. 发明申请

US20100058030A1 ARITHMETIC-LOGIC UNIT, PROCESSOR, AND PROCESSOR ARCHITECTURE 有权
标题翻译：算术逻辑单元，处理器和处理器架构
公开(公告)号：US20100058030A1
公开(公告)日：2010-03-04
申请号：US12618954
申请日：2009-11-16
申请人： Hideki Yoshizawa
发明人： Hideki Yoshizawa
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/30014 , G06F9/3853 , G06F9/3869 , G06F9/3875
摘要： An arithmetic-logic unit for performing an operation of a prescribed bit length in an execution stage of a processor includes a plurality of sub-arithmetic-logic units which perform in respectively different pipeline stages sub-operations created by decomposing the operation of the prescribed bit length in a bit length direction, and a plurality of pipeline registers provided so as to separate the pipeline stages from each other, wherein each of the pipeline registers operates in such a manner as to be switchable between two operation modes, a flip-flop mode in which an output value is updated in synchronism with an input trigger and a transparent mode in which an input value is directly output.
摘要翻译：用于在处理器的执行阶段中执行规定位长的操作的算术逻辑单元包括多个子算术逻辑单元，它们分别在不同的流水线级执行通过分解规定位的操作而产生的子操作以及多个流水线寄存器，其被设置为将流水线级彼此分离，其中每个流水线寄存器以可在两种操作模式之间切换的方式操作，触发器模式其中输出值与输入触发和输入值直接输出的透明模式同步更新。

2. 发明申请

US20090232190A1 SIGNAL TRANSMITTING METHOD, TRANSMITTING APPARATUS, AND RECEIVING APPARATUS USED FOR THE SIGNAL TRANSMITTING METHOD 有权
标题翻译：信号发送方法，发送装置和用于信号发送方法的接收装置
公开(公告)号：US20090232190A1
公开(公告)日：2009-09-17
申请号：US12329508
申请日：2008-12-05
申请人： Hideki Yoshizawa
发明人： Hideki Yoshizawa
IPC分类号： H04B1/707
CPC分类号： H04J13/00
摘要： A disclosed signal transmitting method includes the steps of a) categorizing plural digital signals, obtained by performing A/D conversion on plural analog signals consecutively arranged in a time direction, into plural signal groups in an order starting from lower bits of the plural digital signals, b) performing code spreading on the plural digital signals by using a different spread frequency for each signal group and using different spread codes for each bit, c) multiplexing the spread digital signals, and d) transmitting the multiplexed plural digital signals.
摘要翻译：所公开的信号发送方法包括以下步骤：a）将从时间方向连续排列的多个模拟信号上进行A / D转换获得的多个数字信号分类为多个信号组，从多个数字信号的低位开始 b）通过对每个信号组使用不同的扩展频率并对每个比特使用不同的扩展码来对多个数字信号执行码扩频，c）复用扩展的数字信号，以及d）发送多路复用的多个数字信号。

3. 发明授权

US06470380B1 Signal processing device accessible as memory 失效
标题翻译：信号处理设备作为存储器访问
公开(公告)号：US06470380B1
公开(公告)日：2002-10-22
申请号：US08955089
申请日：1997-10-21
申请人： Hideki Yoshizawa , Toru Tsuruta , Norichika Kumamoto , Yuji Nomura
发明人： Hideki Yoshizawa , Toru Tsuruta , Norichika Kumamoto , Yuji Nomura
IPC分类号： G06F15167
CPC分类号： G06F9/5066 , G06F9/5011 , G06F12/0813 , G06F12/1466 , G06F2209/509
摘要： A signal processing device is provided by connecting information processing units to each other using communication links and connecting the information processing units to each other and a host processor using an external bus. Parallel and pipe-line processing is accommodated by communication between the information processing units via the communication links and respective storage units of the information processing units and also by communication between the host processor and the information processing units via the external bus and the respective storage units. The host processor can communicate with the information processing units via the external bus through the respective storage units, the storage units being accessible as memory by the host processor. If each information processing unit is implemented on a single chip as an integrated circuit, the signal processing device can be incorporated in a computer in the same manner as conventional memory device are incorporated.
摘要翻译：通过使用通信链路将信息处理单元彼此连接并将信息处理单元彼此连接并使用外部总线来连接主处理器来提供信号处理设备。通过通信链路和信息处理单元的各个存储单元之间的信息处理单元之间的通信以及经由外部总线和各个存储单元的主处理器和信息处理单元之间的通信来适应并行和管线处理。主机处理器可以通过外部总线通过相应的存储单元与信息处理单元进行通信，存储单元可由主机处理器作为存储器访问。如果每个信息处理单元在作为集成电路的单个芯片上实现，则信号处理设备可以以与传统的存储器件相同的方式并入计算机中。

4. 发明授权

US5544336A Parallel data processing system which efficiently performs matrix and neurocomputer operations, in a negligible data transmission time 失效
标题翻译：并行数据处理系统，在数据传输时间可以忽略不计的情况下有效执行矩阵和神经计算机操作
公开(公告)号：US5544336A
公开(公告)日：1996-08-06
申请号：US420332
申请日：1995-04-11
申请人： Hideki Kato , Hideki Yoshizawa , Hiroki Iciki , Daiki Masumoto
发明人： Hideki Kato , Hideki Yoshizawa , Hiroki Iciki , Daiki Masumoto
IPC分类号： G06F15/16 , G06F15/177 , G06N3/10 , G06F3/00
CPC分类号： G06N3/10
摘要： A parallel data processing system processes data by synchronously operating a plurality of data processing units (processor elements). It aims at reducing the overhead caused by the data transmission in a system, performing a matrix operation and a neurocomputer operation by making the best of its parallel processing method, and at using excess units for another operation when the number of units required for an operation is smaller than the number of the existing units. The parallel data processing system comprises a plurality of data processing units; a plurality of trays which store and transmit data, each connected to a data processing unit; a tray connection switching unit for changing the connection state of the data transmission path between trays, dividing data processing units into a plurality of groups, and performing an independent operation on each group; and a clock generator for synchronously operating a data transmission between trays and a data process in a data processing unit. Thus, the data are transmitted while the data are processed, so the data transmission time can be actually counted as zero.
摘要翻译：并行数据处理系统通过同步操作多个数据处理单元（处理器元件）来处理数据。其目的在于减少系统中的数据传输引起的开销，通过充分利用其并行处理方法执行矩阵运算和神经计算机操作，并且在运行所需的单元数量的情况下使用多余的单位进行另一操作小于现有单位的数量。并行数据处理系统包括多个数据处理单元; 存储和发送数据的多个托盘，每个托盘连接到数据处理单元; 托盘连接切换单元，用于改变托盘之间的数据传输路径的连接状态，将数据处理单元划分成多个组，并对每个组执行独立操作; 以及时钟发生器，用于同步地操作数据处理单元中的托盘与数据处理之间的数据传输。因此，在处理数据的同时发送数据，因此数据传输时间实际上可以被计数为零。

5. 发明授权

US5220660A Parallel data processing apparatus with signal skew compensation 失效
标题翻译：并行数据处理装置与信号补偿
公开(公告)号：US5220660A
公开(公告)日：1993-06-15
申请号：US722198
申请日：1991-06-27
申请人： Hideki Yoshizawa , Hideki Kato , Hiroki Iciki , Daiki Masumoto
发明人： Hideki Yoshizawa , Hideki Kato , Hiroki Iciki , Daiki Masumoto
IPC分类号： G06F15/16 , G06F1/10 , G06F9/52 , G06F15/177 , G06F15/80
CPC分类号： G06F1/10
摘要： A parallel data processing apparatus including a plurality of processors, a pair of signal paths are provided for each processor, one signal path of each pair being used for supplying a predetermined signal to the processor, and the second signal path being used for returning the signal from the processor to a predetermined position common to all of the processors. Each of the above signal paths include a variable delay unit. The apparatus further includes a delay measuring unit for measuring the time elapsing while the signal is propagated from the above predetermined position to a corresponding processor and then returned from the processor to the above predetermined position through each pair of signal paths. Further the apparatus includes a delay adjusting unit for adjusting the delays caused by the variable delay units in all of the signal paths. The delay adjustment are based on the results of a measurement by the delay measuring unit, so that the time elapsing while the signal is propagated from the predetermined position to the plurality of processors, through the respective signal paths for supplying the signal to the processors, are equal.

6. 发明申请

US20110315872A1 OXYGEN DETECTION METHOD, AIR LEAKAGE DETERMINATION METHOD, GAS COMPONENT DETECTION DEVICE, AND VACUUM PROCESSING APPARATUS 有权
标题翻译：氧气检测方法，空气泄漏测定方法，气体成分检测装置和真空处理装置
公开(公告)号：US20110315872A1
公开(公告)日：2011-12-29
申请号：US13125385
申请日：2010-03-16
申请人： Toyoaki Nakajima , Takeshi Miyashita , Yasushi Nagata , Yasufumi Uchida , Hideki Yoshizawa
发明人： Toyoaki Nakajima , Takeshi Miyashita , Yasushi Nagata , Yasufumi Uchida , Hideki Yoshizawa
IPC分类号： H01J49/26 , G01N27/70
CPC分类号： G01N27/66 , G01M3/202
摘要： An oxygen detection method, includes: preparing a grid, an ion collector, and a filament in which an oxide are formed on a surface of metal; controlling a filament current flowing to the filament so that an emission current becomes constant; discharging thermionic electrons which are caused by heat generation by applying the filament current, and generating ions by ionizing a gas; capturing the ions with the ion collector; and detecting oxygen being present in a vacuum processing chamber by measuring a filament current value.
摘要翻译：氧检测方法包括：制备栅格，离子收集器和在金属表面上形成氧化物的长丝; 控制流向灯丝的灯丝电流，使得发射电流变得恒定; 通过施加灯丝电流来放出由发热引起的热离子电子，并通过电离气体产生离子; 用离子收集器捕获离子; 并且通过测量灯丝电流值来检测存在于真空处理室中的氧气。

7. 发明授权

US07774580B2 Array processor having reconfigurable data transfer capabilities 有权
标题翻译：阵列处理器具有可重新配置的数据传输能力
公开(公告)号：US07774580B2
公开(公告)日：2010-08-10
申请号：US11077561
申请日：2005-03-11
申请人： Miyoshi Saito , Hisanori Fujisawa , Hideki Yoshizawa , Tetsu Tanizawa , Ichiro Kasama , Tetsuo Kawano , Kazuaki Imafuku , Hiroshi Furukawa , Shiro Uriu , Mitsuharu Wakayoshi
发明人： Miyoshi Saito , Hisanori Fujisawa , Hideki Yoshizawa , Tetsu Tanizawa , Ichiro Kasama , Tetsuo Kawano , Kazuaki Imafuku , Hiroshi Furukawa , Shiro Uriu , Mitsuharu Wakayoshi
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F15/8007
摘要： A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.
摘要翻译：可重构操作装置由能够通过使用一段给定的第一配置数据并且彼此同时操作的多个操作单元组成，能够重新配置自身; RAMs 构成操作装置所需的各种处理器元件; 互连所述操作单元，所述RAM和所述不同处理器元件的资源间网络，以与所述资源的位置和种类无关的统一传送时间在连接到其之间的资源之间执行数据传输，并且可通过使用给定的第二配置数据来重新配置; 以及存储第一和第二配置数据的配置存储器。配置数据从外部存储装置加载到配置存储器上，并且基于从多个操作单元可获得的数据，将第一和第二配置数据以适当的顺序和定时提供给可重构处理器资源。

8. 发明授权

US5822760A Cache-memory system having multidimensional cache 失效
标题翻译：具有多维缓存的高速缓存存储器系统
公开(公告)号：US5822760A
公开(公告)日：1998-10-13
申请号：US659702
申请日：1996-06-10
申请人： Hideki Yoshizawa , Tatsushi Otsuka
发明人： Hideki Yoshizawa , Tatsushi Otsuka
IPC分类号： G06F12/08 , G09G5/39
CPC分类号： G06F12/0875 , G06F12/0862 , G09G2360/122 , G09G5/39
摘要： A prediction block address is generated from a current block address in accordance with a rule specified by a prediction mode signal. One of two cache memory banks is allocated as a current bank and the other is allocated as a prediction bank. When the current block address is stored in the prediction bank, the allocation of the current and prediction banks is reversed. When the prediction block address is not stored in the prediction bank, a data block specified by the prediction block address is block-read into the prediction bank.
摘要翻译：根据由预测模式信号指定的规则，从当前块地址生成预测块地址。两个高速缓存存储体之一被分配为当前存储体，另一个被分配为预测库。当当前块地址存储在预测库中时，电流和预测库的分配相反。当预测块地址未存储在预测库中时，由预测块地址指定的数据块被块读入预测库。

9. 发明授权

US5627944A Parallel data processing system 失效
标题翻译：并行数据处理系统
公开(公告)号：US5627944A
公开(公告)日：1997-05-06
申请号：US248642
申请日：1994-05-25
申请人： Katsuhito Fujimoto , Hideki Yoshizawa , Tatsushi Otsuka
发明人： Katsuhito Fujimoto , Hideki Yoshizawa , Tatsushi Otsuka
IPC分类号： G06F15/16 , G06F15/80 , G06N3/10 , G06F15/18
CPC分类号： G06N3/10
摘要： A parallel data processing system uses a parallel learning method capable of having sufficient parallelness to shorten learning time and has plural data processing units, each connected to a data transfer unit and having a unit for holding execution parameters as are required for data processing, a unit for holding partial sample data which comprises at least part of the full sample data necessary for the required data processing, an adjustment value calculation unit which calculates, from partial sample data stored in the unit for holding partial sample data and from the execution parameters held in the execution parameter holding unit, adjustment amounts related to the execution parameters with regard to the partial sample data and, further, an accumulator which, when calculating the overall total of the execution parameter adjustment amounts with regard to the full sample data, accumulates the adjustment amounts related to the execution parameters with regard to the partial sample data at the data processing units and the adjustment amounts related to the execution parameters with regard to the partial sample data at other data processing units by the data transfer unit.
摘要翻译：并行数据处理系统使用能够具有足够的并行度以缩短学习时间的并行学习方法，并且具有多个数据处理单元，每个数据处理单元连接到数据传送单元并具有用于保持数据处理所需的执行参数的单元，单元用于保持包括所需数据处理所需的全部样本数据的至少一部分的部分样本数据;调整值计算单元，从存储在用于保存部分样本数据的单元中的部分样本数据和从执行参数保持单元，关于部分采样数据的与执行参数有关的调整量，以及累加器，当计算关于全样本数据的执行参数调整量的总计时，累加调整与部分样本d相关的执行参数的数量在数据处理单元处的ata以及与数据传送单元在其他数据处理单元处的部分采样数据相关的执行参数的调整量。

10. 发明授权

US5131072A Neurocomputer with analog signal bus 失效
标题翻译：具有模拟信号总线的神经元
公开(公告)号：US5131072A
公开(公告)日：1992-07-14
申请号：US474055
申请日：1990-04-30
申请人： Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Yoshihide Sugiura , Kazuo Asakawa , Hiroyuki Tsuzuki , Hideichi Endo , Takashi Kawasaki , Toshiharu Matsuda , Chikara Tsuchiya , Katsuya Ishikawa , Hiromu Iwamoto
发明人： Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Yoshihide Sugiura , Kazuo Asakawa , Hiroyuki Tsuzuki , Hideichi Endo , Takashi Kawasaki , Toshiharu Matsuda , Chikara Tsuchiya , Katsuya Ishikawa , Hiromu Iwamoto
IPC分类号： G06N3/04 , G06N3/063
CPC分类号： G06N3/063 , G06N3/04 , G06N3/0635
摘要： An analogue neuron processor (ANP) performs an operation of sum-of-products of a time divisional analog input signal sequentially input from an analog signal bus and weight data and output an analog signal to an analog signal bus through a nonlinear circuit. A layered type or a feedback type neural network is formed of ANPs. The neural network reads necessary control data from a control pattern memory under the control of micro sequencer and reads the necessary weight data from the weight memory thereby realizing a neuron computer. The neuron computer connects a plurality of ANPs by using a single analog bus, thereby greatly decreasing the number of the wires used for the neural network and also decreasing the size of the circuit. A plurality of ANPs in a single layer simultaneously receives analog signal from an analog bus and carries out a parallel operation in the same time period and ANPs in different layers perform a parallel operation in a pipeline manner, thereby increasing a speed of an operation. Accordingly, the prsent invention can provide a neuron computer with a high practicality.

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