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1. 发明授权

US10163911B2 SRAM cell with T-shaped contact 有权
公开(公告)号：US10163911B2
公开(公告)日：2018-12-25
申请号：US12479266
申请日：2009-06-05
申请人： Theodore W. Houston , Thomas J. Aton , Scott W. Jessen
发明人： Theodore W. Houston , Thomas J. Aton , Scott W. Jessen
IPC分类号： H01L27/088 , H01L27/11 , H01L27/02
摘要： An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments.

2. 发明授权

US09059032B2 SRAM cell parameter optimization 有权
标题翻译： SRAM单元参数优化
公开(公告)号：US09059032B2
公开(公告)日：2015-06-16
申请号：US13097370
申请日：2011-04-29
申请人： Theodore W. Houston , Puneet Kohli , Amitava Chatterjee
发明人： Theodore W. Houston , Puneet Kohli , Amitava Chatterjee
IPC分类号： G11C11/00 , H01L27/11 , H01L27/02 , G11C11/412
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/0207
摘要： An integrated circuit having an SRAM cell includes a pair of cross-coupled inverters with first driver and load transistors connected to provide a first storage node and second driver and load transistors connected to provide a second storage node. The SRAM cell also includes first and second pass gate transistors controlled by at least one word line and respectively connected between a first bit line and the first storage node and a second bit line and the second storage node; wherein a first driver transistor threshold voltage is different than a second driver transistor threshold voltage and one of the first and second driver threshold voltages is different than a pass gate transistor threshold voltage. Alternately, a threshold voltage of the first and second driver transistors is different than a symmetrical pass gate transistor threshold voltage. Additionally, methods of manufacturing an integrated circuit having an SRAM cell are provided.
摘要翻译：具有SRAM单元的集成电路包括一对交叉耦合的反相器，其中第一驱动器和负载晶体管被连接以提供第一存储节点和第二驱动器以及连接到第二存储节点的负载晶体管。 SRAM单元还包括由至少一个字线控制并分别连接在第一位线和第一存储节点之间的第一和第二通过栅极晶体管以及第二位线和第二存储节点; 其中第一驱动晶体管阈值电压不同于第二驱动晶体管阈值电压，并且第一和第二驱动器阈值电压中的一个不同于通过栅极晶体管阈值电压。或者，第一和第二驱动晶体管的阈值电压不同于对称的通过栅极晶体管阈值电压。另外，提供了具有SRAM单元的集成电路的制造方法。

3. 发明授权

US08755239B2 Read assist circuit for an SRAM 有权
标题翻译：读取SRAM的辅助电路
公开(公告)号：US08755239B2
公开(公告)日：2014-06-17
申请号：US13298825
申请日：2011-11-17
申请人： Lakshmikantha V. Holla , Vinod J. Menezes , Theodore W. Houston , Michael Patrick Clinton
发明人： Lakshmikantha V. Holla , Vinod J. Menezes , Theodore W. Houston , Michael Patrick Clinton
IPC分类号： G11C8/08 , G11C11/417 , G11C11/413
CPC分类号： G11C11/413 , G11C7/02 , G11C8/08 , G11C11/417 , G11C11/419
摘要： A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving one of the array supply voltage and a periphery supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a switch coupled in series. The switch is responsive to the array supply voltage. The word line suppression circuit limits a word line voltage to a value lower than the array supply voltage such that the static noise margin (SNM) of the bit cell is increased.
摘要翻译：存储电路包括接收字线，互补位线和阵列电源电压的位单元; 字线驱动器，其耦合到字线，字线驱动器接收阵列电源电压之一和外围电源电压; 以及耦合到字线的字线抑制电路。字线抑制电路包括二极管和串联耦合的开关。开关响应阵列电源电压。字线抑制电路将字线电压限制在比阵列电源电压低的值，使得位单元的静态噪声容限（SNM）增加。

4. 发明授权

US08654572B2 10T SRAM cell with near dual port functionality 有权
标题翻译： 10T SRAM单元，具有近端口功能
公开(公告)号：US08654572B2
公开(公告)日：2014-02-18
申请号：US13412773
申请日：2012-03-06
申请人： Theodore W. Houston
发明人： Theodore W. Houston
IPC分类号： G11C11/00
CPC分类号： G11C11/419 , G11C8/16 , G11C11/41 , G11C11/412
摘要： An integrated circuit including an array of SRAM cells containing a write port with a write word line and two read buffers with read word lines. The write port includes passgate transistors connected to each data node of the SRAM cell. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are biased during a read operation. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are floated during a read operation. A process of operating the integrated circuit in which the write port and the read ports share data lines and the source nodes of read buffer driver transistors are floated during a write operation.
摘要翻译：一种集成电路，其包括具有写入字线的写入端口和具有读取字线的两个读取缓冲器的SRAM单元阵列。写入端口包括连接到SRAM单元的每个数据节点的通道晶体管。在读操作期间操作读缓冲驱动晶体管的源节点的集成电路的工作过程。在读操作期间操作读缓冲驱动晶体管的源节点浮动的集成电路的处理。在写入操作期间，浮动写入端口和读取端口共享数据线和读取缓冲器驱动器晶体管的源节点的集成电路的工作。

5. 发明授权

US08654568B2 10T SRAM cell with near dual port functionality 有权
标题翻译： 10T SRAM单元，具有近端口功能
公开(公告)号：US08654568B2
公开(公告)日：2014-02-18
申请号：US12546291
申请日：2009-08-24
申请人： Theodore W. Houston
发明人： Theodore W. Houston
IPC分类号： G11C11/00
CPC分类号： G11C11/419 , G11C8/16 , G11C11/41 , G11C11/412
摘要： An integrated circuit including a ram array with SRAM cells containing a write port with a write word line and two read buffers with read word lines. The write port includes passgate transistors connected to each data node of the SRAM cell. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are biased during a read operation. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are floated during a read operation. A process of operating the integrated circuit in which the write port and the read ports share data lines and the source nodes of read buffer driver transistors are floated during a write operation.
摘要翻译：包括具有SRAM单元的RAM阵列的集成电路，其具有写入字线的写入端口和具有读取字线的两个读取缓冲器。写入端口包括连接到SRAM单元的每个数据节点的通道晶体管。在读操作期间操作读缓冲驱动晶体管的源节点的集成电路的工作过程。在读操作期间操作读缓冲驱动晶体管的源节点浮动的集成电路的处理。在写入操作期间，浮动写入端口和读取端口共享数据线和读取缓冲器驱动器晶体管的源节点的集成电路的工作。

6. 发明申请

US20130003471A1 MEMORY CELL EMPLOYING REDUCED VOLTAGE 有权
标题翻译：使用减少电压的存储单元
公开(公告)号：US20130003471A1
公开(公告)日：2013-01-03
申请号：US13551057
申请日：2012-07-17
申请人： Donald George Mikan, JR. , Hugh Mair , Theodore W. Houston , Michael Patrick Clinton
发明人： Donald George Mikan, JR. , Hugh Mair , Theodore W. Houston , Michael Patrick Clinton
IPC分类号： G11C7/22
CPC分类号： G11C7/02 , G11C11/413
摘要： A memory array has a memory cell that comprises a storage element storing a logical state at a reduced voltage during at least one functional operation and a write access circuit configured to connect the storage element to at least a first write bit line in response to a write signal on the write word line for writing the logical state to the memory cell. The memory cell further comprises a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array. The read access circuit is enabled and configured to read the logic state of the storage element in response to a read signal on the read word line. The reduced voltage is reduced relative to an operating voltage of at least one peripheral circuit associated with reading and/or writing of the memory cell.
摘要翻译：存储器阵列具有存储单元，该存储单元包括在至少一个功能操作期间以降低的电压存储逻辑状态的存储单元，以及配置为响应于写入将存储元件连接到至少第一写入位线的写入访问电路写入字线上的信号用于将逻辑状态写入存储单元。存储单元还包括读取存取电路，其包括连接到存储元件的输入节点和连接到存储器阵列的读取位线的输出节点。读取访问电路被启用并被配置为响应于读取的字线上的读取信号来读取存储元件的逻辑状态。降低的电压相对于与存储单元的读取和/或写入相关联的至少一个外围电路的工作电压而降低。

7. 发明申请

US20120302013A1 SRAM CELL WITH DIFFERENT CRYSTAL ORIENTATION THAN ASSOCIATED LOGIC 审中-公开
标题翻译：具有相关逻辑的不同晶体方向的SRAM单元
公开(公告)号：US20120302013A1
公开(公告)日：2012-11-29
申请号：US13570918
申请日：2012-08-09
申请人： Theodore W. Houston
发明人： Theodore W. Houston
IPC分类号： H01L21/8234
CPC分类号： H01L27/1104 , G11C11/412 , H01L21/823807 , H01L21/823878 , H01L27/11 , H01L27/1207
摘要： An integrated circuit containing logic transistors and an array of SRAM cells in which the logic transistors are formed in semiconductor material with one crystal orientation and the SRAM cells are formed in a second semiconductor layer with another crystal orientation. A process of forming an integrated circuit containing logic transistors and an array of SRAM cells in which the logic transistors are formed in a top semiconductor layer with one crystal orientation and the SRAM cells are formed in an epitaxial semiconductor layer with another crystal orientation. A process of forming an integrated circuit containing logic transistors and an array of SRAM cells in which the SRAM cells are formed in a top semiconductor layer with one crystal orientation and the logic transistors are formed in an epitaxial semiconductor layer with another crystal orientation.
摘要翻译：包含逻辑晶体管和SRAM单元阵列的集成电路，其中逻辑晶体管形成在具有一个晶体取向的半导体材料中，并且SRAM单元形成在具有另一晶体取向的第二半导体层中。形成包含逻辑晶体管和SRAM单元阵列的集成电路的过程，其中逻辑晶体管形成在具有一个晶体取向的顶部半导体层中，并且SRAM单元形成在具有另一晶体取向的外延半导体层中。形成包含逻辑晶体管的集成电路和SRAM单元的阵列的处理，其中SRAM单元形成在具有一个晶体取向的顶部半导体层中，并且逻辑晶体管形成在具有另一晶体取向的外延半导体层中。

8. 发明申请

US20120300538A1 SRAM STRAP ROW DOUBLE WELL CONTACT 有权
公开(公告)号：US20120300538A1
公开(公告)日：2012-11-29
申请号：US13301287
申请日：2011-11-21
申请人： Theodore W. Houston
发明人： Theodore W. Houston
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L27/0207 , H01L27/1104 , H01L27/1116
摘要： An integrated circuit containing an SRAM array having a strap row. The strap row has a well tap active area that partially overlaps adjacent first polarity wells and a second polarity well that is located between the adjacent first polarity wells. A well contact plug is disposed on a top surface of a tap layer located within the well tap active area.
摘要翻译：包含具有带排的SRAM阵列的集成电路。带排具有与相邻的第一极性阱部分重叠的阱分接有源区域和位于相邻的第一极性阱之间的第二极性阱。阱接触插头设置在位于阱分接头活动区域内的抽头层的顶表面上。

9. 发明授权

US08315086B1 SRAM strap row well contact 有权
标题翻译： SRAM带排良好接触
公开(公告)号：US08315086B1
公开(公告)日：2012-11-20
申请号：US13301132
申请日：2011-11-21
申请人： Theodore W. Houston
发明人： Theodore W. Houston
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C5/025 , G11C5/063 , H01L21/76895 , H01L27/0207 , H01L27/1104
摘要： An integrated circuit containing an SRAM array having a strap row and an SRAM cell row. The strap row includes a tap connecting region that connects two columnar regions of a first polarity well. The strap row also includes a well tap active area in a tap connecting well region. The well tap active area includes a tap layer and a well contact plug that is disposed on the top surface of the tap layer.
摘要翻译：包含具有带行和SRAM单元行的SRAM阵列的集成电路。带排包括连接第一极性的两个柱状区域的抽头连接区域。带排还包括在水龙头连接井区域中的井口活动区域。阱分接器活动区域包括配置在抽头层顶表面上的抽头层和阱接触插塞。

10. 发明授权

US08300451B2 Two word line SRAM cell with strong-side word line boost for write provided by weak-side word line 有权
标题翻译：两个字线SRAM单元，具有强边字线升压，由弱边字线提供
公开(公告)号：US08300451B2
公开(公告)日：2012-10-30
申请号：US12750270
申请日：2010-03-30
申请人： Hugh T. Mair , Theodore W. Houston
发明人： Hugh T. Mair , Theodore W. Houston
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/412
摘要： An integrated circuit having a static random access memory (SRAM) includes an array of SRAM cells arranged in rows and columns having a write word line and a read/write word line connected to provide row access to the array of SRAM cells. The SRAM also includes a coupling capacitance connected between the write word line and a detachable allocation of the read/write word line as well as an overdrive module connected to charge the coupling capacitance and provide an overdrive voltage on the detachable allocation of the read/write word line during activation of the write word line. A method of operating an integrated circuit having an SRAM includes providing an overdrive voltage on the detachable allocation of the read/write word line corresponding to a charge redistribution across the coupling capacitance during part of a write cycle.
摘要翻译：具有静态随机存取存储器（SRAM）的集成电路包括排列成行和列的SRAM单元的阵列，其具有连接以提供对SRAM单元阵列的行访问的写字线和读/写字线。 SRAM还包括连接在写入字线和读取/写入字线的可拆卸分配之间的耦合电容以及连接到对耦合电容充电的过驱动模块，并且在可读取/写入分配上提供过驱动电压激活写字线时的字线。一种操作具有SRAM的集成电路的方法包括：在写入周期的一部分期间，在对应于耦合电容的电荷再分配的读/写字线的可分离分配上提供过驱动电压。

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