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1. 发明授权

US08213243B2 Program cycle skip 有权
标题翻译：程序循环跳过
公开(公告)号：US08213243B2
公开(公告)日：2012-07-03
申请号：US12638729
申请日：2009-12-15
申请人： Gopinath Balakrishnan , Luca Fasoli , Tz-Yi Liu , Yuheng Zhang , Yan Li
发明人： Gopinath Balakrishnan , Luca Fasoli , Tz-Yi Liu , Yuheng Zhang , Yan Li
IPC分类号： G11C7/00
CPC分类号： G11C13/0069 , G11C5/02 , G11C13/0007 , G11C13/0061 , G11C17/165 , G11C17/18 , G11C2013/0076 , G11C2013/0085 , G11C2213/71
摘要： A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.
摘要翻译：非易失性存储系统包括在编程页面（或其他单元）数据时跳过编程周期的技术。在对页面（或其他单元）数据的当前子集进行编程时，系统将评估页面（或其他单元）的下一个子集是否应编程为非易失性存储元素或跳过。不应被跳过的页面（或其他单元）的子集被编程到非易失性存储元件中。一些实施例包括将适当数据传送到临时锁存器/寄存器，以准备编程，同时评估是编程还是跳过编程。

2. 发明申请

US20120224408A1 THREE DIMENSIONAL MEMORY SYSTEM WITH COLUMN PIPELINE 有权
标题翻译：具有柱管的三维存储系统
公开(公告)号：US20120224408A1
公开(公告)日：2012-09-06
申请号：US13039574
申请日：2011-03-03
申请人： Tianhong Yan , Gopinath Balakrishnan , Jeffrey Koon Yee Lee , Tz-yi Liu
发明人： Tianhong Yan , Gopinath Balakrishnan , Jeffrey Koon Yee Lee , Tz-yi Liu
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/1006 , G11C7/1012 , G11C7/1039 , G11C7/18 , G11C8/08 , G11C8/18 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C13/0069 , G11C17/16
摘要： A monolithic three dimensional array of non-volatile storage elements is arranged in blocks. The non-volatile storage elements are connected to bit lines and word lines. The bit lines for each block are grouped into columns of bit lines. The columns of bit lines include top columns of bit lines that are connected to selection circuits on a top side of a respective block and bottom columns of bit lines that are connected to selection circuits on a bottom side of the respective block. Programming of data is pipelined between two or more columns of bit lines in order to increase programming speed. One embodiment of the programming process includes selectively connecting two columns of bit lines to a set of one or more selection circuits, using the one or more selection circuits to selectively connect one of the two columns of bit lines to one or more signal sources, programming non-volatile storage elements for the column of bit lines that is currently connected to the one or more signal sources, and changing one of the columns of bit lines connected to the set of one or more selection circuits while another column of bit lines is being programmed.
摘要翻译：非易失性存储元件的单片三维阵列以块状排列。非易失性存储元件连接到位线和字线。每个块的位线被分组成位线列。位线列包括连接到相应块的顶侧上的选择电路的位线列和连接到相应块的底侧上的选择电路的位线的底列。数据的编程在两列或更多列的位线之间流水线化，以提高编程速度。编程过程的一个实施例包括使用一个或多个选择电路选择性地将两列位线连接到一组或多个选择电路，以选择性地将两列位线中的一列连接到一个或多个信号源，编程用于当前连接到一个或多个信号源的位线列的非易失性存储元件，以及改变连接到一组或多个选择电路的位线的列之一，而另一列位线正在被程序。

3. 发明授权

US08223525B2 Page register outside array and sense amplifier interface 有权
标题翻译：页面寄存器外部阵列和读出放大器接口
公开(公告)号：US08223525B2
公开(公告)日：2012-07-17
申请号：US12638719
申请日：2009-12-15
申请人： Gopinath Balakrishnan , Jeffrey Koon Yee Lee , Yuheng Zhang , Tz-Yi Liu , Luca Fasoli
发明人： Gopinath Balakrishnan , Jeffrey Koon Yee Lee , Yuheng Zhang , Tz-Yi Liu , Luca Fasoli
IPC分类号： G11C5/06
CPC分类号： G11C5/025 , B82Y10/00 , G11C5/02 , G11C13/0002 , G11C13/0007 , G11C13/025 , G11C17/16 , G11C2213/19 , G11C2213/32 , G11C2213/33 , G11C2213/34 , G11C2213/71
摘要： A non-volatile storage device includes a substrate, a monolithic three-dimensional memory array of non-volatile storage elements arranged above a portion of the substrate, a plurality of sense amplifiers in communication with the non-volatile storage elements, a plurality of temporary storage devices in communication with the sense amplifiers, a page register in communication with the temporary storage devices, and one or more control circuits. The one or more control circuits are in communication with the page register, the temporary storage devices and the sense amplifiers. The sense amplifiers are arranged on the substrate underneath the monolithic three-dimensional memory array. The temporary storage devices are arranged on the substrate underneath the monolithic three-dimensional memory array. The page register is arranged on the substrate in an area that is not underneath the monolithic three-dimensional memory array. Data read from the non-volatile storage elements by the sense amplifiers is transferred to the temporary storage devices and then to the page register in response to the one or more control circuits. Data to be programmed into the non-volatile storage elements is transferred to the temporary storage devices from the page register in response to the one or more control circuits.
摘要翻译：非易失性存储装置包括衬底，布置在衬底的一部分上方的非易失性存储元件的单片三维存储器阵列，与非易失性存储元件通信的多个读出放大器，多个临时与读出放大器通信的存储装置，与临时存储装置通信的页寄存器，以及一个或多个控制电路。一个或多个控制电路与页寄存器，临时存储设备和读出放大器通信。读出放大器布置在单片三维存储器阵列下方的衬底上。临时存储装置布置在单片三维存储器阵列下面的衬底上。页面寄存器在不在单片三维存储器阵列下方的区域中布置在基板上。由感测放大器从非易失性存储元件读取的数据响应于一个或多个控制电路传送到临时存储设备，然后传送到页寄存器。要编程到非易失性存储元件中的数据响应于一个或多个控制电路从页寄存器传送到临时存储设备。

4. 发明申请

US20110141832A1 PROGRAM CYCLE SKIP 有权
标题翻译：程序循环跳
公开(公告)号：US20110141832A1
公开(公告)日：2011-06-16
申请号：US12638729
申请日：2009-12-15
申请人： Gopinath Balakrishnan , Luca Fasoli , Tz-Yi Liu , Yuheng Zhang , Yan Li
发明人： Gopinath Balakrishnan , Luca Fasoli , Tz-Yi Liu , Yuheng Zhang , Yan Li
IPC分类号： G11C11/416 , G11C7/10
CPC分类号： G11C13/0069 , G11C5/02 , G11C13/0007 , G11C13/0061 , G11C17/165 , G11C17/18 , G11C2013/0076 , G11C2013/0085 , G11C2213/71
摘要： A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.
摘要翻译：非易失性存储系统包括在编程页面（或其他单元）数据时跳过编程周期的技术。在对页面（或其他单元）数据的当前子集进行编程时，系统将评估页面（或其他单元）的下一个子集是否应编程为非易失性存储元素或跳过。不应被跳过的页面（或其他单元）的子集被编程到非易失性存储元件中。一些实施例包括将适当数据传送到临时锁存器/寄存器，以准备编程，同时评估是编程还是跳过编程。

5. 发明申请

US20100106893A1 PAGE BUFFER PROGRAM COMMAND AND METHODS TO REPROGRAM PAGES WITHOUT RE-INPUTTING DATA TO A MEMORY DEVICE 有权
标题翻译：页面缓存程序命令和方法来重现数据到存储器件
公开(公告)号：US20100106893A1
公开(公告)日：2010-04-29
申请号：US12414925
申请日：2009-03-31
申请人： Luca Fasoli , Yuheng Zhang , Gopinath Balakrishnan
发明人： Luca Fasoli , Yuheng Zhang , Gopinath Balakrishnan
IPC分类号： G06F12/02 , G06F12/06 , G06F12/00
CPC分类号： G11C16/102 , G06F12/0246
摘要： A technique for efficiently handling write operation failures in a memory device which communicates with an external host device allows a page of data to be re-written to a memory array from a page buffer. The host provides user data, a first write address and a write command to the memory device. If the write attempt fails, the host provides a re-write command with a new address, without re-sending the user data to the memory device. Additional data can be received at a data cache of the memory device while a re-write from the page buffer is in progress. The re-written data may be obtained in a copy operation in which the data is read out to the host, modified and written back to the memory device. Additional data can be input to the memory device during the copy operation. Page buffer data can also be modified in place.
摘要翻译：一种用于在与外部主机设备通信的存储设备中有效地处理写入操作故障的技术允许从页面缓冲器将数据页面重写到存储器阵列。主机向存储设备提供用户数据，第一写地址和写命令。如果写入尝试失败，则主机提供具有新地址的重写命令，而不会将用户数据重新发送到存储设备。在来自页面缓冲器的重新写入正在进行时，可以在存储器件的数据高速缓存处接收附加数据。重新写入的数据可以在数据被读出到主机的复制操作中获得，被修改并写回存储器件。在复制操作期间可以向存储器件输入附加数据。页面缓冲区数据也可以进行修改。

6. 发明授权

US08427890B2 Program cycle skip 有权
标题翻译：程序循环跳过
公开(公告)号：US08427890B2
公开(公告)日：2013-04-23
申请号：US13488609
申请日：2012-06-05
申请人： Gopinath Balakrishnan , Luca Fasoli , Tz-Yi Liu , Yuheng Zhang , Yan Li
发明人： Gopinath Balakrishnan , Luca Fasoli , Tz-Yi Liu , Yuheng Zhang , Yan Li
IPC分类号： G11C7/00
CPC分类号： G11C13/0069 , G11C5/02 , G11C13/0007 , G11C13/0061 , G11C17/165 , G11C17/18 , G11C2013/0076 , G11C2013/0085 , G11C2213/71
摘要： A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.
摘要翻译：非易失性存储系统包括在编程页面（或其他单元）数据时跳过编程周期的技术。在对页面（或其他单元）数据的当前子集进行编程时，系统将评估页面（或其他单元）的下一个子集是否应编程为非易失性存储元素或跳过。不应被跳过的页面（或其他单元）的子集被编程到非易失性存储元件中。一些实施例包括将适当数据传送到临时锁存器/寄存器，以准备编程，同时评估是编程还是跳过编程。

7. 发明授权

US08395948B2 Program cycle skip 有权
公开(公告)号：US08395948B2
公开(公告)日：2013-03-12
申请号：US13488600
申请日：2012-06-05
申请人： Gopinath Balakrishnan , Luca Fasoli , Tz-Yi Liu , Yuheng Zhang , Yan Li
发明人： Gopinath Balakrishnan , Luca Fasoli , Tz-Yi Liu , Yuheng Zhang , Yan Li
IPC分类号： G11C7/00
CPC分类号： G11C13/0069 , G11C5/02 , G11C13/0007 , G11C13/0061 , G11C17/165 , G11C17/18 , G11C2013/0076 , G11C2013/0085 , G11C2213/71
摘要： A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.

8. 发明授权

US08374051B2 Three dimensional memory system with column pipeline 有权
标题翻译：具有柱管道的三维记忆系统
公开(公告)号：US08374051B2
公开(公告)日：2013-02-12
申请号：US13039574
申请日：2011-03-03
申请人： Tianhong Yan , Gopinath Balakrishnan , Jeffrey Koon Yee Lee , Tz-yi Liu
发明人： Tianhong Yan , Gopinath Balakrishnan , Jeffrey Koon Yee Lee , Tz-yi Liu
IPC分类号： G11C8/00
CPC分类号： G11C7/1006 , G11C7/1012 , G11C7/1039 , G11C7/18 , G11C8/08 , G11C8/18 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C13/0069 , G11C17/16
摘要： A monolithic three dimensional array of non-volatile storage elements is arranged in blocks. The non-volatile storage elements are connected to bit lines and word lines. The bit lines for each block are grouped into columns of bit lines. The columns of bit lines include top columns of bit lines that are connected to selection circuits on a top side of a respective block and bottom columns of bit lines that are connected to selection circuits on a bottom side of the respective block. Programming of data is pipelined between two or more columns of bit lines in order to increase programming speed. One embodiment of the programming process includes selectively connecting two columns of bit lines to a set of one or more selection circuits, using the one or more selection circuits to selectively connect one of the two columns of bit lines to one or more signal sources, programming non-volatile storage elements for the column of bit lines that is currently connected to the one or more signal sources, and changing one of the columns of bit lines connected to the set of one or more selection circuits while another column of bit lines is being programmed.
摘要翻译：非易失性存储元件的单片三维阵列以块状排列。非易失性存储元件连接到位线和字线。每个块的位线被分组成位线列。位线列包括连接到相应块的顶侧上的选择电路的位线列和连接到相应块的底侧上的选择电路的位线的底列。数据的编程在两列或更多列的位线之间流水线化，以提高编程速度。编程过程的一个实施例包括使用一个或多个选择电路选择性地将两列位线连接到一组或多个选择电路，以选择性地将两列位线中的一列连接到一个或多个信号源，编程用于当前连接到一个或多个信号源的位线列的非易失性存储元件，以及改变连接到一组或多个选择电路的位线的列之一，而另一列位线正在被程序。

9. 发明授权

US08397024B2 Page buffer program command and methods to reprogram pages without re-inputting data to a memory device 有权
标题翻译：页面缓冲区程序命令和重新编程页面的方法，而不会将数据重新输入到存储设备
公开(公告)号：US08397024B2
公开(公告)日：2013-03-12
申请号：US12414925
申请日：2009-03-31
申请人： Luca Fasoli , Yuheng Zhang , Gopinath Balakrishnan
发明人： Luca Fasoli , Yuheng Zhang , Gopinath Balakrishnan
IPC分类号： G06F12/00
CPC分类号： G11C16/102 , G06F12/0246
摘要： A technique for efficiently handling write operation failures in a memory device which communicates with an external host device allows a page of data to be re-written to a memory array from a page buffer. The host provides user data, a first write address and a write command to the memory device. If the write attempt fails, the host provides a re-write command with a new address, without re-sending the user data to the memory device. Additional data can be received at a data cache of the memory device while a re-write from the page buffer is in progress. The re-written data may be obtained in a copy operation in which the data is read out to the host, modified and written back to the memory device. Additional data can be input to the memory device during the copy operation. Page buffer data can also be modified in place.
摘要翻译：一种用于在与外部主机设备通信的存储设备中有效地处理写入操作故障的技术允许从页面缓冲器将数据页面重写到存储器阵列。主机向存储设备提供用户数据，第一写地址和写命令。如果写入尝试失败，则主机提供具有新地址的重写命令，而不会将用户数据重新发送到存储设备。在来自页面缓冲器的重新写入正在进行时，可以在存储器件的数据高速缓存处接收附加数据。重新写入的数据可以在数据被读出到主机的复制操作中获得，被修改并写回存储器件。在复制操作期间可以向存储器件输入附加数据。页面缓冲区数据也可以进行修改。

10. 发明申请

US20120243349A1 PROGRAM CYCLE SKIP 有权
公开(公告)号：US20120243349A1
公开(公告)日：2012-09-27
申请号：US13488609
申请日：2012-06-05
申请人： Gopinath Balakrishnan , Luca Fasoli , Tz-Yi Liu , Yuheng Zhang , Yan Li
发明人： Gopinath Balakrishnan , Luca Fasoli , Tz-Yi Liu , Yuheng Zhang , Yan Li
IPC分类号： G11C7/00
CPC分类号： G11C13/0069 , G11C5/02 , G11C13/0007 , G11C13/0061 , G11C17/165 , G11C17/18 , G11C2013/0076 , G11C2013/0085 , G11C2213/71
摘要： A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.

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