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1. 发明申请

US20110141788A1 PAGE REGISTER OUTSIDE ARRAY AND SENSE AMPLIFIER INTERFACE 有权
标题翻译：页面寄存器外部阵列和感测放大器接口
公开(公告)号：US20110141788A1
公开(公告)日：2011-06-16
申请号：US12638719
申请日：2009-12-15
申请人： Gopinath Balakrishnan , Jeffrey Koon Yee Lee , Yuheng Zhang , Tz-Yi Liu , Luca Fasoli
发明人： Gopinath Balakrishnan , Jeffrey Koon Yee Lee , Yuheng Zhang , Tz-Yi Liu , Luca Fasoli
IPC分类号： G11C5/02 , G11C11/00 , G11C7/18
CPC分类号： G11C5/025 , B82Y10/00 , G11C5/02 , G11C13/0002 , G11C13/0007 , G11C13/025 , G11C17/16 , G11C2213/19 , G11C2213/32 , G11C2213/33 , G11C2213/34 , G11C2213/71
摘要： A non-volatile storage device includes a substrate, a monolithic three-dimensional memory array of non-volatile storage elements arranged above a portion of the substrate, a plurality of sense amplifiers in communication with the non-volatile storage elements, a plurality of temporary storage devices in communication with the sense amplifiers, a page register in communication with the temporary storage devices, and one or more control circuits. The one or more control circuits are in communication with the page register, the temporary storage devices and the sense amplifiers. The sense amplifiers are arranged on the substrate underneath the monolithic three-dimensional memory array. The temporary storage devices are arranged on the substrate underneath the monolithic three-dimensional memory array. The page register is arranged on the substrate in an area that is not underneath the monolithic three-dimensional memory array. Data read from the non-volatile storage elements by the sense amplifiers is transferred to the temporary storage devices and then to the page register in response to the one or more control circuits. Data to be programmed into the non-volatile storage elements is transferred to the temporary storage devices from the page register in response to the one or more control circuits.
摘要翻译：非易失性存储装置包括衬底，布置在衬底的一部分上方的非易失性存储元件的单片三维存储器阵列，与非易失性存储元件通信的多个读出放大器，多个临时与读出放大器通信的存储装置，与临时存储装置通信的页寄存器，以及一个或多个控制电路。一个或多个控制电路与页寄存器，临时存储设备和读出放大器通信。读出放大器布置在单片三维存储器阵列下方的衬底上。临时存储装置布置在单片三维存储器阵列下面的衬底上。页面寄存器在不在单片三维存储器阵列下方的区域中布置在基板上。由感测放大器从非易失性存储元件读取的数据响应于一个或多个控制电路传送到临时存储设备，然后传送到页寄存器。要编程到非易失性存储元件中的数据响应于一个或多个控制电路从页寄存器传送到临时存储设备。

2. 发明申请

US20090323392A1 SMART DETECTION CIRCUIT FOR WRITING TO NON-VOLATILE STORAGE 有权
标题翻译：用于写入非易失性存储的智能检测电路
公开(公告)号：US20090323392A1
公开(公告)日：2009-12-31
申请号：US12339327
申请日：2008-12-19
申请人： Luca G. Fasoli , Tianhong Yan , Jeffrey Koon Yee Lee
发明人： Luca G. Fasoli , Tianhong Yan , Jeffrey Koon Yee Lee
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C16/3481 , G11C2013/0066 , G11C2213/32 , G11C2213/72
摘要： A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and a circuit for detecting the setting and resetting of the reversible resistance-switching elements.
摘要翻译：存储器系统包括衬底，衬底上的控制电路，包括具有可逆电阻切换元件的多个存储单元的三维存储器阵列（衬底上方），以及用于检测可逆电阻的设置和复位的电路开关元件

3. 发明申请

US20120224408A1 THREE DIMENSIONAL MEMORY SYSTEM WITH COLUMN PIPELINE 有权
标题翻译：具有柱管的三维存储系统
公开(公告)号：US20120224408A1
公开(公告)日：2012-09-06
申请号：US13039574
申请日：2011-03-03
申请人： Tianhong Yan , Gopinath Balakrishnan , Jeffrey Koon Yee Lee , Tz-yi Liu
发明人： Tianhong Yan , Gopinath Balakrishnan , Jeffrey Koon Yee Lee , Tz-yi Liu
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/1006 , G11C7/1012 , G11C7/1039 , G11C7/18 , G11C8/08 , G11C8/18 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C13/0069 , G11C17/16
摘要： A monolithic three dimensional array of non-volatile storage elements is arranged in blocks. The non-volatile storage elements are connected to bit lines and word lines. The bit lines for each block are grouped into columns of bit lines. The columns of bit lines include top columns of bit lines that are connected to selection circuits on a top side of a respective block and bottom columns of bit lines that are connected to selection circuits on a bottom side of the respective block. Programming of data is pipelined between two or more columns of bit lines in order to increase programming speed. One embodiment of the programming process includes selectively connecting two columns of bit lines to a set of one or more selection circuits, using the one or more selection circuits to selectively connect one of the two columns of bit lines to one or more signal sources, programming non-volatile storage elements for the column of bit lines that is currently connected to the one or more signal sources, and changing one of the columns of bit lines connected to the set of one or more selection circuits while another column of bit lines is being programmed.
摘要翻译：非易失性存储元件的单片三维阵列以块状排列。非易失性存储元件连接到位线和字线。每个块的位线被分组成位线列。位线列包括连接到相应块的顶侧上的选择电路的位线列和连接到相应块的底侧上的选择电路的位线的底列。数据的编程在两列或更多列的位线之间流水线化，以提高编程速度。编程过程的一个实施例包括使用一个或多个选择电路选择性地将两列位线连接到一组或多个选择电路，以选择性地将两列位线中的一列连接到一个或多个信号源，编程用于当前连接到一个或多个信号源的位线列的非易失性存储元件，以及改变连接到一组或多个选择电路的位线的列之一，而另一列位线正在被程序。

4. 发明授权

US08223525B2 Page register outside array and sense amplifier interface 有权
标题翻译：页面寄存器外部阵列和读出放大器接口
公开(公告)号：US08223525B2
公开(公告)日：2012-07-17
申请号：US12638719
申请日：2009-12-15
申请人： Gopinath Balakrishnan , Jeffrey Koon Yee Lee , Yuheng Zhang , Tz-Yi Liu , Luca Fasoli
发明人： Gopinath Balakrishnan , Jeffrey Koon Yee Lee , Yuheng Zhang , Tz-Yi Liu , Luca Fasoli
IPC分类号： G11C5/06
CPC分类号： G11C5/025 , B82Y10/00 , G11C5/02 , G11C13/0002 , G11C13/0007 , G11C13/025 , G11C17/16 , G11C2213/19 , G11C2213/32 , G11C2213/33 , G11C2213/34 , G11C2213/71
摘要： A non-volatile storage device includes a substrate, a monolithic three-dimensional memory array of non-volatile storage elements arranged above a portion of the substrate, a plurality of sense amplifiers in communication with the non-volatile storage elements, a plurality of temporary storage devices in communication with the sense amplifiers, a page register in communication with the temporary storage devices, and one or more control circuits. The one or more control circuits are in communication with the page register, the temporary storage devices and the sense amplifiers. The sense amplifiers are arranged on the substrate underneath the monolithic three-dimensional memory array. The temporary storage devices are arranged on the substrate underneath the monolithic three-dimensional memory array. The page register is arranged on the substrate in an area that is not underneath the monolithic three-dimensional memory array. Data read from the non-volatile storage elements by the sense amplifiers is transferred to the temporary storage devices and then to the page register in response to the one or more control circuits. Data to be programmed into the non-volatile storage elements is transferred to the temporary storage devices from the page register in response to the one or more control circuits.
摘要翻译：非易失性存储装置包括衬底，布置在衬底的一部分上方的非易失性存储元件的单片三维存储器阵列，与非易失性存储元件通信的多个读出放大器，多个临时与读出放大器通信的存储装置，与临时存储装置通信的页寄存器，以及一个或多个控制电路。一个或多个控制电路与页寄存器，临时存储设备和读出放大器通信。读出放大器布置在单片三维存储器阵列下方的衬底上。临时存储装置布置在单片三维存储器阵列下面的衬底上。页面寄存器在不在单片三维存储器阵列下方的区域中布置在基板上。由感测放大器从非易失性存储元件读取的数据响应于一个或多个控制电路传送到临时存储设备，然后传送到页寄存器。要编程到非易失性存储元件中的数据响应于一个或多个控制电路从页寄存器传送到临时存储设备。

5. 发明授权

US08374051B2 Three dimensional memory system with column pipeline 有权
标题翻译：具有柱管道的三维记忆系统
公开(公告)号：US08374051B2
公开(公告)日：2013-02-12
申请号：US13039574
申请日：2011-03-03
申请人： Tianhong Yan , Gopinath Balakrishnan , Jeffrey Koon Yee Lee , Tz-yi Liu
发明人： Tianhong Yan , Gopinath Balakrishnan , Jeffrey Koon Yee Lee , Tz-yi Liu
IPC分类号： G11C8/00
CPC分类号： G11C7/1006 , G11C7/1012 , G11C7/1039 , G11C7/18 , G11C8/08 , G11C8/18 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C13/0069 , G11C17/16
摘要： A monolithic three dimensional array of non-volatile storage elements is arranged in blocks. The non-volatile storage elements are connected to bit lines and word lines. The bit lines for each block are grouped into columns of bit lines. The columns of bit lines include top columns of bit lines that are connected to selection circuits on a top side of a respective block and bottom columns of bit lines that are connected to selection circuits on a bottom side of the respective block. Programming of data is pipelined between two or more columns of bit lines in order to increase programming speed. One embodiment of the programming process includes selectively connecting two columns of bit lines to a set of one or more selection circuits, using the one or more selection circuits to selectively connect one of the two columns of bit lines to one or more signal sources, programming non-volatile storage elements for the column of bit lines that is currently connected to the one or more signal sources, and changing one of the columns of bit lines connected to the set of one or more selection circuits while another column of bit lines is being programmed.
摘要翻译：非易失性存储元件的单片三维阵列以块状排列。非易失性存储元件连接到位线和字线。每个块的位线被分组成位线列。位线列包括连接到相应块的顶侧上的选择电路的位线列和连接到相应块的底侧上的选择电路的位线的底列。数据的编程在两列或更多列的位线之间流水线化，以提高编程速度。编程过程的一个实施例包括使用一个或多个选择电路选择性地将两列位线连接到一组或多个选择电路，以选择性地将两列位线中的一列连接到一个或多个信号源，编程用于当前连接到一个或多个信号源的位线列的非易失性存储元件，以及改变连接到一组或多个选择电路的位线的列之一，而另一列位线正在被程序。

6. 发明授权

US08111539B2 Smart detection circuit for writing to non-volatile storage 有权
标题翻译：用于写入非易失性存储的智能检测电路
公开(公告)号：US08111539B2
公开(公告)日：2012-02-07
申请号：US12339327
申请日：2008-12-19
申请人： Luca G. Fasoli , Tianhong Yan , Jeffrey Koon Yee Lee
发明人： Luca G. Fasoli , Tianhong Yan , Jeffrey Koon Yee Lee
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C16/3481 , G11C2013/0066 , G11C2213/32 , G11C2213/72
摘要： A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and a circuit for detecting the setting and resetting of the reversible resistance-switching elements.
摘要翻译：存储器系统包括衬底，衬底上的控制电路，包括具有可逆电阻切换元件的多个存储单元的三维存储器阵列（衬底上方），以及用于检测可逆电阻的设置和复位的电路开关元件

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