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1. 发明申请

US20120266123A1 COHERENT ANALYSIS OF ASYMMETRIC AGING AND STATISTICAL PROCESS VARIATION IN ELECTRONIC CIRCUITS 审中-公开
标题翻译：电子电路不对称老化与统计过程变化的相关分析
公开(公告)号：US20120266123A1
公开(公告)日：2012-10-18
申请号：US13084582
申请日：2011-04-12
申请人： Palkesh JAIN , Vinod Menezes , Francisco Cano
发明人： Palkesh JAIN , Vinod Menezes , Francisco Cano
IPC分类号： G06F9/455
CPC分类号： G06F17/5009 , G06F17/5036
摘要： Coherent analysis of asymmetric aging and statistical process variation. A method of designing a circuit includes preparing an initial netlist of components in the circuit. A plurality of components is selected from the initial netlist by a first statistical process. Further, a process variation netlist is prepared by replacing a plurality of initial operating parameters of the plurality of components with a plurality of process variation operating parameters. A plurality of high stress components is then identified in the process variation netlist and an aged netlist is prepared by replacing a set of operating parameters of the plurality of high stress components with a set of degraded operating parameters. The circuit is simulated using the aged netlist. The method also includes modifying the initial netlist according to a result of simulation and repeating the foregoing steps until a desired circuit performance is obtained.
摘要翻译：不对称老化和统计过程变化的相干分析。一种设计电路的方法包括准备电路中的元件的初始网表。通过第一统计过程从初始网表中选择多个组件。此外，通过用多个处理变化操作参数替换多个分量的多个初始操作参数来准备过程变化网表。然后在过程变化网表中识别多个高应力分量，并且通过用一组降级的操作参数替换多个高应力分量的一组操作参数来制备老化的网表。使用老化的网表模拟电路。该方法还包括根据仿真结果修改初始网表，并重复前述步骤，直到获得所需的电路性能。

2. 发明授权

US08379465B2 Combined write assist and retain-till-accessed memory array bias 有权
标题翻译：组合写入辅助和保留直到存取存储器阵列偏置
公开(公告)号：US08379465B2
公开(公告)日：2013-02-19
申请号：US12764399
申请日：2010-04-21
申请人： Michael Patrick Clinton , Lakshmikantha V. Holla , Vinod Menezes
发明人： Michael Patrick Clinton , Lakshmikantha V. Holla , Vinod Menezes
IPC分类号： G11C7/00 , G11C11/00 , G11C5/14
CPC分类号： G11C11/413
摘要： Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode and with write assist bias in a normal operating mode. The memory is constructed of multiple memory array blocks of SRAM cells. Bias devices are associated with each memory array block, and associated with one or more columns. Each bias device includes a diode-connected transistor in parallel with a shorting transistor, between a power supply voltage and a power supply bias node for cells in its column or columns. The shorting transistor receives control signals from control logic so that the diode-connected transistor for each column is shorted during read cycles, and in write cycles in which its columns are not selected; in write cycles in which its columns are selected, the shorting transistor in the bias device is turned off, so that a reduced power supply voltage is applied to the selected column. The shorting transistors for all columns in the block are turned off in the RTA mode. An additional transistor in series with the diode-connected transistor may be included, to enable a floating power supply bias mode.
摘要翻译：具有保持直读访问（RTA）模式的静态随机存取存储器（SRAM）的偏置电路，以及正常工作模式下的写入辅助偏置。存储器由SRAM单元的多个存储器阵列块构成。偏置设备与每个存储器阵列块相关联，并且与一个或多个列相关联。每个偏置装置包括与短路晶体管并联的二极管连接的晶体管，在电源电压和用于其列或列中的单元的电源偏置节点之间。短路晶体管接收来自控制逻辑的控制信号，使得每个列的二极管连接的晶体管在读周期期间以及在不选择其列的写周期中短路; 在选择其列的写周期中，偏置装置中的短路晶体管截止，使得降低的电源电压被施加到所选择的列。块中所有列的短路晶体管在RTA模式下关闭。可以包括与二极管连接的晶体管串联的附加晶体管，以实现浮置电源偏置模式。

3. 发明申请

US20110261632A1 Combined Write Assist and Retain-Till-Accessed Memory Array Bias 有权
标题翻译：组合写入辅助和保留直接存取存储器阵列偏置
公开(公告)号：US20110261632A1
公开(公告)日：2011-10-27
申请号：US12764399
申请日：2010-04-21
申请人： Michael Patrick Clinton , Lakshmikantha V. Holla , Vinod Menezes
发明人： Michael Patrick Clinton , Lakshmikantha V. Holla , Vinod Menezes
IPC分类号： G11C7/00
CPC分类号： G11C11/413
摘要： Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode and with write assist bias in a normal operating mode. The memory is constructed of multiple memory array blocks of SRAM cells. Bias devices are associated with each memory array block, and associated with one or more columns. Each bias device includes a diode-connected transistor in parallel with a shorting transistor, between a power supply voltage and a power supply bias node for cells in its column or columns. The shorting transistor receives control signals from control logic so that the diode-connected transistor for each column is shorted during read cycles, and in write cycles in which its columns are not selected; in write cycles in which its columns are selected, the shorting transistor in the bias device is turned off, so that a reduced power supply voltage is applied to the selected column. The shorting transistors for all columns in the block are turned off in the RTA mode. An additional transistor in series with the diode-connected transistor may be included, to enable a floating power supply bias mode.
摘要翻译：具有保持直读访问（RTA）模式的静态随机存取存储器（SRAM）的偏置电路，以及正常工作模式下的写入辅助偏置。存储器由SRAM单元的多个存储器阵列块构成。偏置设备与每个存储器阵列块相关联，并且与一个或多个列相关联。每个偏置装置包括与短路晶体管并联的二极管连接的晶体管，在电源电压和用于其列或列中的单元的电源偏置节点之间。短路晶体管接收来自控制逻辑的控制信号，使得每个列的二极管连接的晶体管在读周期期间以及在不选择其列的写周期中短路; 在选择其列的写周期中，偏置装置中的短路晶体管截止，使得降低的电源电压被施加到所选择的列。块中所有列的短路晶体管在RTA模式下关闭。可以包括与二极管连接的晶体管串联的附加晶体管，以实现浮置电源偏置模式。

4. 发明授权

US08812885B2 Detecting wake-up events for a chip based on an I/O power supply 有权
标题翻译：基于I / O电源检测芯片的唤醒事件
公开(公告)号：US08812885B2
公开(公告)日：2014-08-19
申请号：US11695304
申请日：2007-04-02
申请人： Philippe Royannez , Gilles Dubost , Christophe Vatinel , William Douglas Wilson , Vinod Menezes , Hugh Mair , James Sangwon Song
发明人： Philippe Royannez , Gilles Dubost , Christophe Vatinel , William Douglas Wilson , Vinod Menezes , Hugh Mair , James Sangwon Song
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A device is provided that includes a chip having a processor and wake-up logic. The device also includes power management circuitry coupled to the chip. The power management circuitry selectively provides a core power supply and an input/output (I/O) power supply to the chip. Even if the power management circuitry cuts off the core power supply to the chip, the wake-up logic detects and responds to wake-up events based on power provided by the I/O power supply.
摘要翻译：提供了一种包括具有处理器和唤醒逻辑的芯片的设备。该装置还包括耦合到芯片的电源管理电路。电源管理电路选择性地向芯片提供核心电源和输入/输出（I / O）电源。即使电源管理电路切断芯片的核心电源，唤醒逻辑也会根据I / O电源提供的电源来检测和响应唤醒事件。

5. 发明申请

US20080162969A1 DETECTING WAKE-UP EVENTS FOR A CHIP BASED ON AN I/O POWER SUPPLY 有权
标题翻译：检测基于I / O电源的芯片的唤醒事件
公开(公告)号：US20080162969A1
公开(公告)日：2008-07-03
申请号：US11695304
申请日：2007-04-02
申请人： Philippe Royannez , Gilles Dubost , Christophe Vantinel , William Douglas Wilson , Vinod Menezes , Hugh Mair , James Sangwon Song
发明人： Philippe Royannez , Gilles Dubost , Christophe Vantinel , William Douglas Wilson , Vinod Menezes , Hugh Mair , James Sangwon Song
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A device is provided that includes a chip having a processor and wake-up logic. The device also includes power management circuitry coupled to the chip. The power management circuitry selectively provides a core power supply and an input/output (I/O) power supply to the chip. Even if the power management circuitry cuts off the core power supply to the chip, the wake-up logic detects and responds to wake-up events based on power provided by the I/O power supply.
摘要翻译：提供了一种包括具有处理器和唤醒逻辑的芯片的设备。该装置还包括耦合到芯片的电源管理电路。电源管理电路选择性地向芯片提供核心电源和输入/输出（I / O）电源。即使电源管理电路切断芯片的核心电源，唤醒逻辑也会根据I / O电源提供的电源来检测和响应唤醒事件。

6. 发明授权

US06237017B1 Lossy technique for image and speech processing 失效
标题翻译：图像和语音处理的有损技术
公开(公告)号：US06237017B1
公开(公告)日：2001-05-22
申请号：US08638071
申请日：1996-04-25
申请人： Vinod Menezes
发明人： Vinod Menezes
IPC分类号： G06G702
CPC分类号： G06J1/00
摘要： The present invention includes a data compression system which implements transformation and quantization functions using analog devites. The system includes a transformation module with analog devices (22), a quantization module with analog devices (24) and an entropy coding module (26). A data decompression system which implements inverse transformation and inverse quantization functions using analog devices is also shown.
摘要翻译：本发明包括使用模拟视频实现变换和量化功能的数据压缩系统。该系统包括具有模拟设备（22），具有模拟设备（24）的量化模块和熵编码模块（26）的变换模块。还示出了使用模拟设备实现逆变换和逆量化功能的数据解压缩系统。

7. 发明申请

US20100007374A1 ON-DIE THEVENIN TERMINATION FOR HIGH SPEED I/O INTERFACE 审中-公开
标题翻译：用于高速I / O接口的ON-DIE THEVENIN终端
公开(公告)号：US20100007374A1
公开(公告)日：2010-01-14
申请号：US12172282
申请日：2008-07-14
申请人： Rajat Chauhan , Karthik Rajagopal , Vinod Menezes
发明人： Rajat Chauhan , Karthik Rajagopal , Vinod Menezes
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H04L25/0278
摘要： The method, system, and apparatus of on-die Thevenin termination for high speed I/O interface are disclosed. In one embodiment, a system of terminating a transmission line of a chip includes a pull-up circuit located within the chip comprising a voltage source and a positive switch device coupled with the transmission line of the chip, a pull-down circuit located within the chip comprising a ground and a negative switch device coupled with the transmission line of the chip, a resistor located within the chip coupled with the voltage source, the positive switch device, the ground, the negative switch device, and a pad coupled with the resistor to terminate the transmission line of the chip. The system may include resistors coupled in parallel with each other. The system may include an impedance module to determine a load impedance value as seen from the pad that matches a source impedance value.
摘要翻译：公开了用于高速I / O接口的片上戴维宁终端的方法，系统和装置。在一个实施例中，终止芯片的传输线的系统包括位于芯片内的上拉电路，该上拉电路包括与芯片的传输线耦合的电压源和正开关装置，位于该芯片内的下拉电路芯片包括与芯片的传输线耦合的接地和负开关器件，位于与电压源耦合的芯片内的电阻器，正开关器件，地，负开关器件以及与电阻器耦合的焊盘终止芯片的传输线。该系统可以包括彼此并联耦合的电阻。系统可以包括阻抗模块，用于确定从焊盘看到的与源阻抗值匹配的负载阻抗值。

8. 发明授权

US06563349B2 Multiplexor generating a glitch free output when selecting from multiple clock signals 有权
标题翻译：多路复用器从多个时钟信号中选择时产生无毛刺的输出
公开(公告)号：US06563349B2
公开(公告)日：2003-05-13
申请号：US09891541
申请日：2001-06-27
申请人： Vinod Menezes , Rajith Kumar Mavila
发明人： Vinod Menezes , Rajith Kumar Mavila
IPC分类号： H03K1700
CPC分类号： G06F1/08
摘要： A multiplexor generating a glitch free output. A slower clock signal and sleep clock signal are respectively synchronized with positive and negative edges of the faster clock signal. The sleep signal is further synchronized with a negative edge of the slower clock signal and provided to an AND gate gating the slower clock signal based on the value of a select signal formed by the synchronized sleep signal. The slower clock signal is delayed by a number of faster clock cycles equal to the time taken by the select signal to be received at the AND gate after the sleep signal is synchronized to the slower clock signal. In an alternative embodiment, a signal control block ensures that the 0 to 1 transition on one of the select signals follows the 1 to 0 transition on another select signal when the value of the sleep signal changes. In addition, each select signal is synchronized with a negative edge of the corresponding clock signal selected.
摘要翻译：多路复用器产生无毛刺输出。较慢的时钟信号和睡眠时钟信号分别与较快时钟信号的正和负边沿同步。休眠信号进一步与较慢时钟信号的下降沿同步，并提供给基于由同步睡眠信号形成的选择信号的值门控较慢时钟信号的“与”门。较慢的时钟信号被延迟了等于在睡眠信号与较慢时钟信号同步之后在与门接收的选择信号所花费的时间的更快的时钟周期。在替代实施例中，当睡眠信号的值改变时，信号控制块确保在其中一个选择信号上的0至1转换在另一选择信号上的1至0转换之后。此外，每个选择信号与所选择的相应时钟信号的下降沿同步。

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