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1. 发明申请

US20100313003A1 Automatic Save and Restore Configuration Mechanism 有权
标题翻译：自动保存和恢复配置机制
公开(公告)号：US20100313003A1
公开(公告)日：2010-12-09
申请号：US12478715
申请日：2009-06-04
申请人： Alain Breton , Christophe Vatinel , Sivayya Venkata Ayinala
发明人： Alain Breton , Christophe Vatinel , Sivayya Venkata Ayinala
IPC分类号： G06F15/177 , G06F1/32 , G06F1/26
CPC分类号： G06F1/30 , G06F11/1441
摘要： According to various illustrative embodiments, an apparatus, system, and method for automatically saving and restoring pad configuration registers implemented in a core power domain are described. In one aspect, the apparatus comprises a save and restore logic component implemented in the core power domain and coupled to the pad configuration registers. The apparatus also comprises a memory instantiated in an always-on power domain and coupled to the save and restore logic component, the save and restore logic component implemented in the core power domain to automatically save the pad configuration registers in the memory in a pad configuration save process before a power supply to the core power domain is switched off and to automatically restore the pad configuration registers from the memory in a pad configuration restore process after the power supply to the core power domain is switched on.
摘要翻译：根据各种说明性实施例，描述了用于自动保存和恢复在核心功率域中实现的焊盘配置寄存器的装置，系统和方法。在一个方面，该装置包括在核心功率域中实现并耦合到焊盘配置寄存器的保存和恢复逻辑部件。该设备还包括在永远在线功率域中实例化的存储器，并且耦合到保存和恢复逻辑组件，在核心功率域中实现的保存和恢复逻辑组件，以自动将焊盘配置寄存器保存在存储器中的焊盘配置在核心电源域的电源被接通之前，在关闭核心电源域的电源之前关闭保存处理并在焊盘配置恢复过程中自动地从存储器恢复焊盘配置寄存器。

2. 发明授权

US08117428B2 Apparatus and method for automatically saving and restoring pad configuration registers implemented in a core power domain 有权
标题翻译：用于自动保存和恢复在核心电源域中实现的焊盘配置寄存器的装置和方法
公开(公告)号：US08117428B2
公开(公告)日：2012-02-14
申请号：US12478715
申请日：2009-06-04
申请人： Alain Breton , Christophe Vatinel , Sivayya Venkata Ayinala
发明人： Alain Breton , Christophe Vatinel , Sivayya Venkata Ayinala
IPC分类号： G06F9/24 , G06F15/177
CPC分类号： G06F1/30 , G06F11/1441
摘要： According to various illustrative embodiments, an apparatus, system, and method for automatically saving and restoring pad configuration registers implemented in a core power domain are described. In one aspect, the apparatus comprises a save and restore logic component implemented in the core power domain and coupled to the pad configuration registers. The apparatus also comprises a memory instantiated in an always-on power domain and coupled to the save and restore logic component, the save and restore logic component implemented in the core power domain to automatically save the pad configuration registers in the memory in a pad configuration save process before a power supply to the core power domain is switched off and to automatically restore the pad configuration registers from the memory in a pad configuration restore process after the power supply to the core power domain is switched on.
摘要翻译：根据各种说明性实施例，描述了用于自动保存和恢复在核心功率域中实现的焊盘配置寄存器的装置，系统和方法。在一个方面，该装置包括在核心功率域中实现并耦合到焊盘配置寄存器的保存和恢复逻辑部件。该设备还包括在永远在线功率域中实例化的存储器，并且耦合到保存和恢复逻辑组件，在核心功率域中实现的保存和恢复逻辑组件，以自动将焊盘配置寄存器保存在存储器中的焊盘配置在核心电源域的电源被接通之前，在关闭核心电源域的电源之前关闭保存处理并在焊盘配置恢复过程中自动地从存储器恢复焊盘配置寄存器。

3. 发明授权

US08812885B2 Detecting wake-up events for a chip based on an I/O power supply 有权
标题翻译：基于I / O电源检测芯片的唤醒事件
公开(公告)号：US08812885B2
公开(公告)日：2014-08-19
申请号：US11695304
申请日：2007-04-02
申请人： Philippe Royannez , Gilles Dubost , Christophe Vatinel , William Douglas Wilson , Vinod Menezes , Hugh Mair , James Sangwon Song
发明人： Philippe Royannez , Gilles Dubost , Christophe Vatinel , William Douglas Wilson , Vinod Menezes , Hugh Mair , James Sangwon Song
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A device is provided that includes a chip having a processor and wake-up logic. The device also includes power management circuitry coupled to the chip. The power management circuitry selectively provides a core power supply and an input/output (I/O) power supply to the chip. Even if the power management circuitry cuts off the core power supply to the chip, the wake-up logic detects and responds to wake-up events based on power provided by the I/O power supply.
摘要翻译：提供了一种包括具有处理器和唤醒逻辑的芯片的设备。该装置还包括耦合到芯片的电源管理电路。电源管理电路选择性地向芯片提供核心电源和输入/输出（I / O）电源。即使电源管理电路切断芯片的核心电源，唤醒逻辑也会根据I / O电源提供的电源来检测和响应唤醒事件。

4. 发明授权

US06323715B1 Method and apparatus for selecting a clock signal without producing a glitch 失效
标题翻译：用于选择时钟信号而不产生毛刺的方法和装置
公开(公告)号：US06323715B1
公开(公告)日：2001-11-27
申请号：US09475697
申请日：1999-12-30
申请人： Christophe Vatinel
发明人： Christophe Vatinel
IPC分类号： H03K1762
CPC分类号： G06F1/04 , H03K17/005
摘要： A method and apparatus adapted for glitchless switching between unrelated clock signals is achieved using simple AND/OR logic gates to form the circuit that synchronizes the clock inputs. In an example embodiment of the present invention, two clock signals are generated along with a select input signal capable of deselecting one of the clock signals and delaying selection of the second clock input signal. The first and second clock signals and the select input signal are multiplexed to generate a multiplexed output clock signal corresponding to one of the input clock signals. A selection delay is generated between the deselection of the first clock signal and the selection the second clock signal that is longer than the low pulse width of the minimum low pulse width of the first clock signal and the low pulse width of the second clock signal, such that switching between clock signals will not create a glitch at the multiplexed output.
摘要翻译：使用简单的AND / OR逻辑门来实现适用于不相关的时钟信号之间的无故障切换的方法和装置，以形成同步时钟输入的电路。在本发明的示例实施例中，产生两个时钟信号以及能够取消选择时钟信号之一并延迟第二时钟输入信号的选择的选择输入信号。第一和第二时钟信号和选择输入信号被多路复用以产生对应于一个输入时钟信号的复用的输出时钟信号。在第一时钟信号的取消选择和选择长于第一时钟信号的最小低脉冲宽度的低脉冲宽度和第二时钟信号的低脉冲宽度的第二时钟信号之间产生选择延迟，使得时钟信号之间的切换不会在复用的输出端产生毛刺。

5. 发明授权

US6078937A Barrel shifter, circuit and method of manipulating a bit pattern 失效
标题翻译：桶式移位器，电路和操作位模式的方法
公开(公告)号：US6078937A
公开(公告)日：2000-06-20
申请号：US770623
申请日：1996-12-19
申请人： Christophe Vatinel
发明人： Christophe Vatinel
IPC分类号： G06F5/01 , G06F7/76 , G06F7/00
CPC分类号： G06F7/768 , G06F5/015
摘要： The present invention provides for a circuit comprising: an input operable to receive a bit pattern; a shifter configured to selectively shift the bit pattern; a data output operable to output the bit pattern; and a sign extension operator coupled with the data output and operable to provide a sign extension signal thereto. The present invention additionally discloses a barrel shifter and a method for manipulating a bit pattern.
摘要翻译：本发明提供一种电路，包括：可操作以接收位模式的输入; 移位器，被配置为选择性地移位所述位模式; 可操作以输出位模式的数据输出; 以及与数据输出相结合的符号扩展运算符，可操作以向其提供符号扩展信号。本发明另外公开了一种桶形移位器和一种用于操纵位图案的方法。

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