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1. 发明授权

US07725781B2 Repair techniques for memory with multiple redundancy 失效
标题翻译：具有多重冗余的内存修复技术
公开(公告)号：US07725781B2
公开(公告)日：2010-05-25
申请号：US12017091
申请日：2008-01-21
申请人： Warren Kurt Howlett
发明人： Warren Kurt Howlett
IPC分类号： G11C29/00
CPC分类号： G11C29/848
摘要： In one aspect, the present invention features techniques for generating a repair solution for a memory having a set of IOs including a plurality of main IOs and a plurality of redundant IOs. For example, techniques are provided for selecting a mapping between input/output ports of the memory and a subset of the memory's IOs. In particular, techniques are provided for configuring a plurality of multiplexors to implement the selected mapping by establishing electrical connections between the subset of IOs and the memory input/output ports. The subset of IOs may include one or more of the plurality of redundant IOs which effectively replace one or more defective ones of the main IOs. The plurality of multiplexors may be configured by generating one or more thermometer codes which encode the identities of any defective main IOs and which serve as selection inputs to the plurality of multiplexors.
摘要翻译：在一个方面，本发明的特征在于产生用于具有包括多个主IO和多个冗余IO的一组IO的存储器的修复解决方案的技术。例如，提供了用于选择存储器的输入/输出端口与存储器IO的子集之间的映射的技术。特别地，提供了用于配置多个多路复用器以通过建立IO子集与存储器输入/输出端口之间的电连接来实现所选映射的技术。 IO的子集可以包括多个冗余IO中的一个或多个，其有效地替换主IO中的一个或多个有缺陷的IO。可以通过生成一个或多个温度计代码来配置多个多路复用器，所述温度计代码编码任何缺陷主IO的标识，并且用作多个多路复用器的选择输入。

2. 发明授权

US07055074B2 Device to inhibit duplicate cache repairs 有权
公开(公告)号：US07055074B2
公开(公告)日：2006-05-30
申请号：US09842333
申请日：2001-04-25
申请人： Brian William Hughes , J. Michael Hill , Warren Kurt Howlett
发明人： Brian William Hughes , J. Michael Hill , Warren Kurt Howlett
IPC分类号： G11C29/00
CPC分类号： G11C29/72
摘要： The present invention is directed to a system and method which manages one or more errors in a plurality of elements. The invention tests an element of the plurality of elements and detects the error in one of the elements. The invention then repairs a group of N elements, wherein N is greater than one and the group of N elements includes the element with the error. The invention inhibits subsequent repairs of the group of N elements.

3. 发明授权

US06691252B2 Cache test sequence for single-ported row repair CAM 失效
标题翻译：单端口行修复CAM的缓存测试序列
公开(公告)号：US06691252B2
公开(公告)日：2004-02-10
申请号：US09792476
申请日：2001-02-23
申请人： Brian William Hughes , Warren Kurt Howlett
发明人： Brian William Hughes , Warren Kurt Howlett
IPC分类号： G06F1127
CPC分类号： G11C29/72 , G11C15/00 , G11C29/12
摘要： The present invention incorporates built-in self test and self repair functionality into a semiconductor memory device in which reconfiguration data used to replace faulty memory is stored at the same time testing to identify other faulty memory cells continues. To avoid access contention conflicts to a content addressable memory used to identify rows or groups of rows having faulty memory cells, the built in test function writes test data to each cell at least twice before reading the stored data. By writing twice before reading, contention problems caused by simultaneous updating of the content addressable memory are avoided. That is, even if the content addressable memory is initially unavailable to process address information used to access a memory cell to be tested, repetition of the write process ensure that the data will be properly stored when the memory again becomes available after being updated.
摘要翻译：本发明将内置的自检和自修复功能集成到半导体存储器件中，其中用于替换故障存储器的重新配置数据被同时存储在测试中以识别其他故障存储器单元继续。为了避免将访问冲突与用于识别具有故障存储单元的行或组的行的内容可寻址存储器进行访问冲突，内置测试功能在读取存储的数据之前至少将测试数据写入每个单元格至少两次。在阅读之前两次写入，避免了同时更新内容可寻址存储器引起的争用问题。也就是说，即使内容可寻址存储器最初不可用于处理用于访问待测试的存储器单元的地址信息，所以写入过程的重复确保当存储器在更新之后再次变得可用时，数据将被适当地存储。

4. 发明授权

US07328378B2 Repair techniques for memory with multiple redundancy 有权
标题翻译：具有多重冗余的内存修复技术
公开(公告)号：US07328378B2
公开(公告)日：2008-02-05
申请号：US11507272
申请日：2006-08-21
申请人： Warren Kurt Howlett
发明人： Warren Kurt Howlett
IPC分类号： G11C29/00
CPC分类号： G11C29/848
摘要： In one aspect, the present invention features techniques for generating a repair solution for a memory having a set of IOs including a plurality of main IOs and a plurality of redundant IOs. For example, techniques are provided for selecting a mapping between input/output ports of the memory and a subset of the memory's IOs. In particular, techniques are provided for configuring a plurality of multiplexors to implement the selected mapping by establishing electrical connections between the subset of IOs and the memory input/output ports. The subset of IOs may include one or more of the plurality of redundant IOs which effectively replace one or more defective ones of the main IOs. The plurality of multiplexors may be configured by generating one or more thermometer codes which encode the identities of any defective main IOs and which serve as selection inputs to the plurality of multiplexors.
摘要翻译：在一个方面，本发明的特征在于产生用于具有包括多个主IO和多个冗余IO的一组IO的存储器的修复解决方案的技术。例如，提供了用于选择存储器的输入/输出端口与存储器IO的子集之间的映射的技术。特别地，提供了用于配置多个多路复用器以通过建立IO子集与存储器输入/输出端口之间的电连接来实现所选映射的技术。 IO的子集可以包括多个冗余IO中的一个或多个，其有效地替换主IO中的一个或多个有缺陷的IO。可以通过生成一个或多个温度计代码来配置多个多路复用器，所述温度计代码编码任何缺陷主IO的标识，并且用作多个多路复用器的选择输入。

5. 发明授权

US07131039B2 Repair techniques for memory with multiple redundancy 失效
标题翻译：具有多重冗余的内存修复技术
公开(公告)号：US07131039B2
公开(公告)日：2006-10-31
申请号：US10316651
申请日：2002-12-11
申请人： Warren Kurt Howlett
发明人： Warren Kurt Howlett
IPC分类号： G11C29/00
CPC分类号： G11C29/848
摘要： In one aspect, the present invention features techniques for generating a repair solution for a memory having a set of IOs including a plurality of main IOs and a plurality of redundant IOs. For example, techniques are provided for selecting a mapping between input/output ports of the memory and a subset of the memory's IOs. In particular, techniques are provided for configuring a plurality of multiplexors to implement the selected mapping by establishing electrical connections between the subset of IOs and the memory input/output ports. The subset of IOs may include one or more of the plurality of redundant IOs which effectively replace one or more defective ones of the main IOs. The plurality of multiplexors may be configured by generating one or more thermometer codes which encode the identities of any defective main IOs and which serve as selection inputs to the plurality of multiplexors.
摘要翻译：在一个方面，本发明的特征在于产生用于具有包括多个主IO和多个冗余IO的一组IO的存储器的修复解决方案的技术。例如，提供了用于选择存储器的输入/输出端口与存储器IO的子集之间的映射的技术。特别地，提供了用于配置多个多路复用器以通过建立IO子集与存储器输入/输出端口之间的电连接来实现所选映射的技术。 IO的子集可以包括多个冗余IO中的一个或多个，其有效地替换主IO中的一个或多个有缺陷的IO。可以通过生成一个或多个温度计代码来配置多个多路复用器，所述温度计代码编码任何缺陷主IO的标识，并且用作多个多路复用器的选择输入。

6. 发明申请

US20080184096A1 Repair Techniques for Memory with Multiple Redundancy 失效
标题翻译：具有多重冗余的内存修复技术
公开(公告)号：US20080184096A1
公开(公告)日：2008-07-31
申请号：US12017091
申请日：2008-01-21
申请人： Warren Kurt Howlett
发明人： Warren Kurt Howlett
IPC分类号： G06F11/07
CPC分类号： G11C29/848
摘要： In one aspect, the present invention features techniques for generating a repair solution for a memory having a set of IOs including a plurality of main IOs and a plurality of redundant IOs. For example, techniques are provided for selecting a mapping between input/output ports of the memory and a subset of the memory's IOs. In particular, techniques are provided for configuring a plurality of multiplexors to implement the selected mapping by establishing electrical connections between the subset of IOs and the memory input/output ports. The subset of IOs may include one or more of the plurality of redundant IOs which effectively replace one or more defective ones of the main IOs. The plurality of multiplexors may be configured by generating one or more thermometer codes which encode the identities of any defective main IOs and which serve as selection inputs to the plurality of multiplexors.
摘要翻译：在一个方面，本发明的特征在于产生用于具有包括多个主IO和多个冗余IO的一组IO的存储器的修复解决方案的技术。例如，提供了用于选择存储器的输入/输出端口与存储器IO的子集之间的映射的技术。特别地，提供了用于配置多个多路复用器以通过建立IO子集与存储器输入/输出端口之间的电连接来实现所选映射的技术。 IO的子集可以包括多个冗余IO中的一个或多个，其有效地替换主IO中的一个或多个有缺陷的IO。可以通过生成一个或多个温度计代码来配置多个多路复用器，所述温度计代码编码任何缺陷主IO的标识，并且用作多个多路复用器的选择输入。

7. 发明授权

US06438017B1 Read/write eight-slot CAM with interleaving 失效
标题翻译：读/写八插槽CAM交错
公开(公告)号：US06438017B1
公开(公告)日：2002-08-20
申请号：US09756953
申请日：2001-01-09
申请人： Warren Kurt Howlett
发明人： Warren Kurt Howlett
IPC分类号： G11C1900
CPC分类号： G11C7/1036 , G11C7/1042 , G11C15/00 , G11C19/00
摘要： M parallel datastreams are interleaved into a serial bitstream and shifted into a staging register, so that bit zeros of all datastreams shift in first and bit (X-1)s last. All bits of the Mth datastream occupy uniformly spaced non-adjacent memory elements interconnected with a target memory device having M memory registers each of width X. The Mth memory register of the memory device is addressed, simultaneously writing all interconnected bits to the Mth memory register within a single clock period. The bitstream is then shifted by one memory element, such that bits of the (M-1)th parallel datastream occupy the interconnected memory elements, the register address decrements, and the interconnected bits are simultaneously written to the (M-1)th register. This process iterates until M registers are written within an elapsed time of M clock periods. Reading occurs essentially in a reverse sequence.
摘要翻译： M个并行数据流被交织到一个串行比特流中，并被移入一个分段寄存器，所以所有数据流的位零都在第一位和第（X-1）位移位。 Mth数据流的所有位占据与具有每个宽度为X的M个存储器寄存器的目标存储器件互连的均匀间隔的非相邻存储器元件。存储器件的第M个存储器寄存器被寻址，同时将所有互连的位写入第M个存储器寄存器在一个时钟周期内。然后将比特流移位一个存储器元件，使得（M-1）个并行数据流的位占据互连存储器元件，寄存器地址递减，并且互连位同时写入第（M-1）个寄存器。该过程重复直到在M个时钟周期的经过时间内写入M个寄存器。阅读基本上以相反的顺序发生。

8. 发明授权

US06691142B2 Pseudo random address generator for 0.75M cache 失效
标题翻译：用于0.75M缓存的伪随机地址生成器
公开(公告)号：US06691142B2
公开(公告)日：2004-02-10
申请号：US09756947
申请日：2001-01-09
申请人： Warren Kurt Howlett
发明人： Warren Kurt Howlett
IPC分类号： G06F102
CPC分类号： G06F7/584 , G06F2207/582 , G11C8/00 , G11C8/04
摘要： The most significant N bits of each number in a pseudo random sequence are generated by unidirectionally shifting the previous bits from a first memory cell toward the Nth memory cell of a sequential register and generating a new bit in the first memory cell in response to a predetermined combination of the previous N bits through feedback logic, for example by NORing the previous N most significant bits, such that always at least one of the N bits is a zero. N most significant bits are matched with a least significant bits portion that cycles exactly once for each most significant bit value. This results in a pseudo random sequence excluding an upper fraction of one-fourth, one-eighth, . . . , (one-half)N of an otherwise power of two range. Embodiments include right or left shifting, generating reversed sequences, or coupled right- and left-shifting, in hardware or software implementations.
摘要翻译：伪随机序列中每个数字的最高有效N位是通过将先前位从第一存储单元向顺序寄存器的第N个存储单元进行单向移位而生成的，并响应于预定的值而在第一存储单元中产生新位通过反馈逻辑组合前一个N位，例如通过NOR调用前N个最高有效位，使得总是至少一个N位为零。 N个最高有效位与最低有效位部分匹配，每个最高有效位值精确地循环一次。这导致了伪随机序列，不包括四分之一，八分之一的较高分数。。。，（二分之一）两个范围的另外的功率。实施例包括在硬件或软件实现中的右移或左移，产生反向序列或耦合右移和左移。

9. 发明授权

US06373758B1 System and method of operating a programmable column fail counter for redundancy allocation 失效
标题翻译：操作可编程列故障计数器的系统和方法用于冗余分配
公开(公告)号：US06373758B1
公开(公告)日：2002-04-16
申请号：US09792320
申请日：2001-02-23
申请人： Brian William Hughes , Warren Kurt Howlett
发明人： Brian William Hughes , Warren Kurt Howlett
IPC分类号： G11C2900
CPC分类号： G11C29/72 , G11C29/44
摘要： The present invention includes a system and a methodology for eliminating faulty memory cells in a memory array with replacement columns of memory cells and replacement rows of memory cells. The individual memory cells are checked to ensure that each is operational. Non-operational cells are replaced by first replacing columns which contain a threshold number of non-operational cells with spare columns and second removing any remaining non-operational cells by replacing the rows containing those non-operational cells with spare rows.
摘要翻译：本发明包括用于消除存储器阵列中的存储器阵列中的故障存储器单元的系统和方法，其中存储器单元的替换列和存储器单元的替换行。检查各个存储单元以确保每个存储单元都可操作。替换包含具有备用列的非操作单元的阈值数量的列替换非操作单元，并且通过用包含备用行的这些非操作单元替换行来删除任何剩余的非操作单元。

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