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1. 发明授权

US08223828B2 Methods and systems for adaptive receiver equalization 有权
标题翻译：自适应接收机均衡的方法和系统
公开(公告)号：US08223828B2
公开(公告)日：2012-07-17
申请号：US11976185
申请日：2007-10-22
申请人： Aaron Buchwald , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
发明人： Aaron Buchwald , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
IPC分类号： H03H7/30
CPC分类号： H04L25/03885 , H03L7/07 , H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/0274 , H04L7/0337 , H04L25/03006 , H04L2025/03477 , H04L2025/03617
摘要： Methods and systems for minimizing distortions in an analog data signal include equalizing the analog data signal at a receive end. In an embodiment, the invention adapts equalization parameters to a signal path associated with the analog data signal. Adaptive control logic is implemented with analog and/or digital components. In an embodiment, the invention equalizes a discrete-time analog representation of an analog data signal. In an embodiment, the invention digitally controls equalization parameters. In an embodiment, a resultant equalized analog data signal is digitized. In an example implementation, an analog data signal is sampled, a quality of the samples is measured, and one or more equalization parameters are adjusted with digital controls as needed to minimize distortion of the samples. The equalized samples are then digitized. The present invention is suitable for lower rate analog data signals and multi-gigabit data rate analog signals.
摘要翻译：用于最小化模拟数据信号中的失真的方法和系统包括在接收端均衡模拟数据信号。在一个实施例中，本发明使均衡参数适应于与模拟数据信号相关联的信号路径。自适应控制逻辑由模拟和/或数字组件实现。在一个实施例中，本发明使模拟数据信号的离散时间模拟表示相等。在一个实施例中，本发明数字地控制均衡参数。在一个实施例中，所得到的均衡的模拟数据信号被数字化。在示例实现中，对模拟数据信号进行采样，测量样本的质量，并且根据需要使用数字控制来调整一个或多个均衡参数以最小化样本的失真。然后将均衡的样品数字化。本发明适用于低速模拟数据信号和多吉比特数据速率模拟信号。

2. 发明申请

US20100033359A1 NONLINEAR COMPENSATION IN ANALOG TO DIGITAL CONVERTERS 有权
标题翻译：模拟数字转换器的非线性补偿
公开(公告)号：US20100033359A1
公开(公告)日：2010-02-11
申请号：US12341550
申请日：2008-12-22
申请人： Avanindra Madisetti , Thomas D. Kwon , Aaron W. Buchwald
发明人： Avanindra Madisetti , Thomas D. Kwon , Aaron W. Buchwald
IPC分类号： H03M1/12
CPC分类号： H03M1/1038 , H03M1/12
摘要： An apparatus for converting an analog signal to a digital signal comprising a first analog to digital converter for generating a first digital value from an analog value. A second analog to digital converter for generating a second digital value from the analog value. Logic for determining a correction factor for the second digital value based on a difference between the first digital value and the second digital value, wherein the logic updates the correction factor.
摘要翻译：一种用于将模拟信号转换为数字信号的装置，包括用于从模拟值产生第一数字值的第一模数转换器。第二模数转换器，用于从模拟值产生第二数字值。用于基于第一数字值和第二数字值之间的差确定第二数字值的校正因子的逻辑，其中逻辑更新校正因子。

3. 发明申请

US20070189376A1 ARCHITECTURE FOR VERY HIGH-SPEED DECISION FEEDBACK SEQUENCE ESTIMATION 有权
标题翻译：非常高速决策反馈序列估计的架构
公开(公告)号：US20070189376A1
公开(公告)日：2007-08-16
申请号：US11674530
申请日：2007-02-13
申请人： Arthur Abnous , Avanindra Madisetti , Christian Lutkemeyer
发明人： Arthur Abnous , Avanindra Madisetti , Christian Lutkemeyer
IPC分类号： H03H7/30 , H04B1/10
CPC分类号： H04L25/03267 , H04L25/03197 , H04L25/03235 , H04L25/497
摘要： A method for providing a next-cycle input sample from a decision feedback equalizer to a symbol decoder using look-ahead computations such that timing contention between the decision feedback equalizer and the symbol decoder is reduced. During a symbol period, a set of possible values is computed in the decision feedback equalizer and a set of path memory symbols is computed in the symbol decoder, the set of path memory symbols being based on a current input sample. During the same symbol period, one of the possible values is selected as the next-cycle input sample based on at least one of the next-cycle path memory symbols produced from the symbol decoder.
摘要翻译：一种用于使用先行计算从判决反馈均衡器向符号解码器提供下一周期输入样本的方法，从而降低了判决反馈均衡器和符号解码器之间的定时争用。在符号周期期间，在判决反馈均衡器中计算一组可能的值，并且在符号解码器中计算一组路径存储器符号，该路径存储器符号集合基于当前输入样本。在相同的符号周期期间，基于从符号解码器产生的下一循环路径存储器符号中的至少一个，可选值中的一个被选择为下一周期输入采样。

4. 发明授权

US06509773B2 Phase interpolator device and method 有权
公开(公告)号：US06509773B2
公开(公告)日：2003-01-21
申请号：US09844266
申请日：2001-04-30
申请人： Aaron W. Buchwald , Myles Wakayama , Michael Le , Jurgen Van Engelen , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
发明人： Aaron W. Buchwald , Myles Wakayama , Michael Le , Jurgen Van Engelen , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
IPC分类号： H03H1116
CPC分类号： H04L25/03885 , H03L7/07 , H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/0274 , H04L7/0337 , H04L25/03006 , H04L2025/03477 , H04L2025/03617
摘要： A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

5. 发明申请

US20090086805A1 APPARATUS FOR, AND METHOD OF, PROCESSING SIGNALS TRANSMITTED OVER A LOCAL AREA NETWORK 有权
标题翻译：本地区域网络传输信号的处理方法及方法
公开(公告)号：US20090086805A1
公开(公告)日：2009-04-02
申请号：US12017314
申请日：2008-01-21
申请人： Henry Samueli , Fang Lu , Avanindra Madisetti
发明人： Henry Samueli , Fang Lu , Avanindra Madisetti
IPC分类号： H03H7/30
CPC分类号： H04L7/0054 , H04L7/0004 , H04L7/0334 , H04L25/03057 , H04L25/03885 , H04L25/062 , H04L2025/03503
摘要： Systems for recovering communicated information in a communication system are disclosed and may include at least one digitizer for digitizing an analog received signal comprising the communicated information, thereby creating a digital received signal. The system may include at least one filter for bandwidth-limiting at least a portion of the digital received signal. At least one feed forward equalizer may be used for equalizing at least a portion of the bandwidth-limited signal to create an equalized signal. At least one converter for creating a data signal according to at least the equalized signal. At least one soft decision circuit for creating a soft decision signal according to the data signal. The soft decision circuit may cancel at least a portion of the equalized signal.
摘要翻译：公开了用于恢复通信系统中的通信信息的系统，并且可以包括用于数字化包括所传送的信息的模拟接收信号的至少一个数字化仪，从而产生数字接收信号。该系统可以包括用于对数字接收信号的至少一部分进行带宽限制的至少一个滤波器。可以使用至少一个前馈均衡器来均衡带宽限制信号的至少一部分以产生均衡的信号。至少一个转换器，用于根据至少所述均衡信号产生数据信号。用于根据数据信号产生软判决信号的至少一个软判决电路。软判决电路可以消除均衡信号的至少一部分。

6. 发明授权

US07286597B2 Methods and systems for adaptive receiver equalization 失效
标题翻译：自适应接收机均衡的方法和系统
公开(公告)号：US07286597B2
公开(公告)日：2007-10-23
申请号：US09844283
申请日：2001-04-30
申请人： Aaron Buchwald , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
发明人： Aaron Buchwald , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
IPC分类号： H03H7/30
CPC分类号： H04L25/03885 , H03L7/07 , H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/0274 , H04L7/0337 , H04L25/03006 , H04L2025/03477 , H04L2025/03617
摘要： Methods and systems for minimizing distortions in an analog data signal include equalizing the analog data signal at a receive end. In an embodiment, the invention adapts equalization parameters to a signal path associated with the analog data signal. Adaptive control logic is implemented with analog and/or digital components. In an embodiment, the invention equalizes a discreet-time analog representation of an analog data signal. In an embodiment, the invention digitally controls equalization parameters. In an embodiment, a resultant equalized analog data signal is digitized. In an example implementation, an analog data signal is sampled, a quality of the samples is measured, and one or more equalization parameters are adjusted with digital controls as needed to minimize distortion of the samples. The equalized samples are then digitized. The present invention is suitable for lower rate analog data signals and multi-gigabit data rate analog signals.
摘要翻译：用于最小化模拟数据信号中的失真的方法和系统包括在接收端均衡模拟数据信号。在一个实施例中，本发明使均衡参数适应于与模拟数据信号相关联的信号路径。自适应控制逻辑由模拟和/或数字组件实现。在一个实施例中，本发明均衡模拟数据信号的谨慎时间模拟表示。在一个实施例中，本发明数字地控制均衡参数。在一个实施例中，所得到的均衡的模拟数据信号被数字化。在示例实现中，对模拟数据信号进行采样，测量样本的质量，并且根据需要使用数字控制来调整一个或多个均衡参数以最小化样本的失真。然后将均衡的样品数字化。本发明适用于低速模拟数据信号和多吉比特数据速率模拟信号。

7. 发明授权

US07058150B2 High-speed serial data transceiver and related methods 有权
公开(公告)号：US07058150B2
公开(公告)日：2006-06-06
申请号：US09844441
申请日：2001-04-30
申请人： Aaron W. Buchwald , Michael Le , Jurgen Van Engelen , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
发明人： Aaron W. Buchwald , Michael Le , Jurgen Van Engelen , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
IPC分类号： H04L7/00
CPC分类号： H04L25/03885 , H03L7/07 , H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/0274 , H04L7/0337 , H04L25/03006 , H04L2025/03477 , H04L2025/03617
摘要： A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

8. 发明授权

US07012983B2 Timing recovery and phase tracking system and method 失效
公开(公告)号：US07012983B2
公开(公告)日：2006-03-14
申请号：US09844296
申请日：2001-04-30
申请人： Aaron W. Buchwald , Myles Wakayama , Michael Le , Jurgen Van Engelen , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
发明人： Aaron W. Buchwald , Myles Wakayama , Michael Le , Jurgen Van Engelen , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
IPC分类号： H03D3/34 , H04L7/00
CPC分类号： H04L25/03885 , H03L7/07 , H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/0274 , H04L7/0337 , H04L25/03006 , H04L2025/03477 , H04L2025/03617
摘要： A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

9. 发明授权

US06459730B1 Apparatus for, and method of, processing signals transmitted over a local area network 有权
标题翻译：用于处理通过局域网传输的信号的装置和方法
公开(公告)号：US06459730B1
公开(公告)日：2002-10-01
申请号：US09482699
申请日：2000-01-13
申请人： Henry Samueli , Fang Lu , Avanindra Madisetti
发明人： Henry Samueli , Fang Lu , Avanindra Madisetti
IPC分类号： H04L2701
CPC分类号： H04L7/0054 , H04L7/0004 , H04L7/0334 , H04L25/03057 , H04L25/03885 , H04L25/062 , H04L2025/03503
摘要： Digital signals provided by a repeater connected to a plurality of clients by unshielded twisted wire pairs, are converted to analog signals which become degraded during transmission through the wires. Clients convert the degraded analog signals to digital signals. Digital signal phases are coarsely adjusted to have assumed zero crossing times coincide in-time with a clock signal zero crossing. Signal polarity, and the polarity of any change, is determined at the assumed zero crossing times of the digital signals. Pre-cursor and post-cursor responses, resulting from signal degradation, are respectively inhibited by a feed forward and a decision feedback equalizer. The time duration of post-cursor response is further inhibited by a high pass filter and a tail canceller. Phase adjustments are made, after response inhibition, by determining the polarity, and the polarity of any change, at the assumed zero crossing times. Before phase adjustments are made, a phase offset is provided in order to compensate for phase degradations introduced by the unshielded twisted wire pairs.
摘要翻译：由通过非屏蔽双绞线连接到多个客户端的中继器提供的数字信号被转换为在通过电线传输期间降级的模拟信号。客户端将降级的模拟信号转换为数字信号。数字信号相位粗略地调整为假定零交叉时间与时钟信号过零时间一致。信号极性和任何变化的极性在假定的数字信号的零交叉时间确定。分别由前馈和判决反馈均衡器阻止由信号劣化引起的前标和后视标响应。后置光标响应的持续时间被高通滤波器和尾部消除器进一步抑制。通过在假设的零交叉时间确定极性和任何变化的极性，在响应抑制之后进行相位调整。在进行相位调整之前，提供相位偏移以补偿由未屏蔽的双绞线引入的相位劣化。

10. 发明授权

US08934527B2 Architecture for very high-speed decision feedback sequence estimation 有权
公开(公告)号：US08934527B2
公开(公告)日：2015-01-13
申请号：US12816071
申请日：2010-06-15
申请人： Arthur Abnous , Avanindra Madisetti , Christian A. J. Lutkemeyer
发明人： Arthur Abnous , Avanindra Madisetti , Christian A. J. Lutkemeyer
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159 , H04L25/03 , H04L25/497
CPC分类号： H04L25/03267 , H04L25/03197 , H04L25/03235 , H04L25/497
摘要： A method for providing a next-cycle input sample from a decision feedback equalizer to a symbol decoder using look-ahead computations such that timing contention between the decision feedback equalizer and the symbol decoder is reduced. During a symbol period, a set of possible values is computed in the decision feedback equalizer and a set of path memory symbols is computed in the symbol decoder, the set of path memory symbols being based on a current input sample. During the same symbol period, one of the possible values is selected as the next-cycle input sample based on at least one of the next-cycle path memory symbols produced from the symbol decoder.

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