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1. 发明授权

US08557621B2 Method for manufacturing thin film transistor array panel 有权
标题翻译：制造薄膜晶体管阵列面板的方法
公开(公告)号：US08557621B2
公开(公告)日：2013-10-15
申请号：US13157806
申请日：2011-06-10
申请人： Jong-Hyun Choung , Yang Ho Bae , Jean Ho Song , O Sung Seo , Sun-Young Hong , Hwa Yeul Oh , Bong-Kyun Kim , Nam Seok Suh , Dong-Ju Yang , Wang Woo Lee
发明人： Jong-Hyun Choung , Yang Ho Bae , Jean Ho Song , O Sung Seo , Sun-Young Hong , Hwa Yeul Oh , Bong-Kyun Kim , Nam Seok Suh , Dong-Ju Yang , Wang Woo Lee
IPC分类号： H01L21/00
CPC分类号： H01L21/32134 , G02F1/136227 , H01L27/1288 , H01L29/41733
摘要： A method for manufacturing a thin film transistor array panel, including: sequentially forming a first silicon layer, a second silicon layer, a lower metal layer, and an upper metal layer on a gate insulating layer and a gate line; forming a first film pattern on the upper metal layer; forming a first lower metal pattern and a first upper metal pattern that includes a protrusion, by etching the upper metal layer and the lower metal layer; forming first and second silicon patterns by etching the first and second silicon layers; forming a second film pattern by ashing the first film pattern; forming a second upper metal pattern by etching the first upper metal pattern; forming a data line and a thin film transistor by etching the first lower metal pattern and the first and second silicon patterns; and forming a passivation layer and a pixel electrode on the resultant.
摘要翻译：一种制造薄膜晶体管阵列面板的方法，包括：在栅绝缘层和栅极线上依次形成第一硅层，第二硅层，下金属层和上金属层; 在上金属层上形成第一膜图案; 通过蚀刻上金属层和下金属层，形成第一下金属图案和包括突起的第一上金属图案; 通过蚀刻第一和第二硅层形成第一和第二硅图案; 通过灰化第一膜图案形成第二膜图案; 通过蚀刻第一上金属图案形成第二上金属图案; 通过蚀刻第一下金属图案和第一和第二硅图案来形成数据线和薄膜晶体管; 并在所得物上形成钝化层和像素电极。

2. 发明授权

US08372701B2 Thin film transistor array panel including layered line structure and method for manufacturing the same 有权
公开(公告)号：US08372701B2
公开(公告)日：2013-02-12
申请号：US12576217
申请日：2009-10-08
申请人： Je-Hun Lee , Yang-Ho Bae , Beom-Seok Cho , Chang-Oh Jeong
发明人： Je-Hun Lee , Yang-Ho Bae , Beom-Seok Cho , Chang-Oh Jeong
IPC分类号： H01L21/00
CPC分类号： H01L27/1214 , H01L27/1225 , H01L27/124
摘要： The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).

3. 发明授权

US08058114B2 Method of manufacturing the array substrate capable of decreasing a line resistance 有权
标题翻译：能够降低线电阻的阵列基板的制造方法
公开(公告)号：US08058114B2
公开(公告)日：2011-11-15
申请号：US12797527
申请日：2010-06-09
申请人： Jang-Soo Kim , Hong-Long Ning , Bong-Kyun Kim , Hong-Sick Park , Shi-Yul Kim , Chang-Oh Jeong , Sang-Gab Kim , Jae-Hyoung Youn , Woo-Geun Lee , Yang-Ho Bae , Pil-Sang Yun , Jong-Hyun Choung , Sun-Young Hong , Ki-Won Kim , Byeong-Jin Lee , Young-Wook Lee , Jong-In Kim , Byeong-Beom Kim , Nam-Seok Suh
发明人： Jang-Soo Kim , Hong-Long Ning , Bong-Kyun Kim , Hong-Sick Park , Shi-Yul Kim , Chang-Oh Jeong , Sang-Gab Kim , Jae-Hyoung Youn , Woo-Geun Lee , Yang-Ho Bae , Pil-Sang Yun , Jong-Hyun Choung , Sun-Young Hong , Ki-Won Kim , Byeong-Jin Lee , Young-Wook Lee , Jong-In Kim , Byeong-Beom Kim , Nam-Seok Suh
IPC分类号： H01L21/84 , H01L21/336
CPC分类号： G02F1/13458 , G02F1/136286 , G02F2001/136295 , H01L27/1218 , H01L27/124 , H01L27/1288
摘要： A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.
摘要翻译：栅极线包括形成在基底基板上的第一籽晶层和形成在第一籽晶层上的第一金属层。在基底基板上形成第一绝缘层。在基底基板上形成第二绝缘层。这里，在与栅极线交叉的方向上通过第二绝缘层形成线沟槽。数据线包括形成在线沟槽下方的第二晶种层和形成在线沟槽中的第二金属层。像素电极形成在基底基板的像素区域中。因此，使用绝缘层形成预定深度的沟槽，并且通过电镀方法形成金属层，从而可以形成具有足够厚度的金属线。

4. 发明授权

US07851920B2 Wire structure, method for fabricating wire, thin film transistor substrate, and method for fabricating thin film transistor substrate 有权
标题翻译：线结构，制造线的方法，薄膜晶体管衬底以及制造薄膜晶体管衬底的方法
公开(公告)号：US07851920B2
公开(公告)日：2010-12-14
申请号：US11486720
申请日：2006-07-15
申请人： Je-hun Lee , Chang-oh Jeong , Beom-seok Cho , Yang-ho Bae
发明人： Je-hun Lee , Chang-oh Jeong , Beom-seok Cho , Yang-ho Bae
IPC分类号： H01L23/48
CPC分类号： H01L27/124 , G02F2001/13629 , G02F2001/136295 , H01L23/53238 , H01L27/12 , H01L29/41733 , H01L29/458 , H01L29/4908 , H01L2924/0002 , H01L2924/12044 , H01L2924/3011 , Y10T29/49117 , H01L2924/00
摘要： Provided are a wire structure, a method for fabricating a wire, a thin film transistor (TFT) substrate, and a method for fabricating a TFT substrate. The wire structure includes a barrier layer formed on a substrate and including copper nitride and a copper conductive layer formed on the barrier layer and including copper or a copper alloy.
摘要翻译：提供一种线结构，制造线的方法，薄膜晶体管（TFT）基板以及制造TFT基板的方法。导线结构包括在基板上形成的阻挡层，其包括形成在阻挡层上并包括铜或铜合金的氮化铜和铜导电层。

5. 发明申请

US20100261322A1 ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：阵列基板及其制造方法
公开(公告)号：US20100261322A1
公开(公告)日：2010-10-14
申请号：US12797527
申请日：2010-06-09
申请人： Jang-Soo Kim , Hong-Long Ning , Bong-Kyun Kim , Hong-Sick Park , Shi-Yul Kim , Chang-Oh Jeong , Sang-Gab Kim , Jae-Hyoung Youn , Woo-Geun Lee , Yang-Ho Bae , Pil-Sang Yun , Jong-Hyun Choung , Sun-Young Hong , Ki-Won Kim , Byeong-Jin Lee , Young-Wook Lee , Jong-In Kim , Byeong-Beom Kim , Nam-Seok Suh
发明人： Jang-Soo Kim , Hong-Long Ning , Bong-Kyun Kim , Hong-Sick Park , Shi-Yul Kim , Chang-Oh Jeong , Sang-Gab Kim , Jae-Hyoung Youn , Woo-Geun Lee , Yang-Ho Bae , Pil-Sang Yun , Jong-Hyun Choung , Sun-Young Hong , Ki-Won Kim , Byeong-Jin Lee , Young-Wook Lee , Jong-In Kim , Byeong-Beom Kim , Nam-Seok Suh
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： G02F1/13458 , G02F1/136286 , G02F2001/136295 , H01L27/1218 , H01L27/124 , H01L27/1288
摘要： A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.
摘要翻译：栅极线包括形成在基底基板上的第一籽晶层和形成在第一籽晶层上的第一金属层。在基底基板上形成第一绝缘层。在基底基板上形成第二绝缘层。这里，在与栅极线交叉的方向上通过第二绝缘层形成线沟槽。数据线包括形成在线沟槽下方的第二晶种层和形成在线沟槽中的第二金属层。像素电极形成在基底基板的像素区域中。因此，使用绝缘层形成预定深度的沟槽，并且通过电镀方法形成金属层，从而可以形成具有足够厚度的金属线。

6. 发明授权

US07808108B2 Thin film conductor and method of fabrication 有权
标题翻译：薄膜导体和制造方法
公开(公告)号：US07808108B2
公开(公告)日：2010-10-05
申请号：US11502918
申请日：2006-08-11
申请人： Beom-seok Cho , Je-hun Lee , Chang-oh Jeong , Yang-ho Bae
发明人： Beom-seok Cho , Je-hun Lee , Chang-oh Jeong , Yang-ho Bae
IPC分类号： H01L29/43
CPC分类号： H01L27/12 , H01L27/124
摘要： A thin film conductor having improved adhesion and superior conductivity, a method for fabricating the same, a thin film transistor (TFT) plate including the thin film conductor, and a method for fabricating the TFT plate are provided. The thin film conductor includes an adhesive layer containing an oxidation-reactive metal or silicidation-reactive metal and silver, a silver conductive layer formed on the adhesive layer, and a protection layer formed on the silver conductive layer and containing an oxidation-reactive metal and silver.
摘要翻译：提供了具有改善的粘附性和优异导电性的薄膜导体，其制造方法，包括薄膜导体的薄膜晶体管（TFT）板以及制造TFT板的方法。薄膜导体包括含有氧化反应性金属或硅化反应性金属和银的粘合剂层，形成在粘合剂层上的银导电层，以及形成在银导电层上并含有氧化反应性金属的保护层，银。

7. 发明申请

US20090212290A1 DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：显示面板及其制造方法
公开(公告)号：US20090212290A1
公开(公告)日：2009-08-27
申请号：US12354115
申请日：2009-01-15
申请人： Joo-Ae YOUN , Yang-Ho BAE , Chang-Oh JEONG , Chong-Chul CHAI , Pil-Sang YUN , Honglong NING , Byeong-Beom KIM
发明人： Joo-Ae YOUN , Yang-Ho BAE , Chang-Oh JEONG , Chong-Chul CHAI , Pil-Sang YUN , Honglong NING , Byeong-Beom KIM
IPC分类号： H01L27/088 , H01L21/77
CPC分类号： H01L33/0041 , H01L27/124 , H01L29/458
摘要： A display panel includes; a lower gate line, a lower data line disposed substantially perpendicular to the lower gate line, a thin film transistor (“TFT”) connected to the lower gate line and the lower data line, an insulating layer disposed on the lower gate line, the lower data line, and the TFT and having a plurality of trenches exposing the lower gate line and the lower data line, an upper gate line disposed in the trench on the lower gate line, an upper data line disposed in the trench on the lower data line, and a pixel electrode connected to the TFT.
摘要翻译：显示面板包括：下栅极线，基本上垂直于下栅极线设置的下数据线，连接到下栅极线和下数据线的薄膜晶体管（“TFT”），设置在下栅极线上的绝缘层，下数据线和TFT，并且具有暴露下栅极线和下数据线的多个沟槽，设置在下栅极线上的沟槽中的上栅极线，设置在下数据上的沟槽中的上数据线线和与TFT连接的像素电极。

8. 发明申请

US20080213702A1 METHOD FOR PATTERNING CONDUCTIVE POLYMER 审中-公开
标题翻译：用于形成导电聚合物的方法
公开(公告)号：US20080213702A1
公开(公告)日：2008-09-04
申请号：US11932496
申请日：2007-10-31
申请人： Yang-Ho BAE , Chang-Oh JEONG , Byeong-Beom KIM , Jae-Gab LEE , Tae-Wook KWON
发明人： Yang-Ho BAE , Chang-Oh JEONG , Byeong-Beom KIM , Jae-Gab LEE , Tae-Wook KWON
IPC分类号： G03F7/00
CPC分类号： H01L51/0021 , G03F7/0755 , G03F7/165 , H01L51/0023
摘要： A method for patterning a conductive polymer that adheres well to an oxide layer is presented. The method includes forming a self-assembled monolayer on a substrate, patterning the self-assembled monolayer, forming a catalyst layer on the self-assembled monolayer, and forming a conductive polymer layer on the self-assembled monolayer.
摘要翻译：提出了一种用于图案化粘附到氧化物层的导电聚合物的方法。该方法包括在衬底上形成自组装单层，图案化自组装单层，在自组装单层上形成催化剂层，并在自组装单层上形成导电聚合物层。

9. 发明申请

US20080191213A1 THIN FILM TRANSISTOR, THIN FILM TRANSISTOR SUBSTRATE INCLUDING THE SAME AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：薄膜晶体管，包括其的薄膜晶体管基板及其制造方法
公开(公告)号：US20080191213A1
公开(公告)日：2008-08-14
申请号：US11932314
申请日：2007-10-31
申请人： Yang Ho Bae , Chang Oh Jeong , Byeong Beom Kim
发明人： Yang Ho Bae , Chang Oh Jeong , Byeong Beom Kim
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/458 , H01L27/124
摘要： A thin film transistor showing desirable contact characteristics during contact with indium tin oxide (ITO) or indium zinc oxide (IZO), in which a first conductive pattern including a gate electrode and a second conductive pattern including a source electrode and a drain electrode are formed without an etching process, a TFT substrate including the TFTs, and a method of manufacturing the same. The thin film transistor includes a gate electrode formed of a first conductive layer, a gate insulating layer covering the gate electrode, a semiconductor layer forming a channel on the gate insulating layer; an ohmic contact layer formed on the semiconductor layer, and a source electrode and a drain electrode formed of a second conductive layer and of a third conductive layer. The second conductive layer includes an aluminum-nickel alloy and nitrogen and is formed on the semiconductor layer. The third conductive layer includes an aluminum-nickel alloy and is formed on the second conductive layer.
摘要翻译：在与铟锡氧化物（ITO）或铟锌氧化物（IZO）接触期间显示出期望的接触特性的薄膜晶体管，其中形成包括栅电极的第一导电图案和包括源电极和漏电极的第二导电图案没有蚀刻处理，包括TFT的TFT基板及其制造方法。薄膜晶体管包括由第一导电层形成的栅电极，覆盖栅电极的栅极绝缘层，在栅极绝缘层上形成沟道的半导体层; 形成在半导体层上的欧姆接触层，以及由第二导电层和第三导电层形成的源电极和漏电极。第二导电层包括铝 - 镍合金和氮，并形成在半导体层上。第三导电层包括铝镍合金，并形成在第二导电层上。

10. 发明授权

US07352004B2 Thin film transistor array panel and method for manufacturing the same 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07352004B2
公开(公告)日：2008-04-01
申请号：US11249500
申请日：2005-10-14
申请人： Je-Hun Lee , Yang-Ho Bae , Beom-Seok Cho , Chang-Oh Jeong
发明人： Je-Hun Lee , Yang-Ho Bae , Beom-Seok Cho , Chang-Oh Jeong
IPC分类号： H01L29/04 , H01L29/10 , H01L31/00
CPC分类号： H01L27/3279 , H01L27/124 , H01L27/1288 , H01L51/0023 , H01L51/56
摘要： The invention provides a thin film transistor (TFT) array panel that includes an insulating substrate; a gate line formed on the insulating substrate and having a first layer of an Al containing metal, a second layer of a Cu containing metal that is thicker than the first layer, and a gate electrode; a gate insulating layer arranged on the gate line; a semiconductor arranged on the gate insulating layer; a data line having a source electrode and arranged on the gate insulating layer and the semiconductor; a drain electrode arranged on the gate insulating layer and the semiconductor and facing the source electrode; a passivation layer having a contact hole and arranged on the data line and the drain electrode; and a pixel electrode arranged on the passivation layer and coupled with the drain electrode through the contact hole.
摘要翻译：本发明提供一种薄膜晶体管（TFT）阵列面板，其包括绝缘基板; 形成在所述绝缘基板上并具有含有Al的金属的第一层，比所述第一层更厚的含Cu金属的第二层的栅极线和栅电极; 栅极绝缘层，布置在栅极线上; 布置在栅绝缘层上的半导体; 数据线，其具有源电极并且布置在所述栅极绝缘层和所述半导体上; 布置在所述栅绝缘层和所述半导体上并面对所述源电极的漏电极; 钝化层，其具有接触孔并且布置在所述数据线和所述漏电极上; 以及设置在钝化层上并通过接触孔与漏电极耦合的像素电极。

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