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1. 发明授权

US08994023B2 Thin film transistor array substrate and method of fabricating the same 有权
标题翻译：薄膜晶体管阵列基板及其制造方法
公开(公告)号：US08994023B2
公开(公告)日：2015-03-31
申请号：US13115088
申请日：2011-05-24
申请人： Hye-Young Ryu , Woo-Geun Lee , Young-Joo Choi , Kyoung-Jae Chung , Jin-Won Lee , Seung-Ha Choi , Hee-Jun Byeon , Pil-Sang Yun
发明人： Hye-Young Ryu , Woo-Geun Lee , Young-Joo Choi , Kyoung-Jae Chung , Jin-Won Lee , Seung-Ha Choi , Hee-Jun Byeon , Pil-Sang Yun
IPC分类号： H01L47/00 , H01L29/10 , H01L29/04 , H01L29/15 , H01L27/12
CPC分类号： H01L27/1214 , H01L27/1225 , H01L27/1255
摘要： A thin film transistor array substrate capable of reducing degradation of a device due to degradation of an oxide semiconductor pattern and a method of fabricating the same are provided. The thin film transistor array substrate may include an insulating substrate on which a gate electrode is formed, a gate insulating film formed on the insulating substrate, an oxide semiconductor pattern disposed on the gate insulating film, an anti-etching pattern formed on the oxide semiconductor pattern, and a source electrode and a drain electrode formed on the anti-etching pattern. The oxide semiconductor pattern may include an edge portion positioned between the source electrode and the drain electrode, and the edge portion may include at least one conductive region and at least one non-conductive region.
摘要翻译：提供了能够降低由于氧化物半导体图案的劣化引起的器件劣化的薄膜晶体管阵列基板及其制造方法。薄膜晶体管阵列基板可以包括其上形成有栅极的绝缘基板，形成在绝缘基板上的栅极绝缘膜，设置在栅极绝缘膜上的氧化物半导体图案，形成在氧化物半导体上的抗蚀刻图案图案，以及形成在防蚀刻图案上的源电极和漏电极。氧化物半导体图案可以包括位于源电极和漏电极之间的边缘部分，并且边缘部分可以包括至少一个导电区域和至少一个非导电区域。

2. 发明授权

US08501551B2 Thin film transistor array substrate and method of fabricating the same 有权
标题翻译：薄膜晶体管阵列基板及其制造方法
公开(公告)号：US08501551B2
公开(公告)日：2013-08-06
申请号：US13608981
申请日：2012-09-10
申请人： Do-Hyun Kim , Je-Hun Lee , Pil-Sang Yun , Dong-Hoon Lee , Bong-Kyun Kim
发明人： Do-Hyun Kim , Je-Hun Lee , Pil-Sang Yun , Dong-Hoon Lee , Bong-Kyun Kim
IPC分类号： H01L21/00
CPC分类号： H01L27/1225 , H01L29/7869
摘要： A thin film transistor array substrate having a high charge mobility and that can raise a threshold voltage, and a method of fabricating the thin film transistor array substrate are provided. The thin film transistor array substrate includes: an insulating substrate; a gate electrode formed on the insulating substrate; an oxide semiconductor layer comprising a lower oxide layer formed on the gate electrode and an upper oxide layer formed on the lower oxide layer, such that the oxygen concentration of the upper oxide layer is higher than the oxygen concentration of the lower oxide layer; and a source electrode and a drain electrode formed on the oxide semiconductor layer and separated from each other.
摘要翻译：提供具有高电荷迁移率并且可以提高阈值电压的薄膜晶体管阵列基板，以及制造薄膜晶体管阵列基板的方法。薄膜晶体管阵列基板包括：绝缘基板; 形成在所述绝缘基板上的栅电极; 氧化物半导体层，其包括形成在所述栅电极上的低氧化物层和形成在所述低氧化物层上的上氧化物层，使得所述上氧化物层的氧浓度高于所述低氧化物层的氧浓度; 以及形成在氧化物半导体层上并且彼此分离的源电极和漏电极。

3. 发明授权

US08476627B2 Thin-film transistor, method of fabricating the thin-film transistor, and display substrate using the thin-film transistor 有权
标题翻译：薄膜晶体管，制造薄膜晶体管的方法以及使用该薄膜晶体管的显示基板
公开(公告)号：US08476627B2
公开(公告)日：2013-07-02
申请号：US13046130
申请日：2011-03-11
申请人： Pil-Sang Yun , Young-Wook Lee , Woo-Geun Lee
发明人： Pil-Sang Yun , Young-Wook Lee , Woo-Geun Lee
IPC分类号： H01L29/786
CPC分类号： H01L21/467 , H01L27/1214 , H01L27/1225 , H01L27/124 , H01L29/41733 , H01L29/7869
摘要： Provided is an oxide thin-film transistor (TFT) substrate that may enhance the display quality of a display device and a method of fabricating the same via a simple process. The oxide TFT substrate includes: a substrate, a gate line, a data line, an oxide TFT, and a pixel electrode. An oxide layer of the oxide TFT includes a first region that has semiconductor characteristics and a channel, and a second region that is conductive and surrounds the first region. A portion of the first region is electrically connected to the pixel electrode, and the second region is electrically connected to the data line.
摘要翻译：提供了可以通过简单的处理来提高显示装置的显示质量的氧化物薄膜晶体管（TFT）基板及其制造方法。氧化物TFT基板包括：基板，栅极线，数据线，氧化物TFT和像素电极。氧化物TFT的氧化物层包括具有半导体特性的第一区域和沟道，以及导电并围绕第一区域的第二区域。第一区域的一部分电连接到像素电极，并且第二区域电连接到数据线。

4. 发明授权

US08283666B2 Thin film transistor array substrate and method of fabricating the same 有权
标题翻译：薄膜晶体管阵列基板及其制造方法
公开(公告)号：US08283666B2
公开(公告)日：2012-10-09
申请号：US12500506
申请日：2009-07-09
申请人： Do-Hyun Kim , Je-Hun Lee , Pil-Sang Yun , Dong-Hoon Lee , Bong-Kyun Kim
发明人： Do-Hyun Kim , Je-Hun Lee , Pil-Sang Yun , Dong-Hoon Lee , Bong-Kyun Kim
IPC分类号： H01L29/04
CPC分类号： H01L27/1225 , H01L29/7869
摘要： A thin film transistor array substrate having a high charge mobility and that can raise a threshold voltage, and a method of fabricating the thin film transistor array substrate are provided. The thin film transistor array substrate includes: an insulating substrate; a gate electrode formed on the insulating substrate; an oxide semiconductor layer comprising a lower oxide layer formed on the gate electrode and an upper oxide layer formed on the lower oxide layer, such that the oxygen concentration of the upper oxide layer is higher than the oxygen concentration of the lower oxide layer; and a source electrode and a drain electrode formed on the oxide semiconductor layer and separated from each other.
摘要翻译：提供具有高电荷迁移率并且可以提高阈值电压的薄膜晶体管阵列基板，以及制造薄膜晶体管阵列基板的方法。薄膜晶体管阵列基板包括：绝缘基板; 形成在所述绝缘基板上的栅电极; 氧化物半导体层，其包括形成在所述栅电极上的低氧化物层和形成在所述低氧化物层上的上氧化物层，使得所述上氧化物层的氧浓度高于所述低氧化物层的氧浓度; 以及形成在氧化物半导体层上并且彼此分离的源电极和漏电极。

5. 发明授权

US08058114B2 Method of manufacturing the array substrate capable of decreasing a line resistance 有权
标题翻译：能够降低线电阻的阵列基板的制造方法
公开(公告)号：US08058114B2
公开(公告)日：2011-11-15
申请号：US12797527
申请日：2010-06-09
申请人： Jang-Soo Kim , Hong-Long Ning , Bong-Kyun Kim , Hong-Sick Park , Shi-Yul Kim , Chang-Oh Jeong , Sang-Gab Kim , Jae-Hyoung Youn , Woo-Geun Lee , Yang-Ho Bae , Pil-Sang Yun , Jong-Hyun Choung , Sun-Young Hong , Ki-Won Kim , Byeong-Jin Lee , Young-Wook Lee , Jong-In Kim , Byeong-Beom Kim , Nam-Seok Suh
发明人： Jang-Soo Kim , Hong-Long Ning , Bong-Kyun Kim , Hong-Sick Park , Shi-Yul Kim , Chang-Oh Jeong , Sang-Gab Kim , Jae-Hyoung Youn , Woo-Geun Lee , Yang-Ho Bae , Pil-Sang Yun , Jong-Hyun Choung , Sun-Young Hong , Ki-Won Kim , Byeong-Jin Lee , Young-Wook Lee , Jong-In Kim , Byeong-Beom Kim , Nam-Seok Suh
IPC分类号： H01L21/84 , H01L21/336
CPC分类号： G02F1/13458 , G02F1/136286 , G02F2001/136295 , H01L27/1218 , H01L27/124 , H01L27/1288
摘要： A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.
摘要翻译：栅极线包括形成在基底基板上的第一籽晶层和形成在第一籽晶层上的第一金属层。在基底基板上形成第一绝缘层。在基底基板上形成第二绝缘层。这里，在与栅极线交叉的方向上通过第二绝缘层形成线沟槽。数据线包括形成在线沟槽下方的第二晶种层和形成在线沟槽中的第二金属层。像素电极形成在基底基板的像素区域中。因此，使用绝缘层形成预定深度的沟槽，并且通过电镀方法形成金属层，从而可以形成具有足够厚度的金属线。

6. 发明申请

US20100261322A1 ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：阵列基板及其制造方法
公开(公告)号：US20100261322A1
公开(公告)日：2010-10-14
申请号：US12797527
申请日：2010-06-09
申请人： Jang-Soo Kim , Hong-Long Ning , Bong-Kyun Kim , Hong-Sick Park , Shi-Yul Kim , Chang-Oh Jeong , Sang-Gab Kim , Jae-Hyoung Youn , Woo-Geun Lee , Yang-Ho Bae , Pil-Sang Yun , Jong-Hyun Choung , Sun-Young Hong , Ki-Won Kim , Byeong-Jin Lee , Young-Wook Lee , Jong-In Kim , Byeong-Beom Kim , Nam-Seok Suh
发明人： Jang-Soo Kim , Hong-Long Ning , Bong-Kyun Kim , Hong-Sick Park , Shi-Yul Kim , Chang-Oh Jeong , Sang-Gab Kim , Jae-Hyoung Youn , Woo-Geun Lee , Yang-Ho Bae , Pil-Sang Yun , Jong-Hyun Choung , Sun-Young Hong , Ki-Won Kim , Byeong-Jin Lee , Young-Wook Lee , Jong-In Kim , Byeong-Beom Kim , Nam-Seok Suh
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： G02F1/13458 , G02F1/136286 , G02F2001/136295 , H01L27/1218 , H01L27/124 , H01L27/1288
摘要： A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.
摘要翻译：栅极线包括形成在基底基板上的第一籽晶层和形成在第一籽晶层上的第一金属层。在基底基板上形成第一绝缘层。在基底基板上形成第二绝缘层。这里，在与栅极线交叉的方向上通过第二绝缘层形成线沟槽。数据线包括形成在线沟槽下方的第二晶种层和形成在线沟槽中的第二金属层。像素电极形成在基底基板的像素区域中。因此，使用绝缘层形成预定深度的沟槽，并且通过电镀方法形成金属层，从而可以形成具有足够厚度的金属线。

7. 发明申请

US20100123842A1 LIQUID CRYSTAL DISPLAY AND DRIVING METHOD THEREOF 有权
标题翻译：液晶显示及其驱动方法
公开(公告)号：US20100123842A1
公开(公告)日：2010-05-20
申请号：US12421618
申请日：2009-04-09
申请人： Young-Wook LEE , Hwa-Yeul Oh , Pil-Sang Yun , Je-Hyeong Park
发明人： Young-Wook LEE , Hwa-Yeul Oh , Pil-Sang Yun , Je-Hyeong Park
IPC分类号： G02F1/1343 , G02F1/1368
CPC分类号： G02F1/13306 , G02F1/136213 , G02F1/13624 , G02F2001/134345 , G09G3/3659 , G09G2300/0443 , G09G2300/0447 , G09G2300/0809 , G09G2300/0876 , G09G2320/028
摘要： Embodiments of the present invention relate to a liquid crystal display and a driving method thereof. According to an embodiment, the liquid crystal display comprises a pixel electrode having a first subpixel electrode, a second subpixel electrode, and a third subpixel electrode electrically separated from each other. The liquid crystal display comprises a first thin film transistor connected to the first subpixel electrode, a second thin film transistor connected to the second subpixel electrode, a third thin film transistor connected to the third subpixel electrode, and a fourth thin film transistor connected to the second subpixel electrode and the third subpixel electrode. The liquid crystal display comprises a first gate line connected to the first to third thin film transistors, a second gate line connected to the fourth thin film transistor, a data line connected to the first and second thin film transistors, and a storage electrode line connected to the third thin film transistor.
摘要翻译：本发明的实施例涉及一种液晶显示器及其驱动方法。根据实施例，液晶显示器包括具有彼此电分离的第一子像素电极，第二子像素电极和第三子像素电极的像素电极。液晶显示器包括连接到第一子像素电极的第一薄膜晶体管，连接到第二子像素电极的第二薄膜晶体管，连接到第三子像素电极的第三薄膜晶体管和连接到第三子像素电极的第四薄膜晶体管第二子像素电极和第三子像素电极。液晶显示器包括连接到第一至第三薄膜晶体管的第一栅极线，连接到第四薄膜晶体管的第二栅极线，连接到第一和第二薄膜晶体管的数据线，以及连接到第一和第二薄膜晶体管的存储电极线到第三薄膜晶体管。

8. 发明申请

US20100051934A1 THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：薄膜晶体管阵列及其制造方法
公开(公告)号：US20100051934A1
公开(公告)日：2010-03-04
申请号：US12504483
申请日：2009-07-16
申请人： Jong-Hyun Choung , Bong-Kyun Kim , Byeong-Jin Lee , Sun-Young Hong , Pil-Sang Yun , Hong-Sick Park , Dong-Ju Yang , Young-Joo Choi , Nam-Seok Suh
发明人： Jong-Hyun Choung , Bong-Kyun Kim , Byeong-Jin Lee , Sun-Young Hong , Pil-Sang Yun , Hong-Sick Park , Dong-Ju Yang , Young-Joo Choi , Nam-Seok Suh
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/7869 , H01L27/1225 , H01L27/124 , H01L27/1288
摘要： A thin film transistor array panel and a method of manufacturing the same are provided according to one or more embodiments. In an embodiment, a method includes: forming a gate line on an insulation substrate; stacking a gate insulating layer, an oxide semiconductor layer, a first barrier layer, and a first copper layer on the gate line; performing a photolithography process on the oxide semiconductor layer, the first barrier layer, and the first copper layer and forming a data line including a source electrode, a drain electrode, and an oxide semiconductor pattern; forming a passivation layer having the contact hole that exposes the drain electrode on the data line and the drain electrode; and forming a pixel electrode that is connected to the drain electrode through the contact hole on the passivation layer, wherein the forming of a data line, a drain electrode, and an oxide semiconductor pattern includes wet etching the first copper layer and then wet etching the first barrier layer and the oxide semiconductor layer.
摘要翻译：根据一个或多个实施例提供薄膜晶体管阵列面板及其制造方法。在一个实施例中，一种方法包括：在绝缘基板上形成栅极线; 在栅极线上堆叠栅极绝缘层，氧化物半导体层，第一势垒层和第一铜层; 在所述氧化物半导体层，所述第一阻挡层和所述第一铜层上进行光刻工艺，并形成包括源电极，漏电极和氧化物半导体图案的数据线; 形成具有使数据线和漏电极上的漏电极露出的接触孔的钝化层; 以及形成通过钝化层上的接触孔连接到漏电极的像素电极，其中数据线，漏电极和氧化物半导体图案的形成包括湿蚀刻第一铜层，然后湿蚀刻第一阻挡层和氧化物半导体层。

9. 发明申请

US20090212290A1 DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：显示面板及其制造方法
公开(公告)号：US20090212290A1
公开(公告)日：2009-08-27
申请号：US12354115
申请日：2009-01-15
申请人： Joo-Ae YOUN , Yang-Ho BAE , Chang-Oh JEONG , Chong-Chul CHAI , Pil-Sang YUN , Honglong NING , Byeong-Beom KIM
发明人： Joo-Ae YOUN , Yang-Ho BAE , Chang-Oh JEONG , Chong-Chul CHAI , Pil-Sang YUN , Honglong NING , Byeong-Beom KIM
IPC分类号： H01L27/088 , H01L21/77
CPC分类号： H01L33/0041 , H01L27/124 , H01L29/458
摘要： A display panel includes; a lower gate line, a lower data line disposed substantially perpendicular to the lower gate line, a thin film transistor (“TFT”) connected to the lower gate line and the lower data line, an insulating layer disposed on the lower gate line, the lower data line, and the TFT and having a plurality of trenches exposing the lower gate line and the lower data line, an upper gate line disposed in the trench on the lower gate line, an upper data line disposed in the trench on the lower data line, and a pixel electrode connected to the TFT.
摘要翻译：显示面板包括：下栅极线，基本上垂直于下栅极线设置的下数据线，连接到下栅极线和下数据线的薄膜晶体管（“TFT”），设置在下栅极线上的绝缘层，下数据线和TFT，并且具有暴露下栅极线和下数据线的多个沟槽，设置在下栅极线上的沟槽中的上栅极线，设置在下数据上的沟槽中的上数据线线和与TFT连接的像素电极。

10. 发明授权

US09325006B2 Method for preparing positive active material for lithium ion secondary battery, positive active material prepared thereby, and lithium ion secondary battery including the same 有权
标题翻译：制备锂离子二次电池用正极活性物质的方法，由其制备的正极活性物质和包括其的锂离子二次电池
公开(公告)号：US09325006B2
公开(公告)日：2016-04-26
申请号：US13449109
申请日：2012-04-17
申请人： Yun Ju Cho , Pil Sang Yun , Mi Sun Lee , Hae In Cho
发明人： Yun Ju Cho , Pil Sang Yun , Mi Sun Lee , Hae In Cho
IPC分类号： H01M4/485 , H01M2/14 , H01M4/505 , C01D1/20 , C01D1/22 , C01G1/02 , H01M4/525
CPC分类号： H01M4/505 , C01D1/20 , C01D1/22 , C01G1/02 , H01M4/525 , Y02E60/122
摘要： A method for preparing a positive active material for a lithium ion secondary battery, the method including obtaining a mixture by mixing a lithium containing compound and metal oxide, distributing powder of a lithium containing compound into a furnace, and heat treating the mixture in the furnace, wherein a thermal decomposition temperature of the lithium containing compound power distributed into the furnace is lower than that of the lithium containing compound mixed with the metal oxide.
摘要翻译：一种锂离子二次电池用正极活性物质的制造方法，其特征在于，通过混合含锂化合物和金属氧化物而得到混合物，将含锂化合物的粉末分配到炉中，并对所述炉内的混合物进行热处理其中分配到炉中的含锂化合物功率的热分解温度低于与金属氧化物混合的含锂化合物的热分解温度。

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