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1. 发明授权

US07813182B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US07813182B2
公开(公告)日：2010-10-12
申请号：US12272118
申请日：2008-11-17
申请人： Yoshihiko Kamata , Takayuki Harima , Yasuhiko Honda
发明人： Yoshihiko Kamata , Takayuki Harima , Yasuhiko Honda
IPC分类号： G11C16/28
CPC分类号： G11C16/0483 , G11C7/06 , G11C7/062 , G11C11/5642 , G11C16/28 , G11C2207/063 , G11C2211/5634 , G11C2211/5645
摘要： A semiconductor memory has a first-stage amplifier circuit, wherein data stored in a memory cells is read based on a potential between an amplifier input MOS transistor and an amplifier reference MOS transistor, the potential being outputted from the first-stage amplifier circuit.
摘要翻译：半导体存储器具有第一级放大器电路，其中基于放大器输入MOS晶体管和放大器参考MOS晶体管之间的电位来读取存储在存储单元中的数据，该电位从第一级放大器电路输出。

2. 发明申请

US20090115500A1 VOLTAGE GENERATING CIRCUIT 失效
标题翻译：电压发生电路
公开(公告)号：US20090115500A1
公开(公告)日：2009-05-07
申请号：US12260366
申请日：2008-10-29
申请人： Masaaki Kuwagata , Yasuhiko Honda , Yoshihiko Kamata
发明人： Masaaki Kuwagata , Yasuhiko Honda , Yoshihiko Kamata
IPC分类号： G05F1/10
CPC分类号： G11C16/30 , G11C5/143 , G11C5/145 , H02M3/073 , H02M2001/0025 , H02M2001/0032 , Y02B70/16
摘要： A voltage generating circuit for outputting a voltage from an output terminal, has a first voltage dividing circuit which is connected between the output terminal and ground; a switch circuit connected between the output terminal and the first voltage dividing circuit; a first voltage detecting circuit which outputs a first pumping signal corresponding to a comparison result; a second voltage dividing circuit which is connected between the output terminal and the ground; a second voltage detecting circuit which outputs a second pumping signal corresponding to a comparison result; a pump circuit that outputs a voltage boosted from a power supply voltage; and a boost circuit which has a capacitive element having one end connected to the voltage dividing resistor of the first voltage dividing circuit.
摘要翻译：用于从输出端子输出电压的电压产生电路具有连接在输出端子与地之间的第一分压电路; 连接在输出端和第一分压电路之间的开关电路; 第一电压检测电路，输出与比较结果对应的第一泵浦信号; 连接在输出端子和地之间的第二分压电路; 第二电压检测电路，其输出与比较结果相对应的第二泵浦信号; 输出从电源电压提升的电压的泵电路; 以及升压电路，其具有一端与第一分压电路的分压电阻连接的电容元件。

3. 发明授权

US07751252B2 Semiconductor memory with a reference current generating circuit having a reference current generating section and an amplifier section 有权
标题翻译：具有参考电流产生电路的半导体存储器，具有参考电流产生部分和放大器部分
公开(公告)号：US07751252B2
公开(公告)日：2010-07-06
申请号：US12273979
申请日：2008-11-19
申请人： Jin Kashiwagi , Yasuhiko Honda , Yoshihiko Kamata
发明人： Jin Kashiwagi , Yasuhiko Honda , Yoshihiko Kamata
IPC分类号： G11C16/28
CPC分类号： G11C7/14 , G11C16/28
摘要： A semiconductor memory capable of storing and reading data in a memory cell for holding the data corresponding to a threshold voltage has a reference current generating circuit having a reference current generating section and an amplifier section.
摘要翻译：能够存储和读取存储单元中用于保持对应于阈值电压的数据的数据的半导体存储器具有参考电流产生电路，其具有参考电流产生部分和放大器部分。

4. 发明授权

US08238154B2 Nonvolatile semiconductor memory with charge storage layers and control gates 有权
标题翻译：具有电荷存储层和控制栅极的非易失性半导体存储器
公开(公告)号：US08238154B2
公开(公告)日：2012-08-07
申请号：US12552563
申请日：2009-09-02
申请人： Mario Sako , Jun Fujimoto , Noriyasu Kumazaki , Yasuhiko Honda , Yoshihiko Kamata
发明人： Mario Sako , Jun Fujimoto , Noriyasu Kumazaki , Yasuhiko Honda , Yoshihiko Kamata
IPC分类号： G11C16/04
CPC分类号： G11C5/147 , G11C16/0483 , G11C16/30
摘要： A nonvolatile semiconductor memory includes a memory cell array, bit lines, a first voltage generator, and a second voltage generator. The memory cell array includes memory cells. The bit lines each of which is connected electrically to one end of the current path of the corresponding one of the memory cells. The first voltage generator which is capable of supplying via a first output terminal to the bit lines a first voltage externally supplied or a third voltage which is obtained by stepping down a second voltage supplied and higher than the first voltage and which is as high as the first voltage. The second voltage generator which is capable of supplying a fourth voltage obtained by stepping down the second voltage to the bit lines via a second output terminal when the first voltage generator steps down the second voltage to generate the third voltage.
摘要翻译：非易失性半导体存储器包括存储单元阵列，位线，第一电压发生器和第二电压发生器。存储单元阵列包括存储单元。每个位线与相应的一个存储单元的电流路径的一端电连接。第一电压发生器，其能够经由第一输出端子向位线提供外部提供的第一电压或通过降低提供的并高于第一电压的第二电压而获得的第三电压，并且其与第一电压一样高第一电压。第二电压发生器，当第一电压发生器降低第二电压以产生第三电压时，能够将通过第二输出端降低第二电压而获得的第四电压提供给位线。

5. 发明申请

US20100214837A1 NONVOLATILE SEMICONDUCTOR MEMORY WITH CHARGE STORAGE LAYERS AND CONTROL GATES 有权
标题翻译：具有充电储存层和控制栅的非易失性半导体存储器
公开(公告)号：US20100214837A1
公开(公告)日：2010-08-26
申请号：US12552563
申请日：2009-09-02
申请人： Mario SAKO , Jun Fujimoto , Noriyasu Kumazaki , Yasuhiko Honda , Yoshihiko Kamata
发明人： Mario SAKO , Jun Fujimoto , Noriyasu Kumazaki , Yasuhiko Honda , Yoshihiko Kamata
IPC分类号： G11C16/04 , G11C11/00
CPC分类号： G11C5/147 , G11C16/0483 , G11C16/30
摘要： A nonvolatile semiconductor memory includes a memory cell array, bit lines, a first voltage generator, and a second voltage generator. The memory cell array includes memory cells. The bit lines each of which is connected electrically to one end of the current path of the corresponding one of the memory cells. The first voltage generator which is capable of supplying via a first output terminal to the bit lines a first voltage externally supplied or a third voltage which is obtained by stepping down a second voltage supplied and higher than the first voltage and which is as high as the first voltage. The second voltage generator which is capable of supplying a fourth voltage obtained by stepping down the second voltage to the bit lines via a second output terminal when the first voltage generator steps down the second voltage to generate the third voltage.
摘要翻译：非易失性半导体存储器包括存储单元阵列，位线，第一电压发生器和第二电压发生器。存储单元阵列包括存储单元。每个位线与相应的一个存储单元的电流路径的一端电连接。第一电压发生器，其能够经由第一输出端子向位线提供外部提供的第一电压或通过降低提供的并高于第一电压的第二电压而获得的第三电压，并且其与第一电压一样高第一电压。第二电压发生器，当第一电压发生器降低第二电压以产生第三电压时，能够将通过第二输出端降低第二电压而获得的第四电压提供给位线。

6. 发明授权

US07750727B2 Voltage generating circuit 失效
标题翻译：电压发生电路
公开(公告)号：US07750727B2
公开(公告)日：2010-07-06
申请号：US12260366
申请日：2008-10-29
申请人： Masaaki Kuwagata , Yasuhiko Honda , Yoshihiko Kamata
发明人： Masaaki Kuwagata , Yasuhiko Honda , Yoshihiko Kamata
IPC分类号： G05F1/10
CPC分类号： G11C16/30 , G11C5/143 , G11C5/145 , H02M3/073 , H02M2001/0025 , H02M2001/0032 , Y02B70/16
摘要： A voltage generating circuit for outputting a voltage from an output terminal, has a first voltage dividing circuit which is connected between the output terminal and ground; a switch circuit connected between the output terminal and the first voltage dividing circuit; a first voltage detecting circuit which outputs a first pumping signal corresponding to a comparison result; a second voltage dividing circuit which is connected between the output terminal and the ground; a second voltage detecting circuit which outputs a second pumping signal corresponding to a comparison result; a pump circuit that outputs a voltage boosted from a power supply voltage; and a boost circuit which has a capacitive element having one end connected to the voltage dividing resistor of the first voltage dividing circuit.
摘要翻译：用于从输出端子输出电压的电压产生电路具有连接在输出端子与地之间的第一分压电路; 连接在输出端和第一分压电路之间的开关电路; 第一电压检测电路，输出与比较结果对应的第一泵浦信号; 连接在输出端子和地之间的第二分压电路; 第二电压检测电路，其输出与比较结果相对应的第二泵浦信号; 输出从电源电压提升的电压的泵电路; 以及升压电路，其具有一端与第一分压电路的分压电阻连接的电容元件。

7. 发明申请

US20150251188A1 REGENERATED CUTTING BLADE AND SHEARING TYPE GRINDER 审中-公开
标题翻译：再生切割刀片和剪切型磨床
公开(公告)号：US20150251188A1
公开(公告)日：2015-09-10
申请号：US14417344
申请日：2012-08-28
申请人： Naoya Wada , Naoki Ueno , Yasuhiko Honda , Isao Nagai
发明人： Naoya Wada , Naoki Ueno , Yasuhiko Honda , Isao Nagai
IPC分类号： B02C18/18 , B02C18/14
CPC分类号： B02C18/184 , B02C18/142 , B02C18/145
摘要： To present a regenerated cutting blade, capable of regenerating efficiently by saving the cost and labor for regenerating a cutting blade, and improved in the grinding efficiency of a shearing type grinder to be close to that of a new cutting blade, when mounted and used in a shearing type grinder, including a fixed part 125, and a blade tip 127 projecting outward from this fixed part 125, in which the blade tip 127 has a leading end edge 109 pointed toward the rotating direction, and side edges 110 on the lateral side outer periphery including the blade tip 127, the leading end edge 109 and the side edges 110 are regenerated and formed by build-up welding, and the lateral sides are provided with slip preventive build-up welding parts 111, 112, 113 of the workpiece extending from the side edges 110 toward the central side of its rotation or the central direction, being formed by three regenerating processes.
摘要翻译：为了提供能够通过节省用于再生切割刀片的成本和劳动力而有效地再生的再生切割刀片，并且将剪切式研磨机的研磨效率提高为接近于新的切割刀片的磨削效率，当安装和使用时包括固定部分125的剪切式研磨机以及从该固定部125向外突出的叶片尖端127，其中叶片尖端127具有朝向旋转方向指向的前端边缘109，侧面侧的侧边缘110 包括叶片尖端127，前端缘109和侧边缘110的外周边通过堆积焊接再生和形成，并且侧边设置有工件的防滑成型焊接部111,112,113 从侧边缘110向其旋转中心方向或中心方向延伸，由三个再生过程形成。

8. 发明授权

US08130545B2 Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08130545B2
公开(公告)日：2012-03-06
申请号：US12938435
申请日：2010-11-03
申请人： Yasuhiko Honda , Takahiro Suzuki , Masao Iwamoto , Kiyochika Kinjo
发明人： Yasuhiko Honda , Takahiro Suzuki , Masao Iwamoto , Kiyochika Kinjo
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C29/00
摘要： A nonvolatile semiconductor storage device capable of storing a plurality of bits of data in one memory cell by assigning multivalued data having a higher-order bit selected from one of a pair of data in a first unit and a lower-order bit selected from the other of the pair of data to each threshold voltage of the memory cell, wherein in a first write operation that processes data in the first unit, the logic of one of the higher-order bit and the lower-order bit is fixed, and two pieces of multivalued data that maximize the difference between the threshold voltages are assigned, thereby storing one bit of input data in the one memory cell in a pseudo binary state, and in a second write operation that processes data in a second unit larger than the first unit, a plurality of bits of input data is stored in the one memory cell in a multivalued state, and parity data for error correction in the second unit is stored in the memory cell.
摘要翻译：一种非易失性半导体存储装置，其能够通过分配具有从第一单位中选择的一对数据中的一个中选择的高阶位的多值数据和从另一个存储单元中选择的低位位来存储多个数据位在一个存储单元中所述数据对与所述存储单元的每个阈值电压相关，其中在处理所述第一单元中的数据的第一写入操作中，所述高位和低位中的一个的逻辑被固定，并且两个分配最大化阈值电压之间的差异的多值数据，从而将一位存储单元中的一位输入数据存储在伪二进制状态，并且在第二写入操作中处理大于第一单元的第二单元中的数据输入数据的多个位以多值状态存储在一个存储单元中，第二单元中用于纠错的奇偶校验数据被存储在存储单元中。

9. 发明授权

US08098532B2 Non-volatile semiconductor storage device with address search circuit used when writing 有权
标题翻译：写入时使用地址搜索电路的非易失性半导体存储器件
公开(公告)号：US08098532B2
公开(公告)日：2012-01-17
申请号：US12273813
申请日：2008-11-19
申请人： Yuji Komine , Shinya Fujisawa , Yasuhiko Honda , Ryu Hondai , Takamichi Kasai , Takahiro Suzuki
发明人： Yuji Komine , Shinya Fujisawa , Yasuhiko Honda , Ryu Hondai , Takamichi Kasai , Takahiro Suzuki
IPC分类号： G11C7/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C15/046 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459
摘要： A non-volatile semiconductor storage device includes a memory cell array having a plurality of non-volatile memory cells, an address search circuit which searches for write object data and outputs an address where the write object data is present, when writing data into the non-volatile memory cells, and a control circuit which exercises control to write the write object data into the non-volatile memory cells in accordance with the address output from the address search circuit.
摘要翻译：非挥发性半导体存储装置包括具有多个非易失性存储单元的存储单元阵列，地址搜索电路，当将数据写入非易失性存储单元时，搜索写入对象数据并输出存在写入对象数据的地址并且控制电路根据从地址搜索电路输出的地址进行控制以将写入目标数据写入非易失性存储单元。

10. 发明授权

US07924620B2 Nonvolatile semiconductor memory including charge accumulation layer and control gate 失效
标题翻译：非易失性半导体存储器，包括电荷累积层和控制栅极
公开(公告)号：US07924620B2
公开(公告)日：2011-04-12
申请号：US12543161
申请日：2009-08-18
申请人： Yasuhiko Honda
发明人： Yasuhiko Honda
IPC分类号： G11C16/00
CPC分类号： G11C8/08 , G11C16/0483 , G11C16/10
摘要： A nonvolatile semiconductor memory includes a transistor, a first MOS, a second MOS, a first voltage circuit, and a second voltage circuit. The transistor includes a accumulation layer, a control gate, and a first impurity diffused layer. The first MOS includes a first electrode and a second layer. The second MOS includes a second electrode and a third layer, after the channels being formed, the first MOS and the second MOS being cut off. The first voltage circuit applies a first voltage to an active region to generate a forward bias. The second voltage circuit applies a second voltage, and a third voltage to the control gate of the transistor, after the first voltage circuit charges the first to third impurity diffused layer to the first voltage, the second voltage circuit applying the second voltage and the third voltage to the control gate of the transistor.
摘要翻译：非易失性半导体存储器包括晶体管，第一MOS，第二MOS，第一电压电路和第二电压电路。晶体管包括累积层，控制栅极和第一杂质扩散层。第一MOS包括第一电极和第二层。第二MOS包括第二电极和第三层，在形成沟道之后，第一MOS和第二MOS被截止。第一电压电路向有源区域施加第一电压以产生正向偏置。在第一电压电路将第一至第三杂质扩散层充电至第一电压之后，第二电压电路将第二电压和第三电压施加到晶体管的控制栅极，施加第二电压的第二电压电路和施加第二电压的第二电压电路电压到晶体管的控制栅极。

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