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1. 发明授权

US08516197B2 Write-through cache optimized for dependence-free parallel regions 有权
标题翻译：针对无依赖并行区域优化的直写缓存
公开(公告)号：US08516197B2
公开(公告)日：2013-08-20
申请号：US13025706
申请日：2011-02-11
申请人： Alexandre E. Eichenberger , Alan G. Gara , Martin Ohmacht , Vijayalakshmi Srinivasan
发明人： Alexandre E. Eichenberger , Alan G. Gara , Martin Ohmacht , Vijayalakshmi Srinivasan
IPC分类号： G06F12/00
CPC分类号： G06F12/0837
摘要： An apparatus, method and computer program product for improving performance of a parallel computing system. A first hardware local cache controller associated with a first local cache memory device of a first processor detects an occurrence of a false sharing of a first cache line by a second processor running the program code and allows the false sharing of the first cache line by the second processor. The false sharing of the first cache line occurs upon updating a first portion of the first cache line in the first local cache memory device by the first hardware local cache controller and subsequent updating a second portion of the first cache line in a second local cache memory device by a second hardware local cache controller.
摘要翻译：一种用于提高并行计算系统性能的装置，方法和计算机程序产品。与第一处理器的第一本地高速缓冲存储器设备相关联的第一硬件本地高速缓存控制器通过运行程序代码的第二处理器检测出第一高速缓存行的虚假共享的发生，并允许第一高速缓存行的错误共享由第二处理器。当由第一硬件本地高速缓存控制器更新第一本地高速缓存存储器设备中的第一高速缓存行的第一部分并且随后在第二本地高速缓冲存储器中更新第一高速缓存行的第二部分时，发生第一高速缓存行的错误共享设备由第二硬件本地缓存控制器。

2. 发明授权

US08627010B2 Write-through cache optimized for dependence-free parallel regions 有权
标题翻译：针对无依赖并行区域优化的直写缓存
公开(公告)号：US08627010B2
公开(公告)日：2014-01-07
申请号：US13604349
申请日：2012-09-05
申请人： Alexandre E. Eichenberger , Alan G. Gara , Martin Ohmacht , Vijayalakshmi Srinivasan
发明人： Alexandre E. Eichenberger , Alan G. Gara , Martin Ohmacht , Vijayalakshmi Srinivasan
IPC分类号： G06F12/00
CPC分类号： G06F12/0837
摘要： An apparatus and computer program product for improving performance of a parallel computing system. A first hardware local cache controller associated with a first local cache memory device of a first processor detects an occurrence of a false sharing of a first cache line by a second processor running the program code and allows the false sharing of the first cache line by the second processor. The false sharing of the first cache line occurs upon updating a first portion of the first cache line in the first local cache memory device by the first hardware local cache controller and subsequent updating a second portion of the first cache line in a second local cache memory device by a second hardware local cache controller.
摘要翻译：一种用于提高并行计算系统性能的设备和计算机程序产品。与第一处理器的第一本地高速缓冲存储器设备相关联的第一硬件本地高速缓存控制器通过运行程序代码的第二处理器来检测第一高速缓存行的虚假共享的发生，并允许第一高速缓存行的错误共享由第二处理器。当由第一硬件本地高速缓存控制器更新第一本地高速缓存存储器设备中的第一高速缓存行的第一部分并且随后在第二本地高速缓冲存储器中更新第一高速缓存行的第二部分时，发生第一高速缓存行的错误共享设备由第二硬件本地缓存控制器。

3. 发明申请

US20120210073A1 WRITE-THROUGH CACHE OPTIMIZED FOR DEPENDENCE-FREE PARALLEL REGIONS 有权
标题翻译：写入 - 通过高速缓存优化为无依赖的并行区域
公开(公告)号：US20120210073A1
公开(公告)日：2012-08-16
申请号：US13025706
申请日：2011-02-11
申请人： Alexandre E. Eichenberger , Alan Gara , Martin Ohmacht , Vijayalakshmi Srinivasan
发明人： Alexandre E. Eichenberger , Alan Gara , Martin Ohmacht , Vijayalakshmi Srinivasan
IPC分类号： G06F12/08
CPC分类号： G06F12/0837
摘要： An apparatus, method and computer program product for improving performance of a parallel computing system. A first hardware local cache controller associated with a first local cache memory device of a first processor detects an occurrence of a false sharing of a first cache line by a second processor running the program code and allows the false sharing of the first cache line by the second processor. The false sharing of the first cache line occurs upon updating a first portion of the first cache line in the first local cache memory device by the first hardware local cache controller and subsequent updating a second portion of the first cache line in a second local cache memory device by a second hardware local cache controller.
摘要翻译：一种用于提高并行计算系统性能的装置，方法和计算机程序产品。与第一处理器的第一本地高速缓冲存储器设备相关联的第一硬件本地高速缓存控制器通过运行程序代码的第二处理器来检测第一高速缓存行的虚假共享的发生，并允许第一高速缓存行的错误共享由第二处理器。当由第一硬件本地高速缓存控制器更新第一本地高速缓存存储器设备中的第一高速缓存行的第一部分并且随后在第二本地高速缓冲存储器中更新第一高速缓存行的第二部分时，发生第一高速缓存行的错误共享设备由第二硬件本地缓存控制器。

4. 发明申请

US20120331232A1 WRITE-THROUGH CACHE OPTIMIZED FOR DEPENDENCE-FREE PARALLEL REGIONS 有权
标题翻译：写入 - 通过高速缓存优化为无依赖的并行区域
公开(公告)号：US20120331232A1
公开(公告)日：2012-12-27
申请号：US13604349
申请日：2012-09-05
申请人： Alexandre E. Eichenberger , Alan Gara , Martin Ohmacht , Vijayalakshmi Srinivasan
发明人： Alexandre E. Eichenberger , Alan Gara , Martin Ohmacht , Vijayalakshmi Srinivasan
IPC分类号： G06F12/08
CPC分类号： G06F12/0837
摘要： An apparatus and computer program product for improving performance of a parallel computing system. A first hardware local cache controller associated with a first local cache memory device of a first processor detects an occurrence of a false sharing of a first cache line by a second processor running the program code and allows the false sharing of the first cache line by the second processor. The false sharing of the first cache line occurs upon updating a first portion of the first cache line in the first local cache memory device by the first hardware local cache controller and subsequent updating a second portion of the first cache line in a second local cache memory device by a second hardware local cache controller.
摘要翻译：一种用于提高并行计算系统性能的设备和计算机程序产品。与第一处理器的第一本地高速缓冲存储器设备相关联的第一硬件本地高速缓存控制器通过运行程序代码的第二处理器来检测第一高速缓存行的虚假共享的发生，并允许第一高速缓存行的错误共享由第二处理器。当由第一硬件本地高速缓存控制器更新第一本地高速缓存存储器设备中的第一高速缓存行的第一部分并且随后在第二本地高速缓冲存储器中更新第一高速缓存行的第二部分时，发生第一高速缓存行的错误共享设备由第二硬件本地缓存控制器。

5. 发明授权

US09092341B2 Methods of cache preloading on a partition or a context switch 有权
标题翻译：缓存预加载在分区或上下文切换上的方法
公开(公告)号：US09092341B2
公开(公告)日：2015-07-28
申请号：US13545304
申请日：2012-07-10
申请人： Harold W. Cain, III , Vijayalakshmi Srinivasan , Jason Zebchuk
发明人： Harold W. Cain, III , Vijayalakshmi Srinivasan , Jason Zebchuk
IPC分类号： G06F12/00 , G06F12/08 , G06F12/10 , G06F12/12
CPC分类号： G06F12/0862 , G06F12/0813 , G06F12/0866 , G06F12/1009 , G06F12/122 , G06F12/123 , G06F2212/602 , G06F2212/69
摘要： A scheme referred to as a “Region-based cache restoration prefetcher” (RECAP) is employed for cache preloading on a partition or a context switch. The RECAP exploits spatial locality to provide a bandwidth-efficient prefetcher to reduce the “cold” cache effect caused by multiprogrammed virtualization. The RECAP groups cache blocks into coarse-grain regions of memory, and predicts which regions contain useful blocks that should be prefetched the next time the current virtual machine executes. Based on these predictions, and using a simple compression technique that also exploits spatial locality, the RECAP provides a robust prefetcher that improves performance without excessive bandwidth overhead or slowdown.
摘要翻译：被称为“基于区域的高速缓存恢复预取器”（RECAP）的方案被用于在分区或上下文切换上进行高速缓存预加载。 RECAP利用空间局部性提供带宽有效的预取器，以减少由多编程虚拟化引起的“冷”缓存效应。 RECAP组将高速缓存块缓存到内存的粗粒度区域中，并预测哪些区域包含下一次执行当前虚拟机时应预取的有用块。基于这些预测，并且使用也利用空间局部性的简单压缩技术，RECAP提供了一种强大的预取器，可以在没有过多带宽开销或减速的情况下提高性能。

6. 发明授权

US08589762B2 Adaptive multi-bit error correction in endurance limited memories 失效
标题翻译：耐力有限的存储器中的自适应多位错误校正
公开(公告)号：US08589762B2
公开(公告)日：2013-11-19
申请号：US13176092
申请日：2011-07-05
申请人： Jude A. Rivers , Vijayalakshmi Srinivasan
发明人： Jude A. Rivers , Vijayalakshmi Srinivasan
IPC分类号： G11C29/00
CPC分类号： G11C29/52 , G06F11/1048 , G11C16/3418 , G11C29/028 , G11C2029/0409 , G11C2029/0411
摘要： Multi-bit stuck-at fault error recovery can be enabled by adaptive multi-bit error correction method, in which the overhead of error correction hardware is reduced without affecting the lifetime of the memory device. Error correction logic hardware is decoupled from memory blocks. An error correction logic block is partitioned such that error correction logic entries support different number of error correction capabilities based on the probability of occurrence of the different number of errors in different memory blocks. Faulty memory blocks are mapped to appropriate error correction logic entries. The mapping can be one-to-one or many-to-one depending on embodiments. The adaptive partitioning of the error correction logic entries can be configured to match projected statistical distribution of errors in logic blocks, and can reduce the total error correction logic overhead, provide sufficient error correction, and/or extend the lifetime of the memory device.
摘要翻译：可以通过自适应多位错误校正方法来实现多位卡滞故障恢复，其中降低了纠错硬件的开销，而不影响存储器件的使用寿命。纠错逻辑硬件与存储器块分离。错误校正逻辑块被分区，使得纠错逻辑条目基于在不同存储器块中出现不同数量的错误的概率来支持不同数量的纠错能力。错误的存储器块被映射到适当的纠错逻辑条目。取决于实施例，映射可以是一对一或多对一。错误校正逻辑条目的自适应分割可以被配置为匹配逻辑块中的误差的预计统计分布，并且可以减少总误差校正逻辑开销，提供足够的纠错和/或延长存储器件的寿命。

7. 发明授权

US08521999B2 Executing touchBHT instruction to pre-fetch information to prediction mechanism for branch with taken history 有权
标题翻译：执行touchBHT指令，预先获取信息到具有历史记录的分支预测机制
公开(公告)号：US08521999B2
公开(公告)日：2013-08-27
申请号：US12721933
申请日：2010-03-11
申请人： Philip G. Emma , Allan M. Hartstein , Brian R. Prasky , Thomas R. Puzak , Vijayalakshmi Srinivasan
发明人： Philip G. Emma , Allan M. Hartstein , Brian R. Prasky , Thomas R. Puzak , Vijayalakshmi Srinivasan
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/30058 , G06F9/30145 , G06F9/3846 , G06F9/3848
摘要： A method comprising receiving a branch instruction, decoding a branch address and the branch instruction, executing a branch action associated with the branch address, determining whether a branch associated with the branch action was taken, and saving an identifier of the branch instruction and in indicator that the branch action was taken in a prefetch history table responsive to determining that the branch associated with the branch action was taken.
摘要翻译：一种方法，包括接收分支指令，解码分支地址和分支指令，执行与分支地址相关联的分支动作，确定是否采用与分支动作相关联的分支，以及保存分支指令的标识符和指示符响应于确定与分支动作相关联的分支被采取，分支动作被采取在预取历史表中。

8. 发明申请

US20130013977A1 ADAPTIVE MULTI-BIT ERROR CORRECTION IN ENDURANCE LIMITED MEMORIES 失效
标题翻译：自适应多重错误修正在有限的记忆
公开(公告)号：US20130013977A1
公开(公告)日：2013-01-10
申请号：US13176092
申请日：2011-07-05
申请人： Jude A. Rivers , Vijayalakshmi Srinivasan
发明人： Jude A. Rivers , Vijayalakshmi Srinivasan
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G11C29/52 , G06F11/1048 , G11C16/3418 , G11C29/028 , G11C2029/0409 , G11C2029/0411
摘要： Multi-bit stuck-at fault error recovery can be enabled by adaptive multi-bit error correction method, in which the overhead of error correction hardware is reduced without affecting the lifetime of the memory device. Error correction logic hardware is decoupled from memory blocks. An error correction logic block is partitioned such that error correction logic entries support different number of error correction capabilities based on the probability of occurrence of the different number of errors in different memory blocks. Faulty memory blocks are mapped to appropriate error correction logic entries. The mapping can be one-to-one or many-to-one depending on embodiments. The adaptive partitioning of the error correction logic entries can be configured to match projected statistical distribution of errors in logic blocks, and can reduce the total error correction logic overhead, provide sufficient error correction, and/or extend the lifetime of the memory device.
摘要翻译：可以通过自适应多位错误校正方法来实现多位卡滞故障恢复，其中降低了纠错硬件的开销，而不影响存储器件的使用寿命。纠错逻辑硬件与存储器块分离。错误校正逻辑块被分区，使得纠错逻辑条目基于在不同存储器块中出现不同数量的错误的概率来支持不同数量的纠错能力。错误的存储器块被映射到适当的纠错逻辑条目。取决于实施例，映射可以是一对一或多对一。错误校正逻辑条目的自适应分割可以被配置为匹配逻辑块中的误差的预测统计分布，并且可以减少总误差校正逻辑开销，提供足够的纠错和/或延长存储器件的寿命。

9. 发明申请

US20130007423A1 PREDICTING OUT-OF-ORDER INSTRUCTION LEVEL PARALLELISM OF THREADS IN A MULTI-THREADED PROCESSOR 有权
标题翻译：在多线程处理器中预测线程的超出指令级别并行列表
公开(公告)号：US20130007423A1
公开(公告)日：2013-01-03
申请号：US13172218
申请日：2011-06-29
申请人： Ioana Monica Burcea , Alper Buyuktosunoglu , Brian Robert Prasky , Vijayalakshmi Srinivasan
发明人： Ioana Monica Burcea , Alper Buyuktosunoglu , Brian Robert Prasky , Vijayalakshmi Srinivasan
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3851
摘要： Systems and methods for predicting out-of-order instruction-level parallelism (ILP) of threads being executed in a multi-threaded processor and prioritizing scheduling thereof are described herein. One aspect provides for tracking completion of instructions using a global completion table having a head segment and a tail segment; storing prediction values for each instruction in a prediction table indexed via instruction identifiers associated with each instruction, a prediction value being configured to indicate an instruction is predicted to issue from one of: the head segment and the tail segment; and predicting threads with more instructions issuing from the tail segment have a higher degree of out-of-order instruction-level parallelism. Other embodiments and aspects are also described herein.
摘要翻译：这里描述了用于预测在多线程处理器中执行的线程的无序指令级并行性（ILP）和优先级调度的系统和方法。一个方面提供使用具有头段和尾段的全局完成表跟踪指令的完成; 将每个指令的预测值存储在通过与每个指令相关联的指令标识符索引的预测表中，预测值被配置为指示从头段和尾段之一发出指令; 并且预测具有从尾段发出的更多指令的线程具有更高程度的无序指令级并行性。本文还描述了其它实施例和方面。

10. 发明申请

US20110161780A1 METHOD AND SYSTEM FOR PROVIDING AN IMPROVED STORE-IN CACHE 有权
标题翻译：提供改进存储缓存的方法和系统
公开(公告)号：US20110161780A1
公开(公告)日：2011-06-30
申请号：US13041248
申请日：2011-03-04
申请人： Philip George Emma , Wing K. Luk , Thomas R. Puzak , Vijayalakshmi Srinivasan
发明人： Philip George Emma , Wing K. Luk , Thomas R. Puzak , Vijayalakshmi Srinivasan
IPC分类号： H03M13/00 , G06F11/00
CPC分类号： G06F12/0802 , G06F11/1064 , G06F11/1666
摘要： A hardened store-in cache system includes a store-in cache having lines of a first linesize stored with checkbits, wherein the checkbits include byte-parity bits, and an ancillary store-only cache (ASOC) that holds a copy of most recently stored-to lines of the store-in cache. The ASOC includes fewer lines than the store-in cache, each line of the ASOC having the first linesize stored with the checkbits.
摘要翻译：硬化的存储缓存系统包括具有存储有校验位的第一行的行的存储高速缓存，其中校验位包括字节奇偶校验位，以及保存最近存储的副本的辅助存储高速缓存（ASOC）到存储缓存中的行。 ASOC包括比存储缓存更少的行，ASOC的每一行都具有与检查位一起存储的第一行。

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