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1. 发明申请

US20070155350A1 Method of frequency planning in an ultra wide band system 审中-公开
标题翻译：超宽带系统频率规划方法
公开(公告)号：US20070155350A1
公开(公告)日：2007-07-05
申请号：US11322073
申请日：2005-12-29
申请人： Behzad Razavi , Zaw Soe
发明人： Behzad Razavi , Zaw Soe
IPC分类号： H03J7/32
CPC分类号： H03J1/0008 , H03D7/165
摘要： The present invention provides reduces the number of required synthesizers thereby reducing the area and power concerns to extract/insert a signal from/to a multi-channel communication system and is also known as frequency planning. The highest frequency of operation required for the synthesizers or oscillators is approximately the midpoint of the entire signal frequency range. Two superimposed Weaver architectures are used to form the architecture. The receiver extracts the baseband I and Q signals from the multi-channel communication system, while the transmitter upconverts the baseband I and Q signals to the multi-channel communication system. The Weaver architecture, depending on the select bit, can enhance the image signal and reduce the desired signal or the image signal can be reduced while the desired signal is enhanced. Because the image and signal components are symmetrically displaced from the RF LO, less IF LO frequencies or synthesizers are required to operate the system.
摘要翻译：本发明减少了所需的合成器的数量，从而减少了从多通道通信系统提取/插入信号的面积和功率问题，也被称为频率规划。合成器或振荡器所需的最高运行频率大约是整个信号频率范围的中点。两个叠加的Weaver架构被用来形成架构。接收机从多通道通信系统中提取基带I和Q信号，而发射机将基带I和Q信号上变频到多通道通信系统。取决于选择位的韦弗架构可以增强图像信号并减少所需信号，或者可以在所需信号增强的同时降低图像信号。由于图像和信号分量从RF LO对称地移位，因此需要较少的IF LO频率或合成器来操作系统。

2. 发明申请

US20070236267A1 High-speed latching technique and application to frequency dividers 有权
标题翻译：高速锁存技术和应用于分频器
公开(公告)号：US20070236267A1
公开(公告)日：2007-10-11
申请号：US11398278
申请日：2006-04-05
申请人： Behzad Razavi , Zaw Soe
发明人： Behzad Razavi , Zaw Soe
IPC分类号： H03K3/00
CPC分类号： H03K3/012 , H03K3/356043
摘要： The inventive technique can dynamically adjust the current being applied within the components of a prescaler or divider. This dynamic scaling of the current can improve the speed of the divider by a factor of two or reduce the average current in half when compared to the conventional prescaler. Inverters are used to directly adjust the dynamic value of the currents. The removal of the conventional NMOS device within the conventional circuit eliminates one gate delay in the CML prescaler. Second, the inventive prescaler circuits operate under a current injection/extraction technique. A group of small matched inverters can be used to drive each current switching circuit independently within the entire prescaler as compared to a large buffer driving the entire conventional prescaler. Finally, dynamic current scaling offers the designer additional flexibility in the design trade off between the maximum current applied to the load and achieving the maximum performance.
摘要翻译：本发明的技术可以动态地调节在预分频器或分频器的组件内施加的电流。电流的这种动态缩放可以将分频器的速度提高一倍，或者将传统的预分频器的平均电流减小一半。逆变器用于直接调整电流的动态值。常规电路中的常规NMOS器件的去除消除了CML预分频器中的一个门延迟。第二，本发明的预分频器电路在当前的注入/提取技术下工作。与驱动整个常规预分频器的大型缓冲器相比，一组小型匹配的反相器可以在整个预分频器内单独驱动每个电流开关电路。最后，动态电流扩展为设计人员提供了额外的灵活性，可以在施加到负载的最大电流和实现最大性能之间进行折衷。

3. 发明申请

US20070155348A1 Apparatus and method for ultra wide band architectures 审中-公开
标题翻译：超宽带架构的装置和方法
公开(公告)号：US20070155348A1
公开(公告)日：2007-07-05
申请号：US11321348
申请日：2005-12-29
申请人： Behzad Razavi , Zaw Soe
发明人： Behzad Razavi , Zaw Soe
IPC分类号： H04B1/04
CPC分类号： H04B1/719 , H04B1/71635
摘要： The present invention describes a transmitter/receiver architecture that uses a Weaver architecture in conjunction with digitally controlled adder/subtractor components to insert/extract a signal into/from the multi-channel system. In the transmitter, the selection of the band select bit causes the up/downconverted IF baseband I and Q signals to insert/extract on either side of an RF LO signal. In addition, the image of the first LO is eliminated while the desired signal is enhanced after passing through this new architecture. The invention also adds an RSSI circuit to the MBOA Weaver architecture receiver architecture to detect whether an 802.11 WLAN signal is interfering with the desired UWB signal. If so, the system is designed to detect this interference and jump to a new frequency range to avoid this interference. This invention focuses on devices that operate over the entire UWB band including the newly formed 60 GHz UWB band system.
摘要翻译：本发明描述了一种使用Weaver架构结合数字控制的加法器/减法器组件来将信号插入/从多通道系统中提取的发射机/接收机体系结构。在发射机中，频带选择位的选择会导致上/下转换的IF基带I和Q信号在RF LO信号的任一侧插入/提取。另外，消除了第一个LO的图像，同时在通过这个新架构之后增强了所需的信号。本发明还向MBOA Weaver架构接收机架构添加了RSSI电路，以检测802.11 WLAN信号是否干扰所需的UWB信号。如果是这样，系统被设计为检测这种干扰并跳转到新的频率范围以避免这种干扰。本发明专注于在包括新形成的60GHz UWB频带系统的整个UWB频带上工作的设备。

4. 发明授权

US07084707B2 Low noise amplifier and related method 有权
标题翻译：低噪声放大器及相关方法
公开(公告)号：US07084707B2
公开(公告)日：2006-08-01
申请号：US10711538
申请日：2004-09-24
申请人： Behzad Razavi , Han-Chang Kang
发明人： Behzad Razavi , Han-Chang Kang
IPC分类号： H03F3/04
CPC分类号： H03F3/189 , H03F2200/294 , H03F2200/372
摘要： A low noise amplifier (LNA) for filtering an input signal to generate an output signal. The low noise amplifier includes a switched loading circuit having a plurality of loading units, each of the loading units determining a corresponding center frequency of the low noise amplifier. The switched loading circuit selectively enables a loading unit having the desired corresponding center frequency. At least one converters coupled to the switched loading circuit converts a voltage of the input signal into a loading current and passes the loading current through the enabled loading unit to generate the output signal.
摘要翻译：用于滤波输入信号以产生输出信号的低噪声放大器（LNA）。低噪声放大器包括具有多个加载单元的开关加载电路，每个加载单元确定低噪声放大器的相应中心频率。开关加载电路选择性地启用具有期望的相应中心频率的装载单元。耦合到开关负载电路的至少一个转换器将输入信号的电压转换为负载电流，并将负载电流传递通过使能的负载单元以产生输出信号。

5. 发明授权

US07286625B2 High-speed clock and data recovery circuit 有权
标题翻译：高速时钟和数据恢复电路
公开(公告)号：US07286625B2
公开(公告)日：2007-10-23
申请号：US10616021
申请日：2003-07-09
申请人： Jri Lee , Behzad Razavi
发明人： Jri Lee , Behzad Razavi
IPC分类号： H03D3/24
CPC分类号： H03L7/0995 , H03K3/3562 , H03K3/86 , H03K5/14 , H03K19/215 , H03K2005/00032 , H03L7/091 , H04L7/033
摘要： A 40-Gb/s clock and data recovery (CDR) circuit incorporates a quarter-rate phase detector and a multi-phase voltage controlled oscillator to re-time and de-multiplex a 40-Gb/s input data signal into four 10-Gb/s output data signals. The circuit is fabricated in 0.18 μm CMOS technology.
摘要翻译： 40Gb / s时钟和数据恢复（CDR）电路采用四分之一速率相位检测器和多相压控振荡器，将40 Gb / s输入数据信号重新定时和解复用为四个10- Gb / s输出数据信号。该电路采用0.18毫米CMOS技术制造。

6. 发明授权

US06606489B2 Differential to single-ended converter with large output swing 有权
标题翻译：差分到单端转换器，输出摆幅大
公开(公告)号：US06606489B2
公开(公告)日：2003-08-12
申请号：US09784735
申请日：2001-02-14
申请人： Behzad Razavi , Pengfei Zhang
发明人： Behzad Razavi , Pengfei Zhang
IPC分类号： H04B126
CPC分类号： H03F1/226 , H03F3/45381 , H03F2200/294 , H03F2200/372 , H03F2203/45701
摘要： A method and apparatus of converting differential signals to single-ended signals. The method includes receiving a differential signal comprising a first current and a second current and applying the second current to a first load to generate a first voltage. A third current is generated in response to the first voltage. The first current is summed with the third current and applied to a second load to generate the single-ended signal.
摘要翻译：将差分信号转换为单端信号的方法和装置。该方法包括接收包括第一电流和第二电流的差分信号，并将第二电流施加到第一负载以产生第一电压。响应于第一电压产生第三电流。第一个电流与第三个电流相加并施加到第二个负载以产生单端信号。

7. 发明授权

US5534802A Sample and hold circuitry in bipolar transistor technology using a bootstrapping technique 失效
标题翻译：采用自举技术的双极晶体管技术中的采样和保持电路
公开(公告)号：US5534802A
公开(公告)日：1996-07-09
申请号：US299724
申请日：1994-09-01
申请人： Behzad Razavi
发明人： Behzad Razavi
IPC分类号： G06F3/05 , G11C27/02 , H03K19/082 , H03M1/12
CPC分类号： G11C27/024
摘要： A sample-and-hold circuit is formed in bipolar transistor technology with the aid of clocked and complementary-clocked bipolar transistors in combination with a holding capacitor whose output terminal, in going from sample to hold phases of the clock, undergoes change in voltage .DELTA.V equal to the input voltage samples Vin applied to its input terminal during the sample phases (electrical bootstrapping operation). In particular, an input terminal of the holding capacitor is connected to a clocked input voltage device that ensures that, during the sample phases, the input voltage applied to the input terminal of the capacitor represents the input voltage being sampled, and that during the hold phases of the clock, the input terminal of the capacitor is electrically clamped. An output terminal of the holding capacitor is connected to one of the clocked transistors and to an auxiliary bipolar transistor whose base terminal is controlled by a complementary-clocked voltage-dropping device. This complementary-clocked voltage-dropping device sets the output terminal of the capacitor to a fixed voltage during the sample phases and is disconnected from this output terminal during the hold phases, whereby during the hold phases the output terminal of the holding capacitor is electrically floating and the voltage thereat represents the input voltage during the immediately preceding sample phase.
摘要翻译：采用双极型晶体管技术，采用时钟和互补时钟的双极型晶体管与保持电容相结合形成采样保持电路，保持电容的输出端从时钟的采样到保持相位经历电压变化DELTA V等于在采样阶段（电自举操作）期间施加到其输入端的输入电压采样Vin。特别地，保持电容器的输入端子连接到时钟输入电压装置，其确保在采样相位期间施加到电容器的输入端子的输入电压表示正在被采样的输入电压，以及在保持期间的输入电压时钟的相位，电容器的输入端子被电气钳位。保持电容器的输出端连接到时钟晶体管之一和辅助双极晶体管，其基极由互补时钟降压器控制。这种互补时钟降压装置在采样相位期间将电容器的输出端子设置为固定电压，并且在保持阶段期间与该输出端子断开连接，由此在保持阶段期间，保持电容器的输出端子电浮动并且其上的电压表示紧接在前的采样相位期间的输入电压。

8. 发明授权

US06947720B2 Low noise mixer circuit with improved gain 失效
标题翻译：具有改善增益的低噪声混频器电路
公开(公告)号：US06947720B2
公开(公告)日：2005-09-20
申请号：US09847866
申请日：2001-05-02
申请人： Behzad Razavi , Pengfei Zhang
发明人： Behzad Razavi , Pengfei Zhang
IPC分类号： H03D7/14 , H04B1/28
CPC分类号： H03D7/1441 , H03D7/1433 , H03D2200/0025 , H03D2200/0033 , H03D2200/0043 , H03D2200/0084
摘要： A mixer circuit of the present invention includes a gain stage configured to receive a first signal and a modulated bias current, and in accordance therewith, produce an output signal, the gain stage generating a first current and receiving the modulated bias current from a bias circuit on a common node. The bias circuit includes an input configured to receive a second signal, and in accordance therewith, generate the modulated bias current. The mixer circuit also includes a current shunt circuit for generating a second current. The first current, the second current, and the modulated bias current are coupled to the common node. In one embodiment, the first signal is approximately a square wave, and the frequency of the first signal is one-third the frequency of the second signal.
摘要翻译：本发明的混频器电路包括：增益级，被配置为接收第一信号和调制偏置电流，并且根据其产生输出信号，增益级产生第一电流并从偏置电路接收经调制的偏置电流在公共节点上。偏置电路包括被配置为接收第二信号的输入，并且根据其产生调制的偏置电流。混频器电路还包括用于产生第二电流的电流分路电路。第一电流，第二电流和调制偏置电流耦合到公共节点。在一个实施例中，第一信号近似为方波，第一信号的频率是第二信号频率的三分之一。

9. 发明授权

US06850749B2 Local oscillator architecture to reduce transmitter pulling effect and minimize unwanted sideband 有权
标题翻译：本地振荡器架构可减少发射机的拉动效应，并尽量减少不必要的边带
公开(公告)号：US06850749B2
公开(公告)日：2005-02-01
申请号：US10113846
申请日：2002-03-27
申请人： Chet Soorapanth , Behzad Razavi , Pengfei Zhang
发明人： Chet Soorapanth , Behzad Razavi , Pengfei Zhang
IPC分类号： H03B5/12 , H03B21/01 , H03B27/00 , H04B1/26
CPC分类号： H03B27/00 , H03B5/1209 , H03B5/1228 , H03B21/01 , H03B2200/0078
摘要： A local oscillator architecture provides a signal at an output frequency with reduced pulling effect. A voltage controlled oscillator (VCO) generates a first signal having a frequency that is a fraction of the output frequency. A frequency shifter generates a second signal with a frequency substantially equal to the difference between the VCO frequency and the output frequency. Single-sideband mixers are used to produce output signals at the sum of the VCO frequency and the shifted frequency while suppressing an unwanted sideband at the difference of the two frequencies.
摘要翻译：本地振荡器架构以输出频率提供信号，具有减小的拉动效果。压控振荡器（VCO）产生具有小于输出频率的频率的第一信号。频移器产生频率基本上等于VCO频率与输出频率之差的第二信号。单边带混频器用于以VCO频率和移位频率之和产生输出信号，同时抑制两个频率差的不需要的边带。

10. 发明授权

US5574405A Low noise amplifier/mixer/frequency synthesizer circuit for an RF system 失效
标题翻译：用于射频系统的低噪声放大器/混频器/频率合成器电路
公开(公告)号：US5574405A
公开(公告)日：1996-11-12
申请号：US517935
申请日：1995-08-22
申请人： Behzad Razavi
发明人： Behzad Razavi
IPC分类号： H03L7/18 , H03D7/00 , H03F3/189 , H03K3/354 , H04B1/26 , H03B5/24 , H03L7/07
CPC分类号： H03D7/00 , H04B1/26
摘要： A low noise amplifier (LNA)/mixer/frequency synthesizer circuit for the front end of a RF system. The LNA/mixer/frequency synthesizer circuit is fabricated as an integrated circuit utilizing 0.6 .mu.M CMOS technologies. The LNA within the circuit is provided a bias current from a power supply. Due to the CMOS construction of the LNA, a significant amount of unused power is available within the LNA. The frequency synthesizer requires the same bias current as does the LNA. The frequency synthesizer is directly coupled to the LNA, wherein the unused bias current of the LNA is used to supply the required bias current to the oscillators within the frequency synthesizer. Since the bias current used by the frequency synthesizer is drawn from the surplus of the LNA, a RF system front end is provided that has greatly reduced power requirements. The LNA is coupled to the frequency synthesizer, via an inductor. The inductor provides resonance to a node between the LNA and the frequency synthesizer that joins to the mixer. The inductor suppresses band harmonics while preserving the unused bias current.
摘要翻译：用于RF系统前端的低噪声放大器（LNA）/混频器/频率合成器电路。 LNA /混频器/频率合成器电路被制造为使用0.6微米CMOS技术的集成电路。电路内的LNA提供来自电源的偏置电流。由于LNA的CMOS结构，在LNA中有大量未使用的功率。频率合成器需要与LNA相同的偏置电流。频率合成器直接耦合到LNA，其中LNA的未使用的偏置电流用于将所需的偏置电流提供给频率合成器内的振荡器。由于频率合成器所使用的偏置电流来自LNA的剩余部分，所以提供了大大降低功率需求的RF系统前端。 LNA通过电感耦合到频率合成器。电感器为连接到混频器的LNA和频率合成器之间的节点提供谐振。电感器抑制频带谐波，同时保持未使用的偏置电流。

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