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1. 发明授权

US07986726B2 CMOS transceiver for communication system 有权
标题翻译： CMOS收发器用于通信系统
公开(公告)号：US07986726B2
公开(公告)日：2011-07-26
申请号：US11267829
申请日：2005-11-03
申请人： Behzad Razavi , Han-Chang Kang , Turgut Aytur , Ran Yan
发明人： Behzad Razavi , Han-Chang Kang , Turgut Aytur , Ran Yan
IPC分类号： H04B1/38
CPC分类号： H04B1/7163 , H04B1/7136 , H04B1/71635 , H04B1/71637 , H04B2001/71362
摘要： A direct conversion ultrawideband transceiver employing three phase locked loops (PLLs). The PLLs are preferably fixed-frequency PLLs that operate continuously, at different frequencies, with a selected frequency determined by selecting the output of one of the three PLLs. The use of three PLLs is suitable for use in a communication system employing frequency hopping across three bands or sub-bands.
摘要翻译：采用三个锁相环（PLL）的直接转换超宽带收发器。 PLL优选地是以不同频率连续工作的固定频率PLL，选择的频率是通过选择三个PLL之一的输出来确定的。使用三个PLL适用于在三个频带或子频带上采用跳频的通信系统。

2. 发明授权

US07336114B2 High-speed latching technique and application to frequency dividers 有权
标题翻译：高速锁存技术和应用于分频器
公开(公告)号：US07336114B2
公开(公告)日：2008-02-26
申请号：US11398278
申请日：2006-04-05
申请人： Behzad Razavi , Zaw Min Soe
发明人： Behzad Razavi , Zaw Min Soe
IPC分类号： H03K3/00
CPC分类号： H03K3/012 , H03K3/356043
摘要： The inventive technique can dynamically adjust the current being applied within the components of a prescaler or divider. This dynamic scaling of the current can improve the speed of the divider by a factor of two or reduce the average current in half when compared to the conventional prescaler. Inverters are used to directly adjust the dynamic value of the currents. The removal of the conventional NMOS device within the conventional circuit eliminates one gate delay in the CML prescaler. Second, the inventive prescaler circuits operate under a current injection/extraction technique. A group of small matched inverters can be used to drive each current switching circuit independently within the entire prescaler as compared to a large buffer driving the entire conventional prescaler. Finally, dynamic current scaling offers the designer additional flexibility in the design trade off between the maximum current applied to the load and achieving the maximum performance.
摘要翻译：本发明的技术可以动态地调节在预分频器或分频器的组件内施加的电流。电流的这种动态缩放可以将分频器的速度提高一倍，或者将传统的预分频器的平均电流减小一半。逆变器用于直接调整电流的动态值。常规电路中的常规NMOS器件的去除消除了CML预分频器中的一个门延迟。第二，本发明的预分频器电路在当前的注入/提取技术下工作。与驱动整个常规预分频器的大型缓冲器相比，一组小型匹配的反相器可以在整个预分频器内单独驱动每个电流开关电路。最后，动态电流扩展为设计人员提供了额外的灵活性，可以在施加到负载的最大电流和实现最大性能之间进行折衷。

3. 发明申请

US20070155348A1 Apparatus and method for ultra wide band architectures 审中-公开
标题翻译：超宽带架构的装置和方法
公开(公告)号：US20070155348A1
公开(公告)日：2007-07-05
申请号：US11321348
申请日：2005-12-29
申请人： Behzad Razavi , Zaw Soe
发明人： Behzad Razavi , Zaw Soe
IPC分类号： H04B1/04
CPC分类号： H04B1/719 , H04B1/71635
摘要： The present invention describes a transmitter/receiver architecture that uses a Weaver architecture in conjunction with digitally controlled adder/subtractor components to insert/extract a signal into/from the multi-channel system. In the transmitter, the selection of the band select bit causes the up/downconverted IF baseband I and Q signals to insert/extract on either side of an RF LO signal. In addition, the image of the first LO is eliminated while the desired signal is enhanced after passing through this new architecture. The invention also adds an RSSI circuit to the MBOA Weaver architecture receiver architecture to detect whether an 802.11 WLAN signal is interfering with the desired UWB signal. If so, the system is designed to detect this interference and jump to a new frequency range to avoid this interference. This invention focuses on devices that operate over the entire UWB band including the newly formed 60 GHz UWB band system.
摘要翻译：本发明描述了一种使用Weaver架构结合数字控制的加法器/减法器组件来将信号插入/从多通道系统中提取的发射机/接收机体系结构。在发射机中，频带选择位的选择会导致上/下转换的IF基带I和Q信号在RF LO信号的任一侧插入/提取。另外，消除了第一个LO的图像，同时在通过这个新架构之后增强了所需的信号。本发明还向MBOA Weaver架构接收机架构添加了RSSI电路，以检测802.11 WLAN信号是否干扰所需的UWB信号。如果是这样，系统被设计为检测这种干扰并跳转到新的频率范围以避免这种干扰。本发明专注于在包括新形成的60GHz UWB频带系统的整个UWB频带上工作的设备。

4. 发明申请

US20060103473A1 Ultrawideband CMOS transceiver 有权
标题翻译：超宽带CMOS收发器
公开(公告)号：US20060103473A1
公开(公告)日：2006-05-18
申请号：US11267829
申请日：2005-11-03
申请人： Behzad Razavi , Han-Chang Kang , Turgut Aytur , Ran Yan
发明人： Behzad Razavi , Han-Chang Kang , Turgut Aytur , Ran Yan
IPC分类号： H03L7/00
CPC分类号： H04B1/7163 , H04B1/7136 , H04B1/71635 , H04B1/71637 , H04B2001/71362
摘要： A direct conversion ultrawideband transceiver employing three phase locked loops (PLLs). The PLLs are preferably fixed-frequency PLLs that operate continuously, at different frequencies, with a selected frequency determined by selecting the output of one of the three PLLs. The use of three PLLs is suitable for use in a communication system employing frequency hopping across three bands or sub-bands.
摘要翻译：采用三个锁相环（PLL）的直接转换超宽带收发器。 PLL优选地是以不同频率连续工作的固定频率PLL，选择的频率是通过选择三个PLL之一的输出来确定的。使用三个PLL适用于在三个频带或子频带上采用跳频的通信系统。

5. 发明申请

US20060066410A1 LOW NOISE AMPLIFIER AND RELATED METHOD 有权
标题翻译：低噪声放大器及相关方法
公开(公告)号：US20060066410A1
公开(公告)日：2006-03-30
申请号：US10711538
申请日：2004-09-24
申请人： Behzad Razavi , Han-Chang Kang
发明人： Behzad Razavi , Han-Chang Kang
IPC分类号： H03F3/191
CPC分类号： H03F3/189 , H03F2200/294 , H03F2200/372
摘要： A low noise amplifier (LNA) for filtering an input signal to generate an output signal. The low noise amplifier includes a switched loading circuit having a plurality of loading units, each of the loading units determining a corresponding center frequency of the low noise amplifier. The switched loading circuit selectively enables a loading unit having the desired corresponding center frequency. At least one converters coupled to the switched loading circuit converts a voltage of the input signal into a loading current and passes the loading current through the enabled loading unit to generate the output signal.
摘要翻译：用于滤波输入信号以产生输出信号的低噪声放大器（LNA）。低噪声放大器包括具有多个加载单元的开关加载电路，每个加载单元确定低噪声放大器的相应中心频率。开关加载电路选择性地启用具有期望的相应中心频率的装载单元。耦合到开关负载电路的至少一个转换器将输入信号的电压转换为负载电流，并将负载电流传递通过使能的负载单元以产生输出信号。

6. 发明授权

US06807406B1 Variable gain mixer circuit 有权
标题翻译：可变增益混频器电路
公开(公告)号：US06807406B1
公开(公告)日：2004-10-19
申请号：US09690937
申请日：2000-10-17
申请人： Behzad Razavi , Pengfei Zhang
发明人： Behzad Razavi , Pengfei Zhang
IPC分类号： H04B126
CPC分类号： H03G1/0088 , H03G3/001 , H03G3/3036
摘要： In accordance with embodiments of the present invention, a receiver system is provided with a variable gain mixer circuit that is advantageous over current architectures used in wireless communication systems. The use of a variable gain mixer circuit simplifies the receiver architecture resulting in the elimination of additional circuit blocks and a reduction in complexity and cost. Moreover, one embodiment of the present invention includes a mixer circuit comprising a mixer core, a bias circuit coupled to the mixer core for providing a bias current, and a variable impedance network. The mixer core receives input signals and generates output currents that are coupled to the variable impedance network. Each of the output currents are selectively coupled to a voltage output node through a variable impedance. Variable gain is established by varying the impedance between the output currents of the mixer core and the voltage output node.
摘要翻译：根据本发明的实施例，接收机系统设置有可变增益混频器电路，其优于无线通信系统中使用的现有架构。使用可变增益混频器电路简化了接收器架构，从而消除了额外的电路块并降低了复杂性和成本。此外，本发明的一个实施例包括混频器电路，该混频器电路包括混频器核心，耦合到用于提供偏置电流的混频器核心的偏置电路以及可变阻抗网络。混频器核心接收输入信号并产生耦合到可变阻抗网络的输出电流。每个输出电流通过可变阻抗选择性地耦合到电压输出节点。通过改变混频器核心的输出电流和电压输出节点之间的阻抗来建立可变增益。

7. 发明授权

US06509777B2 Method and apparatus for reducing DC offset 有权
标题翻译：降低直流偏移的方法和装置
公开(公告)号：US06509777B2
公开(公告)日：2003-01-21
申请号：US09768841
申请日：2001-01-23
申请人： Behzad Razavi , Pengfei Zhang
发明人： Behzad Razavi , Pengfei Zhang
IPC分类号： H03L500
CPC分类号： H03D3/008 , H03F3/45753 , H03F2200/294 , H03F2200/372 , H04B1/30
摘要： Various circuits and methods provide for dc offset reduction that is effective under varying circuit and signal conditions. The offset signal is first sampled and stored, and then subtracted from the signal path via a programmable transconductance amplifier that is placed in a feedback loop during offset reduction. By designing the transconductance amplifier to have programmable gain, the offset reduction technique is capable of compensating for variations in the magnitude of the offset signal. In one embodiment, an amplifier is placed in the feedback path in series with the programmable transconductance amplifier to optimize the trade off between noise and accuracy of offset reduction.
摘要翻译：各种电路和方法提供在变化的电路和信号条件下有效的直流偏移减小。首先对偏移信号进行采样和存储，然后经由可编程跨导放大器从信号路径中减去，该放大器在偏移减小期间放置在反馈环路中。通过将跨导放大器设计为具有可编程增益，偏移降低技术能够补偿偏移信号幅度的变化。在一个实施例中，将放大器放置在与可编程跨导放大器串联的反馈路径中，以优化噪声和偏移减小精度之间的折衷。

8. 发明授权

US07528357B2 Pulse detector which employs a self-resetting pulse amplifier 失效
标题翻译：采用自复位脉冲放大器的脉冲检测器
公开(公告)号：US07528357B2
公开(公告)日：2009-05-05
申请号：US11407376
申请日：2006-04-19
申请人： Behzad Razavi , Lawrence C. West , Bryan D. Ackland
发明人： Behzad Razavi , Lawrence C. West , Bryan D. Ackland
IPC分类号： H03G3/20
CPC分类号： H01L27/144 , H03F3/08 , H03K5/1534 , H04B10/66
摘要： A circuit including: an optical detector for detecting an optical pulse and generating therefrom a current pulse on an output; a pulse detector circuit having an input electrically connected to the optical detector and having an output for outputting a detection pulse in response to detecting the current pulse on its input, said pulse detector circuit including: a resettable amplifier including an input for receiving the current pulse from the optical detector, a reset terminal for resetting the amplifier after the amplifier detects the current pulse on its input, and an output for outputting a signal from which the detection pulse is derived; and a reset delay chain feeding back to the reset terminal of the resettable amplifier a feedback signal derived from the output signal of the resettable amplifier.
摘要翻译：一种电路，包括：光检测器，用于检测光脉冲并产生输出上的电流脉冲; 脉冲检测器电路，其具有电连接到所述光学检测器的输入端，并具有用于响应于检测其输入上的电流脉冲而输出检测脉冲的输出，所述脉冲检测器电路包括：可复位放大器，包括用于接收电流脉冲的输入来自光检测器的复位端子，用于在放大器检测到其输入上的电流脉冲之后复位放大器，以及用于输出用于输出检测脉冲的信号的输出; 以及复位延迟链，其将可重置放大器的输出信号导出的反馈信号反馈到可复位放大器的复位端。

9. 发明申请

US20070236267A1 High-speed latching technique and application to frequency dividers 有权
标题翻译：高速锁存技术和应用于分频器
公开(公告)号：US20070236267A1
公开(公告)日：2007-10-11
申请号：US11398278
申请日：2006-04-05
申请人： Behzad Razavi , Zaw Soe
发明人： Behzad Razavi , Zaw Soe
IPC分类号： H03K3/00
CPC分类号： H03K3/012 , H03K3/356043
摘要： The inventive technique can dynamically adjust the current being applied within the components of a prescaler or divider. This dynamic scaling of the current can improve the speed of the divider by a factor of two or reduce the average current in half when compared to the conventional prescaler. Inverters are used to directly adjust the dynamic value of the currents. The removal of the conventional NMOS device within the conventional circuit eliminates one gate delay in the CML prescaler. Second, the inventive prescaler circuits operate under a current injection/extraction technique. A group of small matched inverters can be used to drive each current switching circuit independently within the entire prescaler as compared to a large buffer driving the entire conventional prescaler. Finally, dynamic current scaling offers the designer additional flexibility in the design trade off between the maximum current applied to the load and achieving the maximum performance.
摘要翻译：本发明的技术可以动态地调节在预分频器或分频器的组件内施加的电流。电流的这种动态缩放可以将分频器的速度提高一倍，或者将传统的预分频器的平均电流减小一半。逆变器用于直接调整电流的动态值。常规电路中的常规NMOS器件的去除消除了CML预分频器中的一个门延迟。第二，本发明的预分频器电路在当前的注入/提取技术下工作。与驱动整个常规预分频器的大型缓冲器相比，一组小型匹配的反相器可以在整个预分频器内单独驱动每个电流开关电路。最后，动态电流扩展为设计人员提供了额外的灵活性，可以在施加到负载的最大电流和实现最大性能之间进行折衷。

10. 发明授权

US07149128B2 Data latch 有权
标题翻译：数据锁存
公开(公告)号：US07149128B2
公开(公告)日：2006-12-12
申请号：US10904567
申请日：2004-11-16
申请人： Behzad Razavi , Han-Chang Kang
发明人： Behzad Razavi , Han-Chang Kang
IPC分类号： G11C7/10
CPC分类号： H03K3/356104 , H03K3/012
摘要： A high-speed latch includes a latch unit and a first current source. The latch unit has a first input terminal for receiving a first input signal and a first output terminal for outputting a first output signal. The first current source is coupled to the first output terminal, and is enabled for providing the first output terminal with a first driving current to reduce a voltage difference between the first output signal and the first input signal when the first output signal and the first input signal correspond to different logic states.
摘要翻译：高速锁存器包括锁存单元和第一电流源。锁存单元具有用于接收第一输入信号的第一输入端和用于输出第一输出信号的第一输出端。第一电流源耦合到第一输出端，并且使得第一输出端能够提供第一驱动电流，以在第一输出信号和第一输入信号之间减小第一输出信号和第一输入信号之间的电压差信号对应于不同的逻辑状态。

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