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1. 发明申请

US20120275543A1 SELECTIVE PEAK POWER REDUCTION 有权
标题翻译：选择峰值功率降低
公开(公告)号：US20120275543A1
公开(公告)日：2012-11-01
申请号：US13541348
申请日：2012-07-03
申请人： Bradley John Morris , Arthur Thomas Gerald Fuller
发明人： Bradley John Morris , Arthur Thomas Gerald Fuller
IPC分类号： H04L25/49
CPC分类号： H04L25/49 , H04L27/2624
摘要： A communication system comprising signal processing circuitry and up-conversion circuitry. The signal processing circuitry is configured to: i) generate a first signal of a first modulation type and a second signal of a second modulation type; ii) combine the first and second signals to form a combined input signal; iii) generate peak reduction distortion based on the combined input signal; iv) select a portion of the peak reduction distortion that corresponds to a first frequency band; and v) apply the selected portion of the peak reduction distortion in the first frequency band of the combined input signal to provide a combined output signal. The up-conversion circuitry up-converts the combined output signal to an RF signal for transmission.
摘要翻译：一种包括信号处理电路和上转换电路的通信系统。信号处理电路被配置为：i）产生第一调制类型的第一信号和第二调制类型的第二信号; ii）组合第一和第二信号以形成组合的输入信号; iii）基于组合的输入信号产生峰值减小失真; iv）选择对应于第一频带的峰值减小失真的一部分; 以及v）将组合输入信号的第一频带中的峰值减小失真的选定部分应用于组合输出信号。上变频电路将组合输出信号上变频为RF信号进行传输。

2. 发明授权

US07095278B2 Power amplifier arrangement and method for memory correction/linearization 有权
标题翻译：用于存储器校正/线性化的功率放大器布置和方法
公开(公告)号：US07095278B2
公开(公告)日：2006-08-22
申请号：US10900300
申请日：2004-07-28
申请人： Arthur Thomas Gerald Fuller , Bradley John Morris
发明人： Arthur Thomas Gerald Fuller , Bradley John Morris
IPC分类号： H03F1/26
CPC分类号： H03F1/0211 , H03F1/3258 , H03F2200/102
摘要： A device, system, and method are provided for a power amplifier arrangement. In embodiments of a Vdd modulated power amplifier arrangement, a memory correction block includes a Vdd predictor for predicting waveform distortions of a Vdd modulated power supply and a main-path corrector for pre-distorting the input to the power amplifier arrangement as a function of the input to the power amplifier arrangement, an input envelope signal determined as a function of the input to the power amplifier arrangement, and an output of the Vdd predictor. Embodiments of the invention provide for operating power amplifier arrangements having memory. In some embodiments, methods of training the Vdd predictor and the main-path corrector of the memory correction block are provided.
摘要翻译：提供了用于功率放大器装置的装置，系统和方法。在Vdd调制功率放大器装置的实施例中，存储器校正块包括用于预测Vdd调制电源的波形失真的Vdd预测器和用于将功率放大器装置的输入预失真的主路径校正器作为输入到功率放大器装置，确定为功率放大器装置的输入的函数的输入包络信号以及Vdd预测器的输出。本发明的实施例提供具有存储器的操作功率放大器装置。在一些实施例中，提供训练存储器校正块的Vdd预测器和主路径校正器的方法。

3. 发明授权

US06987953B2 Digital transmitter and method 有权
标题翻译：数字发射机和方法
公开(公告)号：US06987953B2
公开(公告)日：2006-01-17
申请号：US10403727
申请日：2003-03-31
申请人： Bradley John Morris , Arthur Thomas Gerald Fuller
发明人： Bradley John Morris , Arthur Thomas Gerald Fuller
IPC分类号： H04B1/02 , H04B1/04
CPC分类号： H04B1/0483
摘要： A transmitter and method is provided for digitally upconverting a baseband digital signal to a modulated intermediate frequency (IF) digital signal and sigma-delta modulating the IF digital signal. The baseband digital signal is split into N phases, as can be accomplished using a polyphase interpolation technique (polyphase filter), and modulated. The modulated N phases are not recombined and each phase is further modulated, as can be accomplished using a digital-to-digital sigma-delta modulator that generates digital output signals at the same rate. A high speed digital multiplexer multiplexes the digital output signals into a single bit stream at a higher rate for subsequent power amplification and RF transmission.
摘要翻译：提供了一种发射机和方法，用于将基带数字信号数字上变频到调制中频（IF）数字信号和Σ-Δ调制IF数字信号。基带数字信号被分为N个阶段，可以使用多相插值技术（多相滤波器）实现并进行调制。调制的N相不被重新组合，并且每个相位被进一步调制，这可以使用以相同速率产生数字输出信号的数字 - 数字Σ-Δ调制器来实现。高速数字多路复用器以更高的速率将数字输出信号复用为单个比特流，用于随后的功率放大和RF传输。

4. 发明授权

US08472562B2 Digital receiver and method 有权
标题翻译：数字接收机和方法
公开(公告)号：US08472562B2
公开(公告)日：2013-06-25
申请号：US13230660
申请日：2011-09-12
申请人： Bradley John Morris , Arthur Thomas Gerald Fuller
发明人： Bradley John Morris , Arthur Thomas Gerald Fuller
IPC分类号： H04L27/00 , H04B1/00
CPC分类号： H04L27/22 , H03M3/462 , H03M3/47 , H03M7/3028 , H04B1/0007
摘要： A receiver and method is provided for sigma-delta converting an RF signal to a digital signal and downconverting to a digital baseband signal. The RF signal is split into N phases, as can be accomplished using a sample and hold circuit, and each phase is digitized, as can be accomplished using an analog-to-digital (A/D) sigma-delta converter. Polyphase decimation techniques and demodulation are applied to the phased signals to generate a demodulated digital signal. The demodulated digital signal is further downconverted to the appropriate baseband signal.
摘要翻译：提供了一种接收机和方法，用于将RF信号转换成数字信号并下变频成数字基带信号。 RF信号被分为N个相位，可以使用采样和保持电路实现，并且每个相位被数字化，如可以使用模数（A / D）Σ-Δ转换器所实现的。将多相抽取技术和解调应用于相控信号以产生解调数字信号。解调的数字信号进一步下变频到适当的基带信号。

5. 发明授权

US08369447B2 Predistortion with sectioned basis functions 有权
标题翻译：预失真与分段基函数
公开(公告)号：US08369447B2
公开(公告)日：2013-02-05
申请号：US12402643
申请日：2009-03-12
申请人： Arthur Thomas Gerald Fuller , Bradley John Morris
发明人： Arthur Thomas Gerald Fuller , Bradley John Morris
IPC分类号： H04K1/02
CPC分类号： H03F1/3247
摘要： A predistortion actuator is provided. The predistortion actuator includes a plurality of branches, each of which implements a basis function that acts on a digital input signal. For at least one of the branches, the respective basis function is a sectioned basis function, where each section of the sectioned basis function corresponds to a respective section of a range of at least one input signal characteristic associated with the digital input signal, such as a value range of a magnitude, a temporal characteristic, or a hybrid of the two. A power amplifier system including the predistortion actuator is also provided. Utilizing sectioned basis functions can potentially reduce the hardware resources necessary to realize the predistortion actuator relative to conventional global basis functions. In addition, signal conditioning during coefficient training can potentially be used to reduce the dynamic range of coefficients associated with each sectioned basis function.
摘要翻译：提供一个预失真执行器。预失真致动器包括多个分支，每个分支执行作用于数字输入信号的基函数。对于至少一个分支，相应的基本函数是分段基函数，其中分段基函数的每个部分对应于与数字输入信号相关联的至少一个输入信号特性的范围的相应部分，诸如大小，时间特征或两者的混合的值范围。还提供了包括预失真致动器的功率放大器系统。利用分段基函数可以潜在地减少实现预失真执行器相对于常规全局基函数所需的硬件资源。此外，在系数训练期间的信号调节可潜在地用于减少与每个分段基函数相关联的系数的动态范围。

6. 发明授权

US08358680B2 Reducing power levels associated with two or more signals using peak reduction distortion that is derived from a combined signal 有权
标题翻译：使用从组合信号导出的峰值降低失真降低与两个或更多个信号相关联的功率电平
公开(公告)号：US08358680B2
公开(公告)日：2013-01-22
申请号：US12343221
申请日：2008-12-23
申请人： Bradley John Morris , Arthur Thomas Gerald Fuller
发明人： Bradley John Morris , Arthur Thomas Gerald Fuller
IPC分类号： H04K1/10 , H04L27/28
CPC分类号： H04B1/0475 , H03F1/3241 , H03F3/195 , H03F3/211 , H03F3/245 , H03F3/68 , H04L27/2614
摘要： The present invention provides a technique for reducing power levels associated with two or more input signals using peak reduction distortion that is derived from a combined signal, which represents a combination of the input signals.
摘要翻译：本发明提供了一种用于使用从表示输入信号的组合的组合信号导出的峰值减小失真来降低与两个或更多个输入信号相关联的功率电平的技术。

7. 发明申请

US20120057654A1 SELECTIVE PEAK POWER REDUCTION 有权
标题翻译：选择峰值功率降低
公开(公告)号：US20120057654A1
公开(公告)日：2012-03-08
申请号：US13291481
申请日：2011-11-08
申请人： Bradley John Morris , Arthur Thomas Gerald Fuller
发明人： Bradley John Morris , Arthur Thomas Gerald Fuller
IPC分类号： H04B15/00
CPC分类号： H04L25/49 , H04L27/2624
摘要： The present invention provides a technique for reducing the peak power of a combined signal that has a first signal of a first modulation type and a second signal of a second modulation type. Based on the combined signal, peak reduction distortion is determined. The peak reduction distortion is configured such that, if applied to the entirety of the combined signal, excessive peaks throughout the combined signal would be reduced. However, instead of applying the entirety of the peak reduction distortion, a selected portion of the peak reduction distortion is applied to a corresponding portion of the combined signal to reduce the peak power of the combined signal.
摘要翻译：本发明提供一种用于降低具有第一调制类型的第一信号和第二调制类型的第二信号的组合信号的峰值功率的技术。基于组合信号，确定峰值减小失真。峰值降低失真被配置为使得如果应用于整个组合信号，则整个组合信号中的过多峰值将被减小。然而，代替应用峰值降低失真的全部，代替峰值减小失真的选定部分被施加到组合信号的相应部分，以降低组合信号的峰值功率。

8. 发明授权

US07176820B1 Multiple input sigma-delta architecture 有权
标题翻译：多输入Σ-Δ架构
公开(公告)号：US07176820B1
公开(公告)日：2007-02-13
申请号：US11235946
申请日：2005-09-27
申请人： Arthur Thomas Gerald Fuller , Bradley John Morris
发明人： Arthur Thomas Gerald Fuller , Bradley John Morris
IPC分类号： H03M3/00
CPC分类号： H03M3/47 , H03M3/50
摘要： A number of parallel modulation functions are configured to provide sigma-delta modulation on a plurality of low sampling rate signals, which are representative of a high sampling rate input signal. Resultant sigma-delta modulated signals from each of the modulation functions are combined in a multiplexing fashion to create a high sampling rate output signal. The modulation functions may be interdependent, wherein error signals from the modulation functions are provided to a parallel block digital filter, which will provide a processed error signal to feed back into the input of each modulation function. The processed error signal for a given modulation function may be a function of the error signals derived from multiple ones of the modulation functions. In one embodiment, there are N modulation functions, and the operating rate of the modulation functions is fs/N wherein the sampling rate of the high frequency output signal is fs.
摘要翻译：多个并行调制功能被配置为在代表高采样率输入信号的多个低采样率信号上提供Σ-Δ调制。来自每个调制功能的所得到的Σ-Δ调制信号以多路复用方式组合以产生高采样率输出信号。调制函数可以是相互依赖的，其中来自调制功能的误差信号被提供给并行块数字滤波器，其将提供经处理的误差信号以反馈到每个调制功能的输入。用于给定调制函数的经处理的误差信号可以是从多个调制函数导出的误差信号的函数。在一个实施例中，存在N个调制功能，并且调制功能的工作速率为f N S / N，其中高频输出信号的采样速率为f N s / 。

9. 发明授权

US07081793B2 High-efficiency amplifier, converter and methods 失效
标题翻译：高效放大器，转换器及方法
公开(公告)号：US07081793B2
公开(公告)日：2006-07-25
申请号：US10858079
申请日：2004-06-02
申请人： Bradley John Morris , Arthur Thomas Gerald Fuller , Russell Smiley
发明人： Bradley John Morris , Arthur Thomas Gerald Fuller , Russell Smiley
IPC分类号： H03F3/38
CPC分类号： H03F3/2178 , H03F1/0205 , H03F1/0211 , H03F1/0227 , H03F1/08 , H03F3/211 , H03F3/217 , H03F3/2175 , H03F2200/331 , H03F2200/504
摘要： Methods and apparatus are provided for efficiently amplifying or converting a signal. An input signal is decomposed into a plurality of two state signals, each two state signal having a respective on level and off level. This may involve sigma-delta modulation and phase splitting. For amplifier applications, each of the two state signals is amplified with a respective switching power amplifier to produce a respective amplified signal. The amplified signals are combined to produce an amplified version of the input signal. Signals may be adjusted for impairments associated with a subsequent processing operation such as the combining.
摘要翻译：提供了用于有效地放大或转换信号的方法和装置。输入信号被分解为多个两个状态信号，每个两个状态信号具有相应的开启和关闭电平。这可能涉及Σ-Δ调制和相位分离。对于放大器应用，两个状态信号中的每一个用相应的开关功率放大器放大以产生相应的放大信号。放大的信号被组合以产生输入信号的放大版本。可以针对与诸如组合的后续处理操作相关联的损伤来调整信号。

10. 发明申请

US20120281793A1 CORDIC Based Complex Tuner with Exact Frequency Resolution 有权
标题翻译：基于CORDIC的复合调谐器，具有精确的频率分辨率
公开(公告)号：US20120281793A1
公开(公告)日：2012-11-08
申请号：US13550975
申请日：2012-07-17
申请人： Arthur Thomas Gerald Fuller , Bradley John Morris
发明人： Arthur Thomas Gerald Fuller , Bradley John Morris
IPC分类号： H04B1/06
CPC分类号： H04L27/0014
摘要： Systems and methods are disclosed that include selecting a sampling frequency and a tuning resolution frequency. These systems and methods may further include determining a wordlength of the phase accumulator, a numeric representation of the phase range, and a reduced representable value of a phase accumulator. In addition, these systems and methods may include operating the phase accumulator, where the phase accumulator creates an output phase accumulator signal. These systems and methods may further includes adjusting the angle of the output phase accumulator signal, where the output phase accumulator signal is adjusted based upon the operation of the phase accumulator, where adjusting the angle of the output phase accumulator signal creates an adjusted output phase accumulator signal and operating a CORDIC module, and where the CORDIC module performs operations upon the output phase accumulator signal based upon the parameters of the phase accumulator.
摘要翻译：公开了包括选择采样频率和调谐分辨率频率的系统和方法。这些系统和方法还可以包括确定相位累加器的字长，相位范围的数值表示以及相位累加器的可表示的值。此外，这些系统和方法可以包括操作相位累加器，其中相位累加器产生输出相位累加器信号。这些系统和方法还可以包括调整输出相位累加器信号的角度，其中基于相位累加器的操作来调节输出相位累加器信号，其中调节输出相位累加器信号的角度产生调整的输出相位累加器信号和操作CORDIC模块，并且其中CORDIC模块基于相位累加器的参数在输出相位累加器信号上执行操作。

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