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1. 发明授权

US09438418B1 Systems and methods for generating a key difficult to clone 有权
标题翻译：用于生成难以克隆的密钥的系统和方法
公开(公告)号：US09438418B1
公开(公告)日：2016-09-06
申请号：US13102673
申请日：2011-05-06
申请人： Bruce B. Pedersen , Ninh D. Ngo
发明人： Bruce B. Pedersen , Ninh D. Ngo
IPC分类号： H04L9/08 , H04L29/06 , H04L9/14
CPC分类号： H04L9/0861 , G09C1/00 , H04L9/14 , H04L9/3239 , H04L63/0478 , H04L63/06
摘要： Systems and methods relating to generating a key that is difficult to clone are described. The methods include receiving a programmable logic device (PLD) with a first key and applying a one-way hash function to a second key or the first key and the second key to create a third key. The application of the one-way hash function is performed using one or more components hardwired into the PLD. The methods further include storing the third key in the PLD only after using the one or more components to apply the one-way hash function.
摘要翻译：描述与生成难以克隆的密钥有关的系统和方法。所述方法包括用第一密钥接收可编程逻辑器件（PLD），并将单向散列函数应用于第二密钥或第一密钥和第二密钥以创建第三密钥。单向散列函数的应用使用硬连线到PLD中的一个或多个组件来执行。所述方法还包括仅在使用所述一个或多个组件来应用所述单向散列函数之后将所述第三密钥存储在所述PLD中。

2. 发明授权

US09331848B1 Differential power analysis resistant encryption and decryption functions 有权
标题翻译：差分功率分析抵抗加密和解密功能
公开(公告)号：US09331848B1
公开(公告)日：2016-05-03
申请号：US13098315
申请日：2011-04-29
申请人： Bruce B. Pedersen
发明人： Bruce B. Pedersen
IPC分类号： H04L9/00 , H04L9/06
CPC分类号： H04L9/0631 , G09C1/00 , H04L9/003 , H04L9/0637 , H04L2209/04
摘要： Circuits, methods, and systems are provided for securing an integrated circuit device against Differential Power Analysis (DPA) attacks. Plaintext (e.g., configuration data for a programmable device) may be encrypted in an encryption system using a cryptographic algorithm. Ciphertext may be decrypted in a decryption system using the cryptographic algorithm. The encryption and/or decryption systems may obfuscate the plaintext, the ciphertext, and/or the substitution tables used by the cryptographic algorithm. The encryption and/or decryption systems may also generate cryptographic key schedules by using different keys for encrypting/decrypting different blocks and/or by expanding round keys between encryption/decryption blocks. These techniques may help mitigate or altogether eliminate the vulnerability of cryptographic elements revealing power consumption information to learn the value of secret information, e.g., through DPA.
摘要翻译：提供了电路，方法和系统，用于保护集成电路设备免受差分功耗分析（DPA）攻击。可以使用加密算法在加密系统中加密明文（例如，可编程设备的配置数据）。可以在使用密码算法的解密系统中解密密文。加密和/或解密系统可能会混淆密码算法使用的明文，密文和/或替换表。加密和/或解密系统还可以通过使用用于加密/解密不同块的不同密钥和/或通过在加密/解密块之间扩展循环密钥来生成加密密钥调度。这些技术可以有助于减轻或完全消除揭示功耗信息的密码元件的漏洞，以便学习秘密信息的价值，例如通过DPA。

3. 发明授权

US08719957B2 Systems and methods for detecting and mitigating programmable logic device tampering 有权
标题翻译：用于检测和减轻可编程逻辑器件篡改的系统和方法
公开(公告)号：US08719957B2
公开(公告)日：2014-05-06
申请号：US13098074
申请日：2011-04-29
申请人： Bruce B. Pedersen
发明人： Bruce B. Pedersen
IPC分类号： G08B21/00 , G06F12/14
CPC分类号： G06F21/86 , G06F21/76 , H03K19/17768
摘要： Systems and methods are disclosed for preventing tampering of a programmable integrated circuit device. Generally, programmable devices, such as FPGAs, have two stages of operation; a configuration stage and a user mode stage. To prevent tampering and/or reverse engineering of a programmable device, various anti-tampering techniques may be employed during either stage of operation to disable the device and/or erase sensitive information stored on the device once tampering is suspected. One type of tampering involves bombarding the device with a number of false configuration attempts in order to decipher encrypted data. By utilizing a dirty bit and a sticky error counter, the device can keep track of the number of failed configuration attempts that have occurred and initiate anti-tampering operations when tampering is suspected while the device is still in the configuration stage of operation.
摘要翻译：公开了用于防止可编程集成电路器件的篡改的系统和方法。通常，可编程器件（如FPGA）具有两个操作阶段; 配置阶段和用户模式阶段。为了防止可编程设备的篡改和/或反向工程，可以在任何操作阶段中采用各种防篡改技术，以在怀疑篡改之后禁用设备和/或擦除存储在设备上的敏感信息。一种类型的篡改涉及用许多虚假配置尝试来轰炸设备以便解密加密的数据。通过使用脏位和粘性错误计数器，设备可以跟踪发生的失败配置尝试次数，并在设备处于配置阶段怀疑篡改时启动防篡改操作。

4. 发明授权

US08482965B2 Volatile memory elements with soft error upset immunity 有权
标题翻译：易失性记忆元件，具有柔软的错误不耐受性
公开(公告)号：US08482965B2
公开(公告)日：2013-07-09
申请号：US13411436
申请日：2012-03-02
申请人： Bruce B. Pedersen
发明人： Bruce B. Pedersen
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C7/20 , G11C11/4125 , H03K19/00392 , H03K19/177 , H03K19/1776 , H03K19/17764
摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors including two address transistors and four transistor pairs that are interconnected to form a bistable element. Clear lines such as true and complement clear lines may be routed to positive power supply terminals and ground power supply terminals associated with certain transistor pairs. During clear operations, some or all of the transistor pairs can be selectively depowered using the clear lines. This facilitates clear operations in which logic zero values are driven through the address transistors and reduces cross-bar current surges.
摘要翻译：提供了存储元件，当受到高能原子粒子撞击时，表现出对软错误失调事件的抵抗力。存储元件可以各自具有十个晶体管，其包括互连以形成双稳态元件的两个地址晶体管和四个晶体管对。诸如真实和补充清除线之类的清除线可以被路由到与某些晶体管对相关联的正电源端子和接地电源端子。在清除操作期间，可以使用清除线选择性地削弱部分或全部晶体管对。这有助于明确的操作，其中逻辑零值通过地址晶体管驱动并且减小交叉电流浪涌。

5. 发明申请

US20130007679A1 RECONFIGURABLE LOGIC BLOCK 有权
标题翻译：可重构逻辑块
公开(公告)号：US20130007679A1
公开(公告)日：2013-01-03
申请号：US13369226
申请日：2012-02-08
申请人： David W. Mendel , Gary Lai , Lu Zhou , Bruce B. Pedersen
发明人： David W. Mendel , Gary Lai , Lu Zhou , Bruce B. Pedersen
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F11/1008 , H03K19/17756 , H03K19/17776
摘要： A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a data verification process. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state. Moreover, the region of configuration logic may be dynamically reconfigured from one state to another without causing verification errors.
摘要翻译：可编程逻辑器件包括诸如可被配置为随机存取存储器（RAM）或查找表（LUT）的逻辑阵列块（LAB）的逻辑块。提供模式标志以指示诸如在逻辑块的部分重新配置期间使用的配置RAM（CRAM）的配置逻辑的操作模式。提供使能读取标志以指示在数据验证处理期间是否读出存储在配置逻辑中的值或者是否读出已知状态。因此，排除和包含来自数据验证和校正处理的配置逻辑区域的部分允许配置逻辑的区域存储设计状态和用户定义的状态。此外，配置逻辑的区域可以从一个状态被动态地重新配置而不引起验证错误。

6. 发明申请

US20120275077A1 SYSTEMS AND METHODS FOR SECURING A PROGRAMMABLE DEVICE AGAINST AN OVER-VOLTAGE ATTACK 有权
标题翻译：用于安全防止过电压攻击的可编程器件的系统和方法
公开(公告)号：US20120275077A1
公开(公告)日：2012-11-01
申请号：US13097313
申请日：2011-04-29
申请人： Bruce B. Pedersen , Dirk A. Reese
发明人： Bruce B. Pedersen , Dirk A. Reese
IPC分类号： H02H9/04
CPC分类号： G11C7/24 , H03K19/17768
摘要： Systems and methods are disclosed for securing a programmable integrated circuit device against an over-voltage attack. Generally, programmable devices, such as FPGAs, contain volatile memory registers that may store sensitive information. To prevent tampering and/or reverse engineering of such a programmable device, an over-voltage detection circuit may be employed to disable the device and/or erase the sensitive information stored on the device when an over-voltage attack is suspected. In particular, once the over-voltage detection circuit detects that the voltage applied to the programmable device exceeds a trigger voltage, it may cause logic circuitry to erase the sensitive information stored on the device. Desirably, the over-voltage detection circuit includes components arranged in such a way as to render current consumption negligible when the voltage applied to the programmable device, e.g., by a battery, remains below the trigger voltage.
摘要翻译：公开了用于保护可编程集成电路装置免受过电压攻击的系统和方法。通常，可编程器件（如FPGA）包含可能存储敏感信息的易失性存储器寄存器。为了防止这种可编程设备的篡改和/或逆向工程，当怀疑有过电压攻击时，可以采用过电压检测电路来禁止该设备和/或擦除存储在设备上的敏感信息。特别地，一旦过电压检测电路检测到施加到可编程器件的电压超过触发电压，则可能导致逻辑电路擦除存储在器件上的敏感信息。期望地，过电压检测电路包括以下方式布置的组件，即当例如通过电池施加到可编程器件的电压保持低于触发电压时，电流消耗可以忽略不计。

7. 发明申请

US20120163067A1 VOLATILE MEMORY ELEMENTS WITH SOFT ERROR UPSET IMMUNITY 有权
标题翻译：具有软错误UPS易失性的易失性存储器元件
公开(公告)号：US20120163067A1
公开(公告)日：2012-06-28
申请号：US13411436
申请日：2012-03-02
申请人： Bruce B. Pedersen
发明人： Bruce B. Pedersen
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C7/20 , G11C11/4125 , H03K19/00392 , H03K19/177 , H03K19/1776 , H03K19/17764
摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors including two address transistors and four transistor pairs that are interconnected to form a bistable element. Clear lines such as true and complement clear lines may be routed to positive power supply terminals and ground power supply terminals associated with certain transistor pairs. During clear operations, some or all of the transistor pairs can be selectively depowered using the clear lines. This facilitates clear operations in which logic zero values are driven through the address transistors and reduces cross-bar current surges.
摘要翻译：提供了存储元件，当受到高能原子粒子撞击时，表现出对软错误失调事件的抵抗力。存储元件可以各自具有十个晶体管，其包括互连以形成双稳态元件的两个地址晶体管和四个晶体管对。诸如真实和补充清除线之类的清除线可以被路由到与某些晶体管对相关联的正电源端子和接地电源端子。在清除操作期间，可以使用清除线选择性地削弱部分或全部晶体管对。这有助于明确的操作，其中逻辑零值通过地址晶体管驱动并且减小交叉电流浪涌。

8. 发明申请

US20110193593A1 Apparatus for Metastability-Hardened Storage Circuits and Associated Methods 有权
标题翻译：用于转换硬化存储电路的设备及相关方法
公开(公告)号：US20110193593A1
公开(公告)日：2011-08-11
申请号：US13089221
申请日：2011-04-18
申请人： Bruce B. Pedersen , Sivaraman Chokkalingam
发明人： Bruce B. Pedersen , Sivaraman Chokkalingam
IPC分类号： H03K19/00
CPC分类号： H03K3/0375 , H03K3/356121 , H03K3/356139
摘要： A metastability-hardened storage circuit includes at least one inverting circuit. The inverting circuit has a logical input. The logical input of the inverting circuit is split into a pair of physical inputs.
摘要翻译：亚稳态硬化存储电路包括至少一个反相电路。反相电路具有逻辑输入。反相电路的逻辑输入被分成一对物理输入。

9. 发明授权

US07864620B1 Partially reconfigurable memory cell arrays 有权
标题翻译：部分可重新配置的存储单元阵列
公开(公告)号：US07864620B1
公开(公告)日：2011-01-04
申请号：US12407750
申请日：2009-03-19
申请人： Bruce B. Pedersen
发明人： Bruce B. Pedersen
IPC分类号： G11C8/00
CPC分类号： G11C11/413 , G11C7/1006 , G11C7/1012 , G11C2207/002 , H03K19/17752 , H03K19/17756 , H03K19/1776
摘要： Partial reconfiguration techniques and reconfiguration circuitry are provided that allow portions of a memory cell array to be reconfigured with new reconfiguration data without disturbing other portions of the memory cell array. The memory cells may be loaded with configuration data on an integrated circuit such as a programmable logic device. Memory cell outputs may configure programmable logic. To avoid disturbing programmable logic operations for programmable logic that is unaffected by the reconfigured cells during reconfiguration, unaffected memory cells are not unnecessarily cleared. Only those memory cells that need to be cleared to conform to the new configuration data that is being loaded into the array need to be loaded with logic zero values during reconfiguration operations. After these clearing operations are complete, set operations may be performed to convert appropriate memory cells to logic one values to match the new configuration data.
摘要翻译：提供部分重配置技术和重新配置电路，其允许存储单元阵列的部分用新的重配置数据重新配置，而不会干扰存储单元阵列的其他部分。存储器单元可以在诸如可编程逻辑器件的集成电路上加载配置数据。存储单元输出可以配置可编程逻辑。为了避免在重新配置期间不受重新配置的单元影响的可编程逻辑的可编程逻辑操作的干扰，未受影响的存储单元不会被不必要地清除。只有那些需要清除以符合正在加载到阵列中的新配置数据的内存单元需要在重新配置操作期间加载逻辑零值。这些清除操作完成后，可以执行设置操作，将适当的存储单元转换为逻辑一个值，以匹配新的配置数据。

10. 发明申请

US20100238715A1 VOLATILE MEMORY ELEMENTS WITH SOFT ERROR UPSET IMMUNITY 有权
公开(公告)号：US20100238715A1
公开(公告)日：2010-09-23
申请号：US12686597
申请日：2010-01-13
申请人： Bruce B. Pedersen
发明人： Bruce B. Pedersen
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C7/20 , G11C11/4125 , H03K19/00392 , H03K19/177 , H03K19/1776 , H03K19/17764
摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors including two address transistors and four transistor pairs that are interconnected to form a bistable element. Clear lines such as true and complement clear lines may be routed to positive power supply terminals and ground power supply terminals associated with certain transistor pairs. During clear operations, some or all of the transistor pairs can be selectively depowered using the clear lines. This facilitates clear operations in which logic zero values are driven through the address transistors and reduces cross-bar current surges.

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