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1. 发明授权

US07584342B1 Parallel data processing systems and methods using cooperative thread arrays and SIMD instruction issue 有权
标题翻译：并行数据处理系统和方法使用协作线程数组和SIMD指令问题
公开(公告)号：US07584342B1
公开(公告)日：2009-09-01
申请号：US11305479
申请日：2005-12-15
申请人： Bryon S. Nordquist , John R. Nickolls , Luis I. Bacayo
发明人： Bryon S. Nordquist , John R. Nickolls , Luis I. Bacayo
IPC分类号： G06F15/80
CPC分类号： G06F9/52 , G06F9/3851 , G06F9/3887
摘要： Parallel data processing systems and methods use cooperative thread arrays (CTAs), i.e., groups of multiple threads that concurrently execute the same program on an input data set to produce an output data set. Each thread in a CTA has a unique identifier (thread ID) that can be assigned at thread launch time and that controls various aspects of the thread's processing behavior, such as the portion of the input data set to be processed by each thread, the portion of the output data set to be produced by each thread, and/or sharing of intermediate results among threads. Where groups of threads are executed in SIMD parallelism, thread IDs for threads in the same SIMD group are generated and assigned in parallel, allowing different SIMD groups to be launched in rapid succession.
摘要翻译：并行数据处理系统和方法使用协同线程数组（CIA），即在输入数据集上同时执行相同程序的多线程组，以产生输出数据集。 CTA中的每个线程都有一个唯一的标识符（线程ID），可以在线程启动时分配，并控制线程处理行为的各个方面，例如每个线程处理的输入数据集的部分，部分由每个线程产生的输出数据集合和/或线程之间的中间结果的共享。在SIMD并行执行线程组的情况下，并行生成并分配同一SIMD组中的线程的线程ID，从而允许快速连续启动不同的SIMD组。

2. 发明授权

US07865894B1 Distributing processing tasks within a processor 有权
标题翻译：在处理器中分配处理任务
公开(公告)号：US07865894B1
公开(公告)日：2011-01-04
申请号：US11311997
申请日：2005-12-19
申请人： Bryon S. Nordquist , John R. Nickolls
发明人： Bryon S. Nordquist , John R. Nickolls
IPC分类号： G06F9/46
CPC分类号： G06F9/5044
摘要： Embodiments of the present invention facilitate distributing processing tasks within a processor. In one embodiment, processing clusters keep track of resource requirements. If sufficient resources are available within a particular processing cluster, the available processing cluster asserts a ready signal to a dispatch unit. The dispatch unit is configured to pass a processing task (such as a cooperative thread array or CTA) to an available processing cluster that asserted a ready signal. In another embodiment, a processing task is passed around a ring of processing clusters until a processing cluster with sufficient resources available accepts the processing task.
摘要翻译：本发明的实施例便于在处理器内分发处理任务。在一个实施例中，处理集群跟踪资源需求。如果在特定处理集群内有足够的资源可用，则可用的处理集群将向就绪信号发出准备好的信号。调度单元被配置为将处理任务（诸如协作线程数组或CTA）传递到断言就绪信号的可用处理簇。在另一个实施例中，处理任务围绕处理集群环传递，直到具有足够资源的处理集群接受处理任务为止。

3. 发明授权

US09223578B2 Coalescing memory barrier operations across multiple parallel threads 有权
标题翻译：在多个并行线程之间合并记忆障碍操作
公开(公告)号：US09223578B2
公开(公告)日：2015-12-29
申请号：US12887081
申请日：2010-09-21
申请人： John R. Nickolls , Steven James Heinrich , Brett W. Coon , Michael C. Shebanow
发明人： John R. Nickolls , Steven James Heinrich , Brett W. Coon , Michael C. Shebanow
IPC分类号： G06F9/46 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/30087 , G06F9/3851
摘要： One embodiment of the present invention sets forth a technique for coalescing memory barrier operations across multiple parallel threads. Memory barrier requests from a given parallel thread processing unit are coalesced to reduce the impact to the rest of the system. Additionally, memory barrier requests may specify a level of a set of threads with respect to which the memory transactions are committed. For example, a first type of memory barrier instruction may commit the memory transactions to a level of a set of cooperating threads that share an L1 (level one) cache. A second type of memory barrier instruction may commit the memory transactions to a level of a set of threads sharing a global memory. Finally, a third type of memory barrier instruction may commit the memory transactions to a system level of all threads sharing all system memories. The latency required to execute the memory barrier instruction varies based on the type of memory barrier instruction.
摘要翻译：本发明的一个实施例提出了一种用于在多个并行线程之间聚合存储器屏障操作的技术。来自给定并行线程处理单元的存储器屏障请求被合并以减少对系统其余部分的影响。此外，存储器屏障请求可以指定针对其提交内存事务的一组线程的级别。例如，第一类型的存储器障碍指令可以将存储器事务提交到共享L1（一级）高速缓存的一组协作线程的级别。第二种类型的存储器障碍指令可以将存储器事务提交到共享全局存储器的一组线程的级别。最后，第三种类型的存储器障碍指令可以将存储器事务提交到共享所有系统存储器的所有线程的系统级。执行存储器屏障指令所需的延迟基于存储器屏障指令的类型而变化。

4. 发明申请

US20120110586A1 THREAD GROUP SCHEDULER FOR COMPUTING ON A PARALLEL THREAD PROCESSOR 有权
标题翻译：用于并行螺纹加工器的螺纹组合调度器
公开(公告)号：US20120110586A1
公开(公告)日：2012-05-03
申请号：US13247819
申请日：2011-09-28
申请人： Brett W. Coon , John R. Nickolls , John Erik Lindholm , Robert J. Stoll , Nicholas Wang , Jack Hilaire Choquette , Kathleen Elliott Nickolls
发明人： Brett W. Coon , John R. Nickolls , John Erik Lindholm , Robert J. Stoll , Nicholas Wang , Jack Hilaire Choquette , Kathleen Elliott Nickolls
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F2209/483
摘要： A parallel thread processor executes thread groups belonging to multiple cooperative thread arrays (CTAs). At each cycle of the parallel thread processor, an instruction scheduler selects a thread group to be issued for execution during a subsequent cycle. The instruction scheduler selects a thread group to issue for execution by (i) identifying a pool of available thread groups, (ii) identifying a CTA that has the greatest seniority value, and (iii) selecting the thread group that has the greatest credit value from within the CTA with the greatest seniority value.
摘要翻译：并行线程处理器执行属于多个协作线程数组（CTA）的线程组。在并行线程处理器的每个周期，指令调度器在随后的周期中选择要发行的线程组以执行。指令调度器通过（i）识别可用线程组的池，（ii）识别具有最大资历值的CTA来选择要执行的线程组，以及（iii）选择具有最大信用值的线程组从具有最高资历价值的CTA内。

5. 发明授权

US07809928B1 Generating event signals for performance register control using non-operative instructions 有权
标题翻译：使用非操作指令生成用于性能寄存器控制的事件信号
公开(公告)号：US07809928B1
公开(公告)日：2010-10-05
申请号：US11313872
申请日：2005-12-20
申请人： Roger L. Allen , Brett W. Coon , Ian A. Buck , John R. Nickolls
发明人： Roger L. Allen , Brett W. Coon , Ian A. Buck , John R. Nickolls
IPC分类号： G06F9/30 , G06F17/00 , G09G5/02
CPC分类号： G06T1/20 , G06F9/30072 , G06F9/30076 , G06F11/3466 , G06F2201/86 , G06F2201/865 , G06F2201/88
摘要： One embodiment of an instruction decoder includes an instruction parser configured to process a first non-operative instruction and to generate a first event signal corresponding to the first non-operative instruction, and a first event multiplexer configured to receive the first event signal from the instruction parser, to select the first event signal from one or more event signals and to transmit the first event signal to an event logic block. The instruction decoder may be implemented in a multithreaded processing unit, such as a shader unit, and the occurrences of the first event signal may be tracked when one or more threads are executed within the processing unit. The resulting event signal count may provide a designer with a better understanding of the behavior of a program, such as a shader program, executed within the processing unit, thereby facilitating overall processing unit and program design.
摘要翻译：指令解码器的一个实施例包括：指令解析器，被配置为处理第一非操作指令并产生对应于第一非操作指令的第一事件信号;以及第一事件多路复用器，被配置为从指令接收第一事件信号解析器，以从一个或多个事件信号中选择第一事件信号，并将第一事件信号发送到事件逻辑块。指令解码器可以在诸如着色器单元的多线程处理单元中实现，并且当在处理单元内执行一个或多个线程时，可以跟踪第一事件信号的出现。所得到的事件信号计数可以使设计者更好地理解在处理单元内执行的诸如着色器程序之类的程序的行为，从而有助于整体处理单元和程序设计。

6. 发明授权

US07640284B1 Bit reversal methods for a parallel processor 有权
标题翻译：并行处理器的位反转方法
公开(公告)号：US07640284B1
公开(公告)日：2009-12-29
申请号：US11424514
申请日：2006-06-15
申请人： Nolan D. Goodnight , John R. Nickolls
发明人： Nolan D. Goodnight , John R. Nickolls
IPC分类号： G06F17/14
CPC分类号： G06F17/142 , G06F7/76
摘要： Parallelism in a processor is exploited to permute a data set based on bit reversal of indices associated with data points in the data set. Permuted data can be stored in a memory having entries arranged in banks, where entries in different banks can be accessed in parallel. A destination location in the memory for a particular data point from the data set is determined based on the bit-reversed index associated with that data point. The bit-reversed index can be further modified so that at least some of the destination locations determined by different parallel processes are in different banks, allowing multiple points of the bit-reversed data set to be written in parallel.
摘要翻译：处理器中的并行性被利用以基于与数据集中的数据点相关联的索引的位反转来置换数据集。被许可的数据可以存储在具有排列在存储体中的条目的存储器中，其中可以并行地访问不同存储体中的条目。基于与该数据点相关联的位反转索引来确定来自数据集的用于特定数据点的存储器中的目的地位置。可以进一步修改位反转索引，使得由不同并行进程确定的至少一些目的地位置在不同的存储体中，允许并行写入位反转数据集的多个点。

7. 发明申请

US20090240895A1 SYSTEMS AND METHODS FOR COALESCING MEMORY ACCESSES OF PARALLEL THREADS 有权
标题翻译：用于并行线程的存储器访问的系统和方法
公开(公告)号：US20090240895A1
公开(公告)日：2009-09-24
申请号：US12054330
申请日：2008-03-24
申请人： Lars Nyland , John R. Nickolls , Gentaro Hirota , Tanmoy Mandal
发明人： Lars Nyland , John R. Nickolls , Gentaro Hirota , Tanmoy Mandal
IPC分类号： G06F12/00
CPC分类号： G06F9/3824 , G06F9/3851 , G06F9/3885 , G06F9/3891
摘要： One embodiment of the present invention sets forth a technique for efficiently and flexibly performing coalesced memory accesses for a thread group. For each read application request that services a thread group, the core interface generates one pending request table (PRT) entry and one or more memory access requests. The core interface determines the number of memory access requests and the size of each memory access request based on the spread of the memory access addresses in the application request. Each memory access request specifies the particular threads that the memory access request services. The PRT entry tracks the number of pending memory access requests. As the memory interface completes each memory access request, the core interface uses information in the memory access request and the corresponding PRT entry to route the returned data. When all the memory access requests associated with a particular PRT entry are complete, the core interface satisfies the corresponding application request and frees the PRT entry.
摘要翻译：本发明的一个实施例提出了一种用于有效且灵活地执行线程组合的存储器访问的技术。对于为线程组服务的每个读取应用程序请求，核心接口生成一个未决请求表（PRT）条目和一个或多个内存访问请求。核心接口基于应用程序请求中的存储器访问地址的扩展来确定存储器访问请求的数量和每个存储器访问请求的大小。每个存储器访问请求指定存储器访问请求服务的特定线程。 PRT条目跟踪挂起的内存访问请求的数量。当存储器接口完成每个存储器访问请求时，核心接口使用存储器访问请求中的信息和对应的PRT条目来路由返回的数据。当与特定PRT条目相关联的所有存储器访问请求完成时，核心接口满足相应的应用请求并释放PRT条目。

8. 发明授权

US07477091B2 Defect tolerant redundancy 有权
标题翻译：缺陷容错冗余
公开(公告)号：US07477091B2
公开(公告)日：2009-01-13
申请号：US11105326
申请日：2005-04-12
申请人： John R. Nickolls
发明人： John R. Nickolls
IPC分类号： G06F11/16
CPC分类号： G11C29/848
摘要： Circuits, methods, and apparatus for using redundant circuitry on integrated circuits in order to increase manufacturing yields. One exemplary embodiment of the present invention provides a circuit configuration wherein functional circuit blocks in a group of circuit blocks are selected by multiplexers. Multiplexers at the input and output of the group of circuit blocks steer input and output signals to and from functional circuit blocks, avoiding circuit blocks found to be defective or nonfunctional. Multiple groups of these circuit blocks may be arranged in series and in parallel. Alternate multiplexer configurations may be used in order to provide a higher level of redundancy. Other embodiments use all functional circuit blocks and sort integrated circuits based on the level of functionality or performance. Other embodiments provide methods of testing integrated circuits having one or more of these circuit configurations.
摘要翻译：用于在集成电路上使用冗余电路的电路，方法和装置，以增加制造产量。本发明的一个示例性实施例提供一种电路配置，其中一组电路块中的功能电路块由多路复用器选择。电路组输入和输出的多路复用器将输入和输出信号转换到功能电路块和从功能电路块输出，避免电路块发现有故障或无功能。这些电路块的多组可以串联和并联布置。可以使用替代多路复用器配置以提供更高级别的冗余。其他实施例使用所有功能电路块并且基于功能或性能的级别对集成电路进行分类。其他实施例提供了测试具有这些电路配置中的一个或多个的集成电路的方法。

9. 发明授权

US07456835B2 Register based queuing for texture requests 有权
标题翻译：基于注册排队的纹理请求
公开(公告)号：US07456835B2
公开(公告)日：2008-11-25
申请号：US11339937
申请日：2006-01-25
申请人： John Erik Lindholm , John R. Nickolls , Simon S. Moy , Brett W. Coon
发明人： John Erik Lindholm , John R. Nickolls , Simon S. Moy , Brett W. Coon
IPC分类号： G06T11/40 , G06T15/00 , G06T1/00 , G09G5/00
CPC分类号： G06T11/60 , G09G5/363
摘要： A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture request buffer queues the relatively small texture commands and parameters. Additionally, for each queued texture command, an associated set of texture arguments, which are typically much larger than the texture command, are stored in a general purpose register. The texture unit retrieves texture commands from the texture request buffer and then fetches the associated texture arguments from the appropriate general purpose register. The texture arguments may be stored in the general purpose register designated as the destination of the final texture value computed by the texture unit. Because the destination register must be allocated for the final texture value as texture commands are queued, storing the texture arguments in this register does not consume any additional registers.
摘要翻译：图形处理单元可以排队大量纹理请求，以平衡纹理请求的可变性，而不需要大的纹理请求缓冲区。专用纹理请求缓冲区排队相对较小的纹理命令和参数。另外，对于每个排队的纹理命令，通常比纹理命令大得多的一组相关的纹理参数存储在通用寄存器中。纹理单元从纹理请求缓冲区中检索纹理命令，然后从相应的通用寄存器获取相关的纹理参数。纹理参数可以存储在指定为由纹理单元计算的最终纹理值的目的地的通用寄存器中。因为当纹理命令排队时，必须为目标寄存器分配最终纹理值，所以将纹理参数存储在该寄存器中不消耗任何其他寄存器。

10. 发明授权

US07313583B2 Galois field arithmetic unit for use within a processor 有权
标题翻译：用于处理器内的伽罗瓦域算术单元
公开(公告)号：US07313583B2
公开(公告)日：2007-12-25
申请号：US10460599
申请日：2003-06-12
申请人： Joshua Porten , Won Kim , Scott D. Johnson , John R. Nickolls
发明人： Joshua Porten , Won Kim , Scott D. Johnson , John R. Nickolls
IPC分类号： G06F15/00 , H03M13/00
CPC分类号： G06F7/724
摘要： A Galois field arithmetic unit includes a Galois field multiplier section and a Galois field adder section. The Galois field multiplier section includes a plurality of Galois field multiplier arrays that perform a Galois field multiplication by multiplying, in accordance with a generating polynomial, a 1st operand and a 2nd operand. The bit size of the 1st and 2nd operands correspond to the bit size of a processor data path, where each of the Galois field multiplier arrays performs a portion of the Galois field multiplication by multiplying, in accordance with a corresponding portion of the generating polynomial, corresponding portions of the 1st and 2nd operands. The bit size of the corresponding portions of the 1st and 2nd operands corresponds to a symbol size of symbols of a coding scheme being implemented by the corresponding processor.
摘要翻译：伽罗瓦域算术单元包括伽罗瓦域乘法器部分和伽罗瓦域加法器部分。伽罗瓦域乘法器部分包括多个伽罗瓦域乘法器阵列，其通过根据生成多项式乘以第1和第2操作数和第2和/ >操作数。 1 ^{和 nd / / SUP>操作数的位大小对应于处理器数据路径的位大小，其中Galois域乘法器阵列中的每一个执行Galois的一部分根据生成多项式的对应部分乘以1＆lt; S＆gt;和2＆lt; nd＆gt;操作数的对应部分进行场乘法运算。第1和第2和第2操作数的对应部分的位大小对应于由对应的处理器实现的编码方案的符号的符号大小。}

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