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1. 发明授权

US08331512B2 Phase control block for managing multiple clock domains in systems with frequency offsets 有权
标题翻译：用于在具有频率偏移的系统中管理多个时钟域的相位控制块
公开(公告)号：US08331512B2
公开(公告)日：2012-12-11
申请号：US12225999
申请日：2007-04-04
申请人： Hae-Chang Lee , Jared LeVan Zerbe , Carl William Werner
发明人： Hae-Chang Lee , Jared LeVan Zerbe , Carl William Werner
IPC分类号： H04L7/00
CPC分类号： H04L7/0278 , H03L7/0814 , H03L7/0816 , H03L7/0818 , H03L7/091 , H03L2207/50 , H04L7/0008 , H04L7/0016 , H04L7/0079 , H04L7/0087 , H04L7/033 , H04L7/0337 , H04L7/0338
摘要： A circuit for performing clock recovery according to a received digital signal (30). The circuit includes at least an edge sampler (105) and a data sampler (145) for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock (25) and data clock (20) signals offset in phase from one another to the respective clock inputs of the edge sampler (105) and the data sampler (145). The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.
摘要翻译：一种用于根据接收到的数字信号（30）执行时钟恢复的电路。该电路至少包括用于采样数字信号的边缘采样器（105）和数据采样器（145），以及时钟信号提供电路。时钟信号供应电路提供边缘时钟（25）和数据时钟（20）信号，其相位偏移到边缘采样器（105）和数据采样器（145）的相应时钟输入。时钟信号供给电路可操作以选择性地改变边缘和数据时钟信号之间的相位偏移。

2. 发明授权

US08995598B2 Low jitter clock recovery circuit 有权
标题翻译：低抖动时钟恢复电路
公开(公告)号：US08995598B2
公开(公告)日：2015-03-31
申请号：US13312773
申请日：2011-12-06
申请人： Carl William Werner
发明人： Carl William Werner
IPC分类号： H03D3/24 , H04L7/033 , H03D13/00 , H03L7/07 , H03L7/081 , H03L7/087 , H03L7/091 , H03L7/089
CPC分类号： H04L7/0331 , H03D13/004 , H03L7/07 , H03L7/081 , H03L7/087 , H03L7/0891 , H03L7/091 , H04L7/033
摘要： A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase shifter responsive to a control signal based on this phase difference adjusts the phase of an incoming clock signal to yield a second clock signal. The phase difference between the first clock signal and the second clock signal is measured and the resulting signal is low-pass filtered to derive a control signal for controlling the VCO. The phase locked loop including the VCO filters out jitter.
摘要翻译：时钟恢复电路包括用于测量来自压控振荡器（VCO）的第一时钟信号与数据信号之间的相位差的第一相位检测器。基于该相位差响应于控制信号的移相器调整输入时钟信号的相位以产生第二时钟信号。测量第一时钟信号和第二时钟信号之间的相位差，并将所得到的信号进行低通滤波，以得到用于控制VCO的控制信号。包括VCO的锁相环滤除抖动。

3. 发明授权

US08774337B2 Phase control block for managing multiple clock domains in systems with frequency offsets 有权
标题翻译：用于在具有频率偏移的系统中管理多个时钟域的相位控制块
公开(公告)号：US08774337B2
公开(公告)日：2014-07-08
申请号：US13710404
申请日：2012-12-10
申请人： Hae-Chang Lee , Jared LeVan Zerbe , Carl William Werner
发明人： Hae-Chang Lee , Jared LeVan Zerbe , Carl William Werner
IPC分类号： H04L7/02
CPC分类号： H04L7/0278 , H03L7/0814 , H03L7/0816 , H03L7/0818 , H03L7/091 , H03L2207/50 , H04L7/0008 , H04L7/0016 , H04L7/0079 , H04L7/0087 , H04L7/033 , H04L7/0337 , H04L7/0338
摘要： A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.
摘要翻译：用于根据接收到的数字信号30执行时钟恢复的电路。该电路至少包括用于对数字信号进行采样的边缘采样器105和数据采样器145以及时钟信号提供电路。时钟信号供应电路提供边缘时钟25和数据时钟20信号，其相位偏移到边缘采样器105和数据采样器145的相应时钟输入。时钟信号供应电路可操作以选择性地改变相位偏移边沿和数据时钟信号。

4. 发明申请

US20130195234A1 Phase Control Block for Managing Multiple Clock Domains in Systems with Frequency Offsets 有权
公开(公告)号：US20130195234A1
公开(公告)日：2013-08-01
申请号：US13710404
申请日：2012-12-10
申请人： Hae-Chang Lee , Jared LeVan Zerbe , Carl William Werner
发明人： Hae-Chang Lee , Jared LeVan Zerbe , Carl William Werner
IPC分类号： H04L7/00
CPC分类号： H04L7/0278 , H03L7/0814 , H03L7/0816 , H03L7/0818 , H03L7/091 , H03L2207/50 , H04L7/0008 , H04L7/0016 , H04L7/0079 , H04L7/0087 , H04L7/033 , H04L7/0337 , H04L7/0338
摘要： A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.

5. 发明授权

US08498344B2 Frequency responsive bus coding 有权
标题翻译：频率响应总线编码
公开(公告)号：US08498344B2
公开(公告)日：2013-07-30
申请号：US12999495
申请日：2009-06-18
申请人： John M. Wilson , Aliazam Abbasfar , John Eble, III , Lei Luo , Jade M. Kizer , Carl William Werner , Wayne Dettloff
发明人： John M. Wilson , Aliazam Abbasfar , John Eble, III , Lei Luo , Jade M. Kizer , Carl William Werner , Wayne Dettloff
IPC分类号： H04B3/00 , H04L25/00
CPC分类号： H04L25/49 , H04L25/4915
摘要： A data system 102 permits bus encoding based on frequency of the bus; an encoding scheme may be implemented to avoid undesirable frequency conditions such as a resonant condition that may lead to degradation in system performance. The device or integrated circuit will typically include an encoder; in one embodiment, the encoder is a data bus inversion (DBI) circuit that selectively inverts all lines of a data bus. A detector that may include a band-pass or stop-band filter that, for example, evaluates data for transmission on the bus to detect frequency, for example, a predetermined frequency or a frequency range. The detector provides a control signal for the encoder to selectively apply an encoding scheme as a function of frequency.
摘要翻译：数据系统102允许基于总线频率的总线编码; 可以实现编码方案以避免不期望的频率条件，例如可能导致系统性能下降的共振条件。设备或集成电路通常将包括编码器; 在一个实施例中，编码器是选择性地反转数据总线的所有行的数据总线反相（DBI）电路。可以包括带通或阻带滤波器的检测器，其例如评估用于在总线上传输的数据以检测频率，例如预定频率或频率范围。检测器为编码器提供控制信号，以选择性地应用作为频率的函数的编码方案。

6. 发明申请

US20120200325A1 LOW JITTER CLOCK RECOVERY CIRCUIT 审中-公开
标题翻译：低抖动时钟恢复电路
公开(公告)号：US20120200325A1
公开(公告)日：2012-08-09
申请号：US13312773
申请日：2011-12-06
申请人： Carl William Werner
发明人： Carl William Werner
IPC分类号： H03L7/06
CPC分类号： H04L7/0331 , H03D13/004 , H03L7/07 , H03L7/081 , H03L7/087 , H03L7/0891 , H03L7/091 , H04L7/033
摘要： A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase shifter responsive to a control signal based on this phase difference adjusts the phase of an incoming clock signal to yield a second clock signal. The phase difference between the first clock signal and the second clock signal is measured and the resulting signal is low-pass filtered to derive a control signal for controlling the VCO. The phase locked loop including the VCO filters out jitter.
摘要翻译：时钟恢复电路包括用于测量来自压控振荡器（VCO）的第一时钟信号与数据信号之间的相位差的第一相位检测器。基于该相位差响应于控制信号的移相器调整输入时钟信号的相位以产生第二时钟信号。测量第一时钟信号和第二时钟信号之间的相位差，并将所得到的信号进行低通滤波，以得到用于控制VCO的控制信号。包括VCO的锁相环滤除抖动。

7. 发明授权

US08085893B2 Low jitter clock recovery circuit 有权
标题翻译：低抖动时钟恢复电路
公开(公告)号：US08085893B2
公开(公告)日：2011-12-27
申请号：US11225559
申请日：2005-09-13
申请人： Carl William Werner
发明人： Carl William Werner
IPC分类号： H03D3/24
CPC分类号： H04L7/0331 , H03D13/004 , H03L7/07 , H03L7/081 , H03L7/087 , H03L7/0891 , H03L7/091 , H04L7/033
摘要： A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase shifter responsive to a control signal based on this phase difference adjusts the phase of an incoming clock signal to yield a second clock signal. The phase difference between the first clock signal and the second clock signal is measured and the resulting signal is low-pass filtered to derive a control signal for controlling the VCO. The phase locked loop including the VCO filters out jitter.
摘要翻译：时钟恢复电路包括用于测量来自压控振荡器（VCO）的第一时钟信号与数据信号之间的相位差的第一相位检测器。基于该相位差响应于控制信号的移相器调整输入时钟信号的相位以产生第二时钟信号。测量第一时钟信号和第二时钟信号之间的相位差，并将所得到的信号进行低通滤波，以得到用于控制VCO的控制信号。包括VCO的锁相环滤除抖动。

8. 发明申请

US20110127990A1 FREQUENCY RESPONSIVE BUS CODING 有权
标题翻译：频率响应总线编码
公开(公告)号：US20110127990A1
公开(公告)日：2011-06-02
申请号：US12999495
申请日：2009-06-18
申请人： John M. Wilson , Aliazam Abbasfar , John Eble, III , Lei Luo , Jade M. Kizer , Carl William Werner , Wayne Dettloff
发明人： John M. Wilson , Aliazam Abbasfar , John Eble, III , Lei Luo , Jade M. Kizer , Carl William Werner , Wayne Dettloff
IPC分类号： G01R23/165
CPC分类号： H04L25/49 , H04L25/4915
摘要： A data system 102 permits bus encoding based on frequency of the bus; an encoding scheme may be implemented to avoid undesirable frequency conditions such as a resonant condition that may lead to degradation in system performance. The device or integrated circuit will typically include an encoder; in one embodiment, the encoder is a data bus inversion (DBI) circuit that selectively inverts all lines of a data bus. A detector that may include a band-pass or stop-band filter that, for example, evaluates data for transmission on the bus to detect frequency, for example, a predetermined frequency or a frequency range. The detector provides a control signal for the encoder to selectively apply an encoding scheme as a function of frequency.
摘要翻译：数据系统102允许基于总线频率的总线编码; 可以实现编码方案以避免不期望的频率条件，例如可能导致系统性能下降的共振条件。设备或集成电路通常将包括编码器; 在一个实施例中，编码器是选择性地反转数据总线的所有行的数据总线反相（DBI）电路。可以包括带通或阻带滤波器的检测器，其例如评估用于在总线上传输的数据以检测频率，例如预定频率或频率范围。检测器为编码器提供控制信号，以选择性地应用作为频率的函数的编码方案。

9. 发明申请

US20090310667A1 PHASE CONTROL BLOCK FOR MANAGING MULTIPLE CLOCK DOMAINS IN SYSTEMS WITH FREQUENCY OFFSETS 有权
标题翻译：用于在具有频率偏移的系统中管理多个时钟域的相位控制块
公开(公告)号：US20090310667A1
公开(公告)日：2009-12-17
申请号：US12225999
申请日：2007-04-04
申请人： Hae-Chang Lee , Jared LeVan Zerbe , Carl William Werner
发明人： Hae-Chang Lee , Jared LeVan Zerbe , Carl William Werner
IPC分类号： H04L7/00 , H04L27/01
CPC分类号： H04L7/0278 , H03L7/0814 , H03L7/0816 , H03L7/0818 , H03L7/091 , H03L2207/50 , H04L7/0008 , H04L7/0016 , H04L7/0079 , H04L7/0087 , H04L7/033 , H04L7/0337 , H04L7/0338
摘要： A circuit for performing clock recovery according to a received digital signal (30). The circuit includes at least an edge sampler (105) and a data sampler (145) for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock (25) and data clock (20) signals offset in phase from one another to the respective clock inputs of the edge sampler (105) and the data sampler (145). The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.
摘要翻译：一种用于根据接收到的数字信号（30）执行时钟恢复的电路。该电路至少包括用于采样数字信号的边缘采样器（105）和数据采样器（145），以及时钟信号提供电路。时钟信号供应电路提供边缘时钟（25）和数据时钟（20）信号，其相位偏移到边缘采样器（105）和数据采样器（145）的相应时钟输入。时钟信号供应电路可操作以选择性地改变边缘和数据时钟信号之间的相位偏移。

10. 发明授权

US07308044B2 Technique for receiving differential multi-PAM signals 有权
标题翻译：接收差分多PAM信号的技术
公开(公告)号：US07308044B2
公开(公告)日：2007-12-11
申请号：US10673677
申请日：2003-09-30
申请人： Jared LeVan Zerbe , Grace Tsang , Mark Horowitz , Bruno Werner Garlepp , Carl William Werner
发明人： Jared LeVan Zerbe , Grace Tsang , Mark Horowitz , Bruno Werner Garlepp , Carl William Werner
IPC分类号： H04L27/06
CPC分类号： H04L25/4917
摘要： A technique for receiving differential multi-PAM signals is disclosed. In one particular exemplary embodiment, the technique may be realized as a differential multi-PAM extractor circuit. In this particular exemplary embodiment, the differential multi-PAM extractor circuit comprises an upper LSB sampler circuit configured to receive a differential multi-PAM input signal and a first differential reference signal, and to generate a first differential sampled output signal. The differential multi-PAM extractor circuit also comprises a lower LSB sampler circuit configured to receive the differential multi-PAM input signal and a second differential reference signal, and to generate a second differential sampled output signal. The differential multi-PAM extractor circuit further comprises a combiner circuit configured to receive the first differential sampled output signal and the second differential sampled output signal, and to generate a differential LSB output signal indicating an LSB value of the differential multi-PAM input signal.
摘要翻译：公开了一种用于接收差分多PAM信号的技术。在一个特定的示例性实施例中，该技术可以被实现为差分多PAM提取器电路。在该特定示例性实施例中，差分多PAM提取器电路包括被配置为接收差分多PAM输入信号和第一差分参考信号的高LSB采样器电路，并且产生第一差分采样输出信号。差分多PAM提取器电路还包括被配置为接收差分多PAM输入信号和第二差分参考信号的低LSB采样器电路，并且产生第二差分采样输出信号。差分多PAM提取器电路还包括组合器电路，其被配置为接收第一差分采样输出信号和第二差分采样输出信号，并且产生指示差分多PAM输入信号的LSB值的差分LSB输出信号。

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