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1. 发明授权

US07483346B2 Digital disk read/write device 有权
标题翻译：数字磁盘读/写设备
公开(公告)号：US07483346B2
公开(公告)日：2009-01-27
申请号：US11292543
申请日：2005-12-02
申请人： Cedric Bertholom , Jean-Michel Goiran
发明人： Cedric Bertholom , Jean-Michel Goiran
IPC分类号： G11B7/00
CPC分类号： G11B7/126 , G11B7/123 , G11B20/10 , G11B20/14
摘要： A device for reading from and/or writing on a rotating disk including a mobile opto-electromechanical device placed above the disk and connected to a motherboard via a set of electric wires. The opto-electromechanical device includes actuators, a laser diode, photodetectors, and an electronic circuit, each photodetector providing the electronic circuit with an analog electric signal proportional to the received light signal, the electronic circuit controlling the diode and the actuators. The electronic circuit comprises an analog-to-digital converter digitizing the analog electric signals coming from the photodetectors and transmitting the digitized signals to a digital processing unit providing data of alignment of the opto-electromechanical device with respect to the disk, and a reference clock signal having its period substantially corresponding to a multiple or to a sub-multiple of the time period corresponding to the overflight by the opto-electromechanical device of a bit of the disk.
摘要翻译：一种用于在旋转盘上读取和/或写入包括移动的光电机电装置的装置，该装置放置在盘的上方并通过一组电线连接到母板。光电机械装置包括致动器，激光二极管，光电检测器和电子电路，每个光电检测器为电子电路提供与接收的光信号成比例的模拟电信号，控制二极管和致动器的电子电路。电子电路包括对来自光电检测器的模拟电信号进行数字化的模数转换器，并将数字化信号传输到数字处理单元，该数字处理单元提供光机电装置相对于盘的对准数据，以及参考时钟信号的周期基本上对应于由光盘的光电机电装置对应于飞越的时间段的倍数或次倍数。

2. 发明授权

US09449672B2 DRAM memory interface 有权
标题翻译： DRAM存储器接口
公开(公告)号：US09449672B2
公开(公告)日：2016-09-20
申请号：US14343352
申请日：2012-09-06
申请人： Cedric Bertholom
发明人： Cedric Bertholom
IPC分类号： G06F13/00 , G06F13/12 , G11C11/406 , G11C5/06 , G11C7/02 , G11C7/10 , G11C11/4093 , G11C11/402
CPC分类号： G11C11/40615 , G11C5/063 , G11C7/02 , G11C7/1048 , G11C7/1057 , G11C7/1084 , G11C11/4023 , G11C11/4093
摘要： It is proposed a DRAM memory interface (40) for transmitting signals between a memory controller device (50) and a DRAM memory device (52). The DRAM memory interface comprises: data lines (44) for transmitting data signals; one or more control line(s) for transmitting control signals; one or more address line(s) for transmitting address signals; for each line, a transmitter device (41) connected to a first end of the line and a receiver device (42) connected to a second end of the line; wherein: each line is a single ended line wherein a signal transmitted on the line is referenced to a first reference voltage line (46); and—each line has an termination (Z1, Z2) on both the first and second ends of the line by connecting a first impedance (Z1) to the first end of the line and a second impedance (Z2) to the second end of the line.
摘要翻译：提出了一种用于在存储器控制器设备（50）和DRAM存储器件（52）之间传输信号的DRAM存储器接口（40）。 DRAM存储器接口包括：用于发送数据信号的数据线（44）用于发送控制信号的一个或多个控制线; 用于发送地址信号的一个或多个地址线; 对于每条线路，连接到线路的第一端的发射机设备（41）和连接到该线路的第二端的接收机设备（42）其中：每条线是单端线，其中在该线上发送的信号参考第一参考电压线（46）; 并且 - 每条线通过将第一阻抗（Z1）连接到线路的第一端并且将第二阻抗（Z2）连接到线路的第二端，在线路的第一和第二端上具有终端（Z1，Z2）线。

3. 发明申请

US20140201436A1 DRAM Memory Interface 有权
标题翻译： DRAM存储器接口
公开(公告)号：US20140201436A1
公开(公告)日：2014-07-17
申请号：US14343352
申请日：2012-09-06
申请人： Cedric Bertholom
发明人： Cedric Bertholom
IPC分类号： G11C11/406 , G11C11/402
CPC分类号： G11C11/40615 , G11C5/063 , G11C7/02 , G11C7/1048 , G11C7/1057 , G11C7/1084 , G11C11/4023 , G11C11/4093
摘要： It is proposed a DRAM memory interface (40) for transmitting signals between a memory controller device (50) and a DRAM memory device (52). The DRAM memory interface comprises: data lines (44) for transmitting data signals; one or more control line(s) for transmitting control signals; one or more address line(s) for transmitting address signals; for each line, a transmitter device (41) connected to a first end of the line and a receiver device (42) connected to a second end of the line; wherein: each line is a single ended line wherein a signal transmitted on the line is referenced to a first reference voltage line (46); and —each line has an termination (Z1, Z2) on both the first and second ends of the line by connecting a first impedance (Z1) to the first end of the line and a second impedance (Z2) to the second end of the line.
摘要翻译：提出了一种用于在存储器控制器设备（50）和DRAM存储器件（52）之间传输信号的DRAM存储器接口（40）。 DRAM存储器接口包括：用于发送数据信号的数据线（44）用于发送控制信号的一个或多个控制线; 用于发送地址信号的一个或多个地址线; 对于每条线路，连接到线路的第一端的发射机设备（41）和连接到该线路的第二端的接收机设备（42）其中：每条线是单端线，其中在该线上发送的信号参考第一参考电压线（46）; 并且 - 每条线路通过将第一阻抗（Z1）连接到线路的第一端并且将第二阻抗（Z2）连接到线路的第二端，在线路的第一端和第二端上具有终端（Z1，Z2）线。

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